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Some legacy RGMII phys don't have in band signaling for the
speed information. so set the RGMII MAC mode according to
the speed got from PHY.
Signed-off-by: Roy Zang <[email protected]>
Reported-by: John Traill <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Delete all occurrences of hang() and provide a generic function.
Signed-off-by: Andreas Bießmann <[email protected]>
Acked-by: Albert ARIBAUD <[email protected]>
[trini: Modify check around puts() in hang.c slightly]
Signed-off-by: Tom Rini <[email protected]>
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log2 of the device block size serves as the shift value used to calculate
the block number to read in file systems when implementing avaiable block
sizes.
It is needed quite often in file systems thus it is pre-calculated and
stored in the block device descriptor.
Signed-off-by: Egbert Eich <[email protected]>
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The number 512 appears quite a bit in the mmc code. Add a constant for this
so that it can be used here and in other parts of the code (e.g. SPL code
which loads from mmc).
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Vadim Bendebury <[email protected]>
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block_read returns unsigned long, so it doesn't make sense to check for
< 0. and neither does marking the header structure as const and then
casting away the constness to load data into it.
Also cleanup some unneeded pointer casting while we're at it.
Signed-off-by: Peter Korsgaard <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Support Xilinx Zynq i2c controller.
Signed-off-by: Joe Hershberger <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Add support for SD, MMC and eMMC card on Xilinx Zynq.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Autodetect phy if phyaddress is setup to -1.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Avoid overwriting GEMx_RCLK_CTRL and GEMx_CLK_CTRL
if the Ethernet interface is connect on EMIO
Do not enable emio for this standard board configuration for now.
Signed-off-by: David Andrey <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Pass the PHY address to the driver init to
allow parallel use of both interfaces
Signed-off-by: David Andrey <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The whole driver used 100Mbps because of zc702 rev B.
Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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BDs can be correctly setup just once and init function
performs only phy autodetection and enabling RX/TX.
RX/TX are disabled in halt function.
This patch solves the problem with repeatable tftp transfers.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Remove one return from the code.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Removing this bit causes that frame is sent only once.
(With wrap big one packet has been sent several times
which dramatically decrease throughput)
TRM: (Table 16-3: Tx Buffer Descriptor Entry)
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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This phy is used on zedboard (xilinx zynq platform).
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Watchdog can be used on Microblaze, PPC and Zynq hw designs.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Add an mxc_ocotp driver for i.MX6.
Signed-off-by: Benoît Thébaudeau <[email protected]>
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Add a fsl_iim driver common to i.MX and MPC.
Signed-off-by: Benoît Thébaudeau <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
Acked-by: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
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This will be used by the i.MX6 NAND support.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
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The following headers are moved to a i.MX common location:
- regs-common.h
- regs-apbh.h
- regs-bch.h
- regs-gpmi.h
- dma.h
This way this header can be re-used also by other i.MX platforms.
For example the i.MX6 which will need it for the upcoming NAND
support.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
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Support to check whether the SD3.0 or not.
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Tested-by: Rommel Custodio <[email protected]>
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eMMC vesrion is supported up to v4.5.
But bootloader isn't saw the exact eMMC version.
After applied this patch,
if use the mmcinfo command, then can see the exactly mmc version.
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Acked-by: Rommel Custodio <[email protected]>
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Rework the waiting for transfer completion loop condition
to continue waiting until both Transfer Complete and DMA End
interrupts occur. Checking of DLA bit in Present State register
looks not needed in addition to interrupts status checking,
so it can be removed from the condition. Also, DMA Error
condition is added to the list of data errors, checked in the loop.
Signed-off-by: Andrew Gabbasov <[email protected]>
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The cache should invalidate the read buffer for
the SD card interface after the transfer complete,
not command-complete.
Tested-by: Andrew Gabbasov <[email protected]>
Signed-off-by: Eric Nelson <[email protected]>
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The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas re-introduced by
commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling).
Actually the glitch is happening due to always toggling between slave mode
and master mode by configuring the CHANNEL_MODE bits in this reset function.
Since the spi driver only supports master mode, set the mode for all channels
always to master mode in order to have a stable, "glitch-free" SPI clock line.
Signed-off-by: Fabio Estevam <[email protected]>
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Add a driver for the I2C TPM from Infineon.
Signed-off-by: Che-Liang Chiou <[email protected]>
Signed-off-by: Rong Chang <[email protected]>
Signed-off-by: Tom Wai-Hong Tam <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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When building for the Sandbox version, the casts in this change are
necessary to avoid compilation issues.
Signed-off-by: Taylor Hutt <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Conflicts:
drivers/video/exynos_fb.c
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This reverts commit 239cb9d904cfa8ab50d840a47b3306189d695c75.
Signed-off-by: Stefan Roese <[email protected]>
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This reverts commit 81a4f7098ba137ea1961cb997ca16d57de2b3483.
Signed-off-by: Stefan Roese <[email protected]>
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If CONFIG_NAND_ECC_BCH is set use 4-bit error correction code instead of
the 1-bit error correction code on the NAND device.
Signed-off-by: Gerlando Falauto <[email protected]>
Signed-off-by: Holger Brunck <[email protected]>
cc: Valentin Longchamp <[email protected]>
cc: Prafulla Wadaskar <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Acked-by: Scott Wood <[email protected]>
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Following the removal of the smdk6400 board, the s3c64xx SoC becomes unused, so
remove associated code. It will still be possible to restore it later from the
Git history if necessary.
Signed-off-by: Benoît Thébaudeau <[email protected]>
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This also fixes support for mx31pdk and tx25, which had been broken by commit
e05e5de7fae5bec79617e113916dac6631251156.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Acked-by: Scott Wood <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
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The syndrome functions should use the page number passed as argument instead of
the page number saved upon NAND_CMD_READ0.
This does not make any difference if the NAND_NO_AUTOINCR option is set, but
otherwise this fixes accesses to the wrong pages.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Acked-by: Scott Wood <[email protected]>
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The page number indicated in the debug trace of mxc_nand_read_oob_syndrome() did
not match the page being worked on.
By the way, replace the GCC-specific __FUNCTION__ with __func__.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Acked-by: Scott Wood <[email protected]>
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Signed-off-by: Benoît Thébaudeau <[email protected]>
Acked-by: Scott Wood <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
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Add some abstraction to NFC definitions so that some parts of the current code
can also be used for future i.MX5 code.
Clean up a few things by the way.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Acked-by: Scott Wood <[email protected]>
Tested-by: Fabio Estevam <[email protected]>
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Currently is_16bit_nand() is a per SoC function and it decides the bus nand
width by reading some boot related registers.
This method works when NAND is the boot medium, but does not work if another
boot medium is used. For example: booting from a SD card and then using NAND
to store the environment variables, would lead to the following error:
NAND bus width 16 instead 8 bit
No NAND device found!!!
0 MiB
Use CONFIG_SYS_NAND_BUSWIDTH_16BIT symbol to decide the bus width.
If it is defined in the board file, then consider 16-bit NAND bus-width,
otherwise assume 8-bit NAND is used.
This also aligns with Documentation/devicetree/bindings/mtd/nand.txt, which
states:
nand-bus-width : 8 or 16 bus width if not present 8
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Scott Wood <[email protected]>
Reviewed-by: Benoît Thébaudeau <[email protected]>
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Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT option so that other NAND controller
drivers could use it when a 16-bit NAND is deployed.
drivers/mtd/nand/ndfc has CONFIG_SYS_NDFC_16BIT, so just rename it, so that
other NAND drivers could reuse the same symbol.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Scott Wood <[email protected]>
Reviewed-by: Benoît Thébaudeau <[email protected]>
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The prints are out of control. SILENCE!
Signed-off-by: Joe Hershberger <[email protected]>
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The unwind code was not reversing operations correctly and was causing
a hang on any error condition.
Signed-off-by: Joe Hershberger <[email protected]>
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Support for NAND storage devices to work with the DFU framework.
Signed-off-by: Pantelis Antoniou <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Acked-by: Scott Wood <[email protected]>
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We make these two functions take a size_t pointer to how much space
was used on NAND to read or write the buffer (when reads/writes happen)
so that bad blocks can be accounted for. We also make them take an
loff_t limit on how much data can be read or written. This means that
we can now catch the case of when writing to a partition would exceed
the partition size due to bad blocks. To do this we also need to make
check_skip_len count not just complete blocks used but partial ones as
well. All callers of nand_(read|write)_skip_bad are adjusted to call
these with the most sensible limits available.
The changes were started by Pantelis and finished by Tom.
Signed-off-by: Pantelis Antoniou <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Previously we didn't support upload/download larger than available
memory. This is pretty bad when you have to update your root filesystem
for example.
This patch removes that limitation (and the crashes when you transfered
any file larger than 4MB) by making raw image writes be done in chunks
and making file maximum size be configurable.
The sequence number is a 16 bit counter; make sure we handle rollover
correctly. This fixes the wrong transfers for large (> 256MB) images.
Also utilize a variable to handle initialization, so that we don't rely
on just the counter sent by the host.
Signed-off-by: Pantelis Antoniou <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Following commit:
"cmd_ext4: BREAK and correct ext4write parameter order"
SHA1:0171d52c410cbaa9290b1b214e695697c835bfe5
introduced cleanup of ext4write semantics to be consistent with other
filesystem's writing commands (e.g. fatwrite).
This commit provides correct ext4write command generation at DFU eMMC
code.
Signed-off-by: Lukasz Majewski <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
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