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This patch builds upon the recently introduced CBMEM console
feature of coreboot.
CBMEM console uses a memry area allocated by coreboot to store
the console output. The memory area has a certain structure,
which allows to determine where the buffer is, the buffer size
and the location of the pointer in the buffer. This allows
different phases of the firmware (rom based coreboot, ram based
coreboot, u-boot after relocation with this change) to keep
adding text to the same buffer.
Note that this patch introduces a new console driver and adds the
driver to the list of drivers to be used for console output, i.e.
it engages only after u-boot relocates. Usiong CBMEM console for
capturing the pre-relocation console output will be done under a
separate change.
>From Linux, run the cbmem.py utility (which is a part of the coreboot
package) to see the output, e.g.:
vvvvvvvvvvvvvvvvv
SCSI: AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode
flags: 64bit ilck stag led pmp pio
...
Magic signature found
Kernel command line: "cros_secure quiet loglevel=1 console=tty2...
^^^^^^^^^^^^^^^^^
Note that the entire u-boot output fits into the buffer only if
the coreboot log level is reduced from the most verbose. Ether
the buffer size will have to be increased, or the coreboot
verbosity permanently reduced.
Signed-off-by: Vadim Bendebury <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
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On kzm9g board (rmobile SoC), autoboot fails if serial console cable is not
connected. When serial cable is not connected, serial error occurs and
some garbage comes in data register.
sh_serial_tstc() in serial_sh.c does not check error status and misunderstand
there is some input data. It is the reason that autoboot fails.
This patch adds checking error status in sh_serial_tstc().
This patch is based on v2013.01-rc1 tag of u-boot master git.
Signed-off-by: Tetsuyuki Kobayashi <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.
Signed-off-by: Yuanquan Chen <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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At some point, a confusion arose about the use of the bit
definitions in host_caps for bus widths, and the value
in ext_csd. By coincidence, a simple shift could convert
between one and the other:
MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0
MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1
MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2
However, as host_caps is a bitmask of supported things,
there is not, in fact, a one-to-one correspondence. host_caps
is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical
things were happening where we would try to set the bus width
to 12.
The new code clarifies the very different namespaces:
host_caps/card_caps = bitmask (MMC_MODE_*)
ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*)
mmc->bus_width integer number of bits (1, 4, 8)
We create arrays to map between the namespaces, like in Linux.
Signed-off-by: Andy Fleming <[email protected]>
Tested-by: Jaehoon Chung <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In
some cases (e.g. user load commands) this cannot be guaranteed by callers
of the MMC APIs. To solve this, modify the Tegra MMC driver to use the
new bounce_buffer_*() APIs.
Note: Ideally, all U-Boot code will always provide address- and size-
aligned buffers, so a bounce buffer will only ever be needed for user-
supplied buffers (e.g. load commands). Ensuring this removes the need
for performance-sucking bounce buffer cache management and memcpy()s.
The one known exception at present is the SCR buffer in sd_change_freq(),
which is only 8 bytes long. Solving this requires enhancing struct
mmc_data to know the difference between buffer size and transferred data
size, or forcing all callers of mmc_send_cmd() to have allocated buffers
using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not
enforced in any way at present, and so cannot be assumed by the core MMC
code.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The current bouncebuf API requires all parameters to be passed to both
bounce_buffer_start() and bounce_buffer_stop(). Modify the bouncebuf
start function to accept a state structure as a parameter, and only
require that state struct to be passed to the stop function. This
simplifies usage of the bounce buffer by clients.
Don't modify the data pointer, but rather store the temporary buffer in
this state struct. The bouncebuf code ensures that client code can
always use a single buffer pointer in the state structure, irrespective
of whether a bounce buffer actually had to be allocated.
Move cache management logic into the bounce buffer code, so that each
client doesn't have to duplicate this. I believe there's no need to
invalidate the buffer before a DMA operation, since flushing the cache
should prevent any write-backs.
Update the MXS MMC driver for this change.
Signed-off-by: Stephen Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Bring in the code from Linux kernel.
Added to Linux kernel by:
commit e08c1694d9e2138204f2b79b73f0f159074ce2f5
Author: Andres Salomon <[email protected]>
Date: Fri Jul 4 10:00:03 2008 -0700
Some HW balks when writing both voltage setting and power up at the same
time to SDHCI_POWER_CONTROL register.
Signed-off-by: Rommel G Custodio <[email protected]>
CC: Andy Fleming <[email protected]>
v2: fix attribution and SOB
Signed-off-by: Andy Fleming <[email protected]>
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The interpretation of the data returned by the MMC_CMD_ALL_SEND_CID
command was incorrect with respect to the JEDEC Standard No. 84-A441.
This change makes the interpretation correct with respect to the
defined fields of the CID register.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Taylor Hutt <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Support DesignWare MMC Controller for Samsung Specific.
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Rajeshawari Shinde <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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usbdescriptors.h conflicts with linux/usb/ch9.h
Remove it.
Signed-off-by: Pantelis Antoniou <[email protected]>
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This patch adds a NAND Flash torture feature, which is useful as a block stress
test to determine if a block is still good and reliable (or should be marked as
bad), e.g. after a write error.
This code is ported from mtd-utils' lib/libmtd.c.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
[[email protected]: removed unnec. ifdef and unwrapped error strings]
Signed-off-by: Scott Wood <[email protected]>
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NAND Flash is erased by blocks, not by pages.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
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This patch cleans up nand_util.c:
- Fix tabs.
- Fix typos.
- Remove space character before opening parenthesis in function calls.
- Fix comments.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
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Use a flag instead of a hard-coded macro so that sub-page reads can be
enabled in other cases (such as on-die ecc).
This is the same as a5ff4f102937a3492bca4a9ff0c341d78813414c in Linux
Signed-off-by: Joe Hershberger <[email protected]>
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IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for
SRAM i.e. "byte select" is not supported. Hence Read Modify Write is
implemented in IFC for any "system side write" into sram buffer. Reading an
uninitialized memory results in ECC Error from sram wrapper.
Hence we must initialize/prefill SRAM buffer by any data before writing
anything in SRAM from system side. To initialize SRAM user can use "READID"
NAND command with read bytes equal to SRAM size. It will be a one time
activity post boot
Signed-off-by: Prabhakar Kushwaha <[email protected]>
[[email protected]: fix fsl_ifc_sram_init prototype]
Signed-off-by: Scott Wood <[email protected]>
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These controllers can only do hardware ECC on full page transfers.
Signed-off-by: Scott Wood <[email protected]>
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Document parameters used for specifying the NAND image to be loaded.
Also fix the definition of CONFIG_SPL_NAND_SIMPLE -- it's only
nand_spl_simple.c, not the entire nand directory. The word "simple" is
there for a reason. :-)
Signed-off-by: Scott Wood <[email protected]>
---
v2: updated for makefile changes earlier in patchset
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Some small SPLs do not use nand_base.c, and a subset of those also
require a special driver. Some SPLs need software ECC but others can't
fit it.
All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these
symbols added to preserve existing behavior.
Signed-off-by: Scott Wood <[email protected]>
--
v2: use positive logic for including bits of NAND, rather than
a MINIMAL symbol that excludes things.
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It's arch code and not a driver, so move it where it belongs. When it
originally went into drivers/misc there was no 8xxx CPU directory.
This will make new-SPL support a little easier since we can keep the CPU
stuff together and not need to pull stuff in from drivers/misc.
Signed-off-by: Scott Wood <[email protected]>
Cc: Andy Fleming <[email protected]>
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TEMT is set when the transmitter is totally empty and all output has
finished.
This prevents output problems (including a loss of synchronization
observed on p2020 that persisted for quite a while) if SPL has output
still on its way out.
Signed-off-by: Scott Wood <[email protected]>
--
v2: fixed typo in subject, and explained what the bit does in the changelog
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CONFIG_NS16550_MIN_FUNCTIONS is used by small SPLs to gain access to basic
ns16550 output code without pulling in things not needed by the SPL.
This previously only worked with non-MULTI configs. Recently MULTI was
made mandatory, and MIN_FUNCTIONS fails like this:
drivers/serial/libserial.o: In function `calc_divisor.clone.0':
serial_ns16550.c:(.text.calc_divisor.clone.0+0x24): undefined reference to `get_bus_freq'
drivers/serial/libserial.o: In function `_serial_getc':
(.text._serial_getc+0x30): undefined reference to `NS16550_getc'
drivers/serial/libserial.o: In function `_serial_tstc':
(.text._serial_tstc+0x30): undefined reference to `NS16550_tstc'
drivers/serial/libserial.o: In function `_serial_setbrg':
(.text._serial_setbrg+0x3c): undefined reference to `NS16550_reinit'
make[1]: *** [/tmp/u-boot/spl/u-boot-spl] Error 1
make: *** [/tmp/u-boot/spl/u-boot-spl.bin] Error 2
With MIN_FUNCTIONS we don't need anything from this file, so don't build
it. The conditional needs to be in the file itself rather than the
makefile, because the config symbols are only imported to the makefiles
once, not separately for the SPL phase of the build.
Signed-off-by: Scott Wood <[email protected]>
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By commit c7e3b2b5, this was chanded to support multiple controllers.
But this has missing of parenthesis. This commit fix it.
-----
r8a66597-hcd.c: In function ‘usb_lowlevel_init’:
r8a66597-hcd.c:911:52: error: expected declaration specifiers before ‘)’
token
r8a66597-hcd.c:935:1: error: expected ‘=’, ‘,’, ‘;’, ‘asm’ or‘__attribute__’ before ‘{’ token
r8a66597-hcd.c:939:1: error: expected ‘{’ at end of input
-----
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
CC: Lucas Stach <[email protected]>
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Some variables are initialized with a value defined by macro.
This was changed to use the macro directly. And the variable not to
use deleted it.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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Backend driver for MUSB OTG controllers found on TI OMAP2/3/4
(tested only on OMAP3 Beagle).
Signed-off-by: Ilya Yanok <[email protected]>
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Backend driver for MUSB OTG controllers found on TI AM35x.
It seems that on AM35X interrupt status registers can be updated
_before_ core registers. As we don't use true interrupts in U-Boot
and poll interrupt status registers instead this can result in
interrupt handler being called with non-updated core registers.
This confuses the code and result in hanged transfers.
Add a small delay in am35x_interrupt as a workaround.
Signed-off-by: Ilya Yanok <[email protected]>
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Backend driver for MUSB OTG controllers found on TI AM33xx and
TI81xx SoCs (tested with AM33xx only).
Signed-off-by: Ilya Yanok <[email protected]>
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Existing U-Boot musb driver has no support for the new gadget framework
and also seems to have other limitations. As gadget framework is ported
from Linux it seems pretty natural to port musb gadget driver as well.
This driver supports both host and peripheral modes.
This is not a replacement for current musb driver (at least now) as
there are still some consumers of the old UDC interface.
No DMA operation support included, CONFIG_MUSB_PIO_ONLY should be
defined.
Virtual root hub device is not implemented.
Known problems: with no devices connected usb_lowlevel_start() fails.
Signed-off-by: Ilya Yanok <[email protected]>
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Linux usb/ch9.h seems to have all the same information (and more)
as usbdescriptors.h so use the former instead of the later one.
As a consequense of this change USB_SPEED_* values don't correspond
directly to EHCI speed encoding anymore, I've added necessary
recoding in EHCI driver. Also there is no point to put speed into
pipe anymore so it's removed and a bunch of host drivers fixed to
look at usb_device->speed instead.
Old usbdescriptors.h included is not removed as it seems to be
used by old USB device code.
This makes usb.h and usbdevice.h incompatible. Fortunately the
only place that tries to include both are the old MUSB code and
it needs usb.h only for USB_DMA_MINALIGN used in aligned attribute
on musb_regs structure but this attribute seems to be unneeded
(old MUSB code doesn't support any DMA at all).
Signed-off-by: Ilya Yanok <[email protected]>
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Signed-off-by: Ilya Yanok <[email protected]>
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If a board has all 8 data lines routed, the SD/MMC controller can still
operate in 4-bit (or presumably even 1-bit) mode. Adjust Tegra's MMC
driver to report the 4-bit capability even for 8-bit slots.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Add support for CONSOLE_MUX to tegra-kbc driver. This requires
adding a flag to struct keyb to know the driver has already been
initialized so if we try to initialize it again we can just return
success. Also call into iomux_doenv() from drv_keyboard_init to
re-evaluate the stdin string.
Signed-off-by: Allen Martin <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Add support for selecting the required cache mode for the LCD:
off, write-through or write-back.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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This driver supports driving a single LCD and providing a U-Boot console
on it.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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The correct bit for H1_PM is 16, not 8, which is the DP pull-up impedance
selection bit.
This issue has been reported by Eric Bénard <[email protected]> and fixed by
Christoph Fritz <[email protected]> on Linux, from which these #define-s
had been copied.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Marek Vasut <[email protected]>
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The correct bit for H1_PM is 16, not 8, which is the DP pull-up impedance
selection bit.
This issue has been reported by Michael Burkey <[email protected]> and fixed by
Christoph Fritz <[email protected]> on Linux, from which these #define-s
had been copied.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Marek Vasut <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Measuring the spi clock line on a scope shows a 'glitch' during the reset of the
spi.
Fix this by toggling only the MXC_CSPICTRL_EN bit, so that the clock line becomes
always stable.
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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In decode_cs() function the polarity of the chip select must be taken into
account.
Also, for the case of low active chip select, the CS was activated too early.
Signed-off-by: Fabio Estevam <[email protected]>
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A custom board_ehci_hcd_init() may be unneeded, so add a weak default
implementation doing nothing.
By the way, use simple __weak from linux/compiler.h for
board_ehci_hcd_postinit() instead of weak alias with full attribute.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
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Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
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Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare
to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at
SoC level.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
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Use EHCI MXC configuration options for i.MX25.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Matthias Weisser <[email protected]>
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Make EHCI power and overcurrent polarities configurable. If not set, these new
configurartions keep the default register values so that existing board files
do not have to be changed.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
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The i.MX53 has MXC_H*_UCTRL_H*_OC_DIS_BIT bits to disable the oc pin.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
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The MXC_*_UCTRL_*PM_BIT bits are available only on i.MX51.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
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MXC_OTG_UCTRL_OPM_BIT disables (masks) the power/oc pins if set, like
MXC_H1_UCTRL_H1PM_BIT and MXC_H2_UCTRL_H2PM_BIT, not the opposite.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
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