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greth.c: In function ‘greth_recv’:
greth.c:507:3: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘unsigned int’ [-Wformat]
greth.c:507:3: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘unsigned int’ [-Wformat]
greth.c:541:6: warning: pointer targets in assignment differ in signedness [-Wpointer-sign]
greth.c: In function ‘greth_initialize’:
greth.c:623:2: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
greth.c:655:3: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
greth.c:684:2: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘struct greth_regs *’ [-Wformat]
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Daniel Hellstrom <[email protected]>
Cc: [email protected]
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In board_nand_init() we only need the 'tmp' variable if MXC_NFC_V2_1 is
defined.
Signed-off-by: Tom Rini <[email protected]>
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Use the same IP revisions as in Linux in order to make the comparison more
clear.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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Merge mxc_setup_config1() into board_nand_init() in order to ease the addition
of i.MX5 support in the following patches.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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mxc_nand_read_page_raw_syndrome() should reenable ECC upon exit. This fixes ECC
errors left uncorrected after a call to this function.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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Use _mxc_nand_enable_hwecc() instead of duplicating its code.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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On the NFC IP 1.1, the 32-bit ecc_status_result value comes from 2
consecutive 16-bit registers. This patch reads all the fields of this value,
which makes a difference for 4-kiB NF pages.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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This patches fixes the TODO to use same register definitions in mtd mxc_nand and
nand_spl fsl nfc drivers.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Scott Wood <[email protected]>
Cc: Stefano Babic <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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This is based on Linux kernel -next:
commit 14f44abf1dafc20ba42ce8616a8fc8fbd1b3712b
Author: Brian Norris <[email protected]>
Date: Fri Jul 13 09:28:24 2012 -0700
mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set from driver
The NAND_CHIPOPTIONS_MSK has limited utility and is causing real bugs. It
silently masks off at least one flag that might be set by the driver
(NAND_NO_SUBPAGE_WRITE). This breaks the GPMI NAND driver and possibly
others.
Really, as long as driver writers exercise a small amount of care with
NAND_* options, this mask is not necessary at all; it was only here to
prevent certain options from accidentally being set by the driver. But the
original thought turns out to be a bad idea occasionally. Thus, kill it.
Note, this patch fixes some major gpmi-nand breakage.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Brian Norris <[email protected]>
Cc: Eric Nelson <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Scott Wood <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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Micron NAND flash (e.g. MT29F4G08ABADAH4) BLOCK LOCK READ STATUS is not
the same as others. Instead of bit 1 being lock, it is #lock_tight.
To make the driver support either format, ignore bit 1 and use only
bit 0 and bit 2.
Signed-off-by: Joe Hershberger <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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NAND_CMD_ constants for lock/unlock should be in the header
Signed-off-by: Joe Hershberger <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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Missed in previous cleanup.
Signed-off-by: Joe Hershberger <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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NAND unlock command allows an invert bit to be set to unlock all but
the selected page range.
Signed-off-by: Joe Hershberger <[email protected]>
[[email protected]: updated docs and added comment about invert bit]
Signed-off-by: Scott Wood <[email protected]>
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With onfi a flash is organized into one or more logical units (LUNs).
A logical unit (LUN) is the minimum unit that can independently execute
commands and report status.
Mtd does not exploit LUN, so make it see a big single flash where size is
lun_size * number_of_lun.
Without this patch MT29F8G08ADBDAH4 size is 512MiB instead of 1GiB.
Artem: split long line on 2 shorter ones.
This is commit 637957551c0ac80de8dfc7650d320c5a98c2c0c0 from Linux
Signed-off-by: Matthieu Castet <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
Signed-off-by: Artem Bityutskiy <[email protected]>
Signed-off-by: David Woodhouse <[email protected]>
[[email protected]: picked from Linux into U-Boot]
Reported-by: Rafael Beims <[email protected]>
Signed-off-by: Scott Wood <[email protected]>
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Using common spi flash operation function to replace private operation
funtion
Signed-off-by: Bo Shen <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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Add atmel at25df321 serial flash support
Signed-off-by: Bo Shen <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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enable.
Before the patch, it looks like:
|U-Boot 2012.07-00441-gd578d6f-dirty (Sep 10 2012 - 16:11:06)
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|CPU: AT91SAM9G35
|Crystal frequency: 12 MHz
|CPU clock : 400 MHz
|Master clock : 133.333 MHz
|DRAM: 128 MiB
|WARNING: Caches not enabled
> |NAND: Initialize PMECC params, cap: 2, sector: 512
> |256 MiB
|MMC: mci: 0
|In: serial
|Out: serial
|Err: serial
|Net: macb0
|Hit any key to stop autoboot: 0
After the patch:
|U-Boot 2012.07-00441-gd578d6f-dirty (Sep 10 2012 - 16:18:11)
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|CPU: AT91SAM9G35
|Crystal frequency: 12 MHz
|CPU clock : 400 MHz
|Master clock : 133.333 MHz
|DRAM: 128 MiB
|WARNING: Caches not enabled
> |NAND: 256 MiB
| ... ...
|Hit any key to stop autoboot: 0
Signed-off-by: Josh Wu <[email protected]>
Signed-off-by: Andreas Bießmann <[email protected]>
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Warning is:
xilinx_spi.c: In function 'spi_setup_slave':
xilinx_spi.c:81: warning: unused variable 'regs'
Signed-off-by: Stephan Linz <[email protected]>
CC: Michal Simek <[email protected]>
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Initialize all possible uartlites and return the first
initialized port. For static configuration is initialization
done in userial_ports array.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Stephan Linz <[email protected]>
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Use CONFIG parameters only at one location to simplify
the code. Also create ace_readw/writew functions.
Signed-off-by: Michal Simek <[email protected]>
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With Simon Glass's include/nand.h alignment changes, some mxs builds
were generating errors. Fix is to ensure asm/cache.h is included before
linux/mtd/nand.h. Moving common.h to top of include list does that.
Signed-off-by: Tom Warren <[email protected]>
Acked-by: Simon Glass <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.
Upcoming Tegra30 port will use common code/defines/names where possible.
Signed-off-by: Tom Warren <[email protected]>
Acked-by: Stephen Warren <[email protected]>
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Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT
bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such
devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set.
Note that the Linux kernel enables access to boot partitions solely based
on the value of EXT_CSD_BOOT_MULT; EXT_CSD_PARTITIONING_SUPPORT only
influences access to "general" partitions.
eMMC devices affected by this issue exist on various NVIDIA Tegra
platforms (and presumably many others too), such as Harmony (plug-in eMMC),
Seaboard, Springbank, and Whistler (plug-in eMMC).
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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A device tree is used to configure the NAND, including memory
timings and block/pages sizes.
If this node is not present or is disabled, then NAND will not
be initialized.
Signed-off-by: Jim Lin <[email protected]>
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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The NAND layer needs to use cache-aligned buffers by default. Towards this
goal. align the default buffers and their members according to the minimum
DMA alignment defined for the architecture.
Signed-off-by: Simon Glass <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
Acked-by: Scott Wood <[email protected]>
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There were a couple of drivers that were actually using the flags
field of the cmd structure, despite the fact that no one ever
*set* that field. When we removed the field, those drivers failed
to compile. Replaced the references with the correct usage of
resp_type.
Signed-off-by: Andy Fleming <[email protected]>
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This patch prevents dcache-related problem. The problem manifested
itself on the SPI driver, this is just a port to the MMC driver.
The scenario is the same. In case an "mmc read" is issued to a
buffer which was written right before it and data cache is enabled,
the cache eviction might happen during the DMA transfer into the
buffer, therefore corrupting the buffer. Clear any cache lines that
might contain the buffer to prevent such issue.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Stefano Babic <[email protected]>
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It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Stefano Babic <[email protected]>
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This patch fixes dcache-related problem. The problem manifested
when dcache was enabled and the following command issued twice:
mw 0x42000000 0 0x4000 ; sf probe ; sf read 0x42000000 0x0 0x10000 ; sha1sum 0x42000000 0x10000
The SHA1 checksum was correct during the first call. Yet with
every subsequent call of the above command, it differed and was
wrong.
It turns out this was because of a race condition. On the first
time the command was called, no cacheline contained any data from
the destination memory location. The DMA transfered data into the
location and the cache above the location was invalidated. Then the
checksum was computed, but that meant the data were loaded into data
cache.
On any subsequent call, the DMA again transfered data into the same
destination. Yet during the transfer, some of the DCache lines were
evicted and written back into the main memory. Once the DMA transfer
completed, the data cache was invalidated over the memory location as
usual. But the data that were to be loaded back into the data cache
by subsequent SHA1 checksuming were corrupted.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Stefano Babic <[email protected]>
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Signed-off-by: Koen Kooi <[email protected]>
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Samsung SoC use the cmu control to set clock.
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Useless code is removed, and get buswidth value.
buswidth value will be used to choice the 4bit or 8bit.
(Now used 4bit mode in sdhci.c by default)
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Samsung SoC is broken busy waiting for R1b type.
And clk delay control value is modified the previosuly value.
(that value used at the s5p_mmc.c)
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Some boards have no Card Detect wired. In that case, set the CD test
bits in the standard interface.
Signed-off-by: Joe Hershberger <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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When setting up the clocks in the sdhci driver, the "spec version"
must be masked off. Otherwise any time the vendor version is not 0,
the check will allways assume the interface is version 3. This breaks
when the interface is actually version 1 or 2.
Signed-off-by: Joe Hershberger <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Andy Fleming <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT
bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such
devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set.
Note that the Linux kernel enables access to boot partitions solely based
on the value of EXT_CSD_BOOT_MULT; EXT_CSD_PARTITIONING_SUPPORT only
influences access to "general" partitions.
eMMC devices affected by this issue exist on various NVIDIA Tegra
platforms (and presumably many others too), such as Harmony (plug-in eMMC),
Seaboard, Springbank, and Whistler (plug-in eMMC).
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Since the type of "ext_csd" was array of char, the following
calculation might fail when the value of ext_csd[EXT_CSD_SEC_CNT]
was minus.
capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
| ext_csd[EXT_CSD_SEC_CNT + 1] << 8
| ext_csd[EXT_CSD_SEC_CNT + 2] << 16
| ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
So, this patch changes the type of "ext_csd" to array of u8.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The controller can control high capacity cards. So, the patch adds
the flag. If the flag is not set, "mmcinfo" will fail when a high
capacity card is used.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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(!timeout) condition check in mmc_send_status() can never be met,
because do-while loop ends up with negative timeout value, -1.
Fix the check to handle TIMEOUT case correctly.
Signed-off-by: Jongman Heo <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Signed-off-by: Stefano Babic <[email protected]>
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* 'master' of git://git.denx.de/u-boot-avr32:
net:macb: add line break
avr32:portmux: fix setup for macb1
avr32: Remove redundant LDSCRIPT definition
Signed-off-by: Wolfgang Denk <[email protected]>
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Without this patch we see annoying output like this:
---8<---
U-Boot> dhcp
macb1: PHY not foundmacb0: PHY present at 1
macb0: Starting autonegotiation...
--->8---
Signed-off-by: Andreas Bießmann <[email protected]>
cc: Joe Hershberger <[email protected]>
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The computation was not correct with low clock values: setting a 1MHz
clock would result in an overlap that would then configure a 25Mhz
clock.
This patch implements a correct computation method according to the
kirkwood functionnal spec. table 600 (Serial Memory Interface
Configuration Register).
Signed-off-by: Valentin Longchamp <[email protected]>
cc: Holger Brunck <[email protected]>
cc: Prafulla Wadaskar <[email protected]>
Acked-by: Prafulla Wadaskar <[email protected]>
Signed-off-by: Prafulla Wadaskar <[email protected]>
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Check for ctrlc() in operations that take time and loop over the flash
addresses.
In netconsole, tstc() is expensive. Only check once in a while to not
slow down the operation significantly.
Signed-off-by: Joe Hershberger <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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