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The DMA didn't work properly because the DMA descriptor wasn't
properly cleaned after it was used once. Also, the DMA_ENABLE bit
was enabled/disabled too late.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Andy Fleming <[email protected]>
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Large blocks (> 512b) shall be transfered via DMA to make
things a bit faster.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Andy Fleming <[email protected]>
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Move DMA and PIO data transfer parts into separate functions.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Andy Fleming <[email protected]>
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The DMA mode didn't properly configure the DMA_ENABLE bit in CTRL1.
Also, it was using SSP0 DMA channel for all SSP devices.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Andy Fleming <[email protected]>
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Signed-off-by: Otavio Salvador <[email protected]>
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As the register accessing mode is the same for all i.MXS SoCs we ought
to use 'mxs' prefix intead of 'mx28'.
Signed-off-by: Otavio Salvador <[email protected]>
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The DMA transfers happen only if the transfered data are larger
than 512 bytes. Otherwise PIO is used. This is a small speed
optimization.
The DMA transfer doesn't work if unaligned transfer is requested
due to the limitation of the DMA controller. This has to be fixed
by introducing generic bounce buffer. Therefore the DMA feature
is now disabled by default.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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Pull out all the PIO transfer logic into separate function,
so DMA can be added.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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This makes it easier to adapt for addition of DMA support.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Otavio Salvador <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Wolfgang Denk <[email protected]>
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Add at91sam9x5ek board support, this board support the following SoCs
AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35
Using at91sam9x5ek_nandflash to configure for the board
Now only supports NAND with software ECC boot up
Signed-off-by: Bo Shen <[email protected]>
[move MAINTAINERS entry to right place]
Signed-off-by: Andreas Bießmann <[email protected]>
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Signed-off-by: Marek Vasut <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: U-Boot DM <[email protected]>
Cc: Tom Rini <[email protected]>
Acked-by: Tom Rini <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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CPSW is an on-chip ethernet switch that is found on various SoCs from Texas
Instruments. This patch adds a simple driver (based on the Linux driver) for
this hardware module.
This patch also adds support to clean and flush dcache during packet send
and receive.
Changes by Sandhya: Added support to clean and flush dcache during packet
send/receive and added timeouts.
Signed-off-by: Cyril Chemparathy <[email protected]>
Signed-off-by: Chandan Nath <[email protected]>
Signed-off-by: Satyanarayana, Sandhya <[email protected]>
[Ilya: Cleaned cache handling, some style cleanup, some small
fixes, use of internal RAM for descriptors]
Signed-off-by: Ilya Yanok <[email protected]>
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also fix NS16550_init() as we need 16x divider
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Acked-by: Christian Riesch <[email protected]>
Tested-by: Christian Riesch <[email protected]>
Acked-by: Sughosh Ganu <[email protected]>
Tested-by: Sughosh Ganu <[email protected]>
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DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will
be in SPI flash and U-Boot image will be in MMC/SD card. SPL will
do the low level initialization and then loads the u-boot image
from MMC/SD card.
Define CONFIG_SPL_MMC_LOAD macro in the DA850/OMAP-L138
configuration file to enable this feature.
Tested-by: Christian Riesch <[email protected]>
Signed-off-by: Lad, Prabhakar <[email protected]>
Signed-off-by: Rajashekhara, Sudhakar <[email protected]>
Signed-off-by: Hadli, Manjunath <[email protected]>
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Various devices like EEPROMs require 2-byte address support to
be properly accessed. This patch adds this support for OMAP2/3/4
I2C controller driver.
I've tested it with EEPROM (16 bit address) and TPS65217 chip
(8 bit address) on TI Beaglebone board.
Unfortunately I don't have access to any compatible hardware
with 16bit data register so I can't test if those #ifdef
clauses really work.
CC: Tom Rini <[email protected]>
Signed-off-by: Ilya Yanok <[email protected]>
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This patch moves all bootcount implementations into a common
directory: drivers/bootcount. The generic bootcount driver
is now usable not only by powerpc platforms, but others as well.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Valentin Longchamp <[email protected]>
Cc: Christian Riesch <[email protected]>
Cc: Manfred Rudigier <[email protected]>
Cc: Mike Frysinger <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Reinhard Meyer <[email protected]>
Tested-by: Valentin Longchamp <[email protected]>
Tested-by: Christian Riesch <[email protected]>
Acked-by: Rob Herring <[email protected]>
Acked-by: Mike Frysinger <[email protected]>
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* 'sf' of git://git.denx.de/u-boot-blackfin:
sf: spansion: Add support for S25FL256S
sf: winbond: fix page_size
sf: stmicro: add support for N25Q128A
sf: stmicro: add support N25Q128 parts
sf: stmicro: support JEDEC standard two-byte signature
sf: winbond: add W25Q32
cmd_spi: remove superfluous semicolon
Signed-off-by: Wolfgang Denk <[email protected]>
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These are not supported as individual build targets, but instead
are supported by another target.
The dead p4040 defines in particular had bitrotted significantly.
Signed-off-by: Scott Wood <[email protected]>
Acked-by: Kumar Gala <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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The P3060 was cancelled before it went into production, so there's no point
in supporting it.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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We have a dedicated function for setting the node status now, so use it.
Also improve a comment and fix the type of the phandle variable.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Function fm_info_get_phy_address() returns the PHY address for a given
Fman port. This is handy when the MDIO code needs to fixup the Ethernet
nodes in the device tree to point to PHY nodes for a specific PHY address.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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P1015 is the same as P1011 and P1016 is the same as P1012 from software
point of view. They have different packages but share SVRs.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.
The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the master module, need to finish these processes:
1. Initialize the PCIE port and address space.
2. Set inbound PCIE windows covered slave's u-boot image stored in
master's NOR flash.
3. Set outbound windows in order to configure slave's registers
for the core's releasing.
4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
or "PCIE3" using the following command:
setenv bootmaster PCIE1
saveenv
Signed-off-by: Liu Gang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.
This has the following advantages:
1. No longer need to rebuild an image when change the SRIO port for
boot from SRIO, just rewrite the new RCW with selected port,
then the code will get the port information by reading new RCW.
2. It will be easier to support other boot location options, for
example, boot from PCIE.
Signed-off-by: Liu Gang <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Add support for Spansion S25FL256S SPI flash.
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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Commit a4ed3b6 "sf: inline data constants" modified winbond.c's page_size
from 256 to 4096. This prevents either/both of "sf write" writing the
correct data, or "sf read" from reading the correct data back.
This allows U-Boot running on Compulab Tegra to upgrade itself.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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commit 54652991
Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips
fixes a problem for Numonyx P33/P30 flashes for 256-Mbit, but this leads
to problems for smaller versions of this chip e.g. the 32Mbit version
with deviceid 0x16 on mgcoge. So move the code for this work around to
an own function and check previously manufacturer id and device id to
not break other flashes which don't need this work around.
Signed-off-by: Holger Brunck <[email protected]>
Signed-off-by: Heiko Schocher <[email protected]>
cc: Stefan Roese <[email protected]>
cc: Philippe De Muyter <[email protected]>
cc: Gerlando Falauto <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Erasing flash sectors protected with persistent protection bit (PPB)
mechanism on Spansion flash chips doesn't work. Add sector protection
status checking and sector lock and unlock commands to fix this.
Signed-off-by: Anatolij Gustschin <[email protected]>
Cc: Stefan Roese <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Support for DS1388 is added by extending the DS1337 driver. DS1388 is
similar to DS1337. The time registers are offset by 1 (due to support
for hundreds of seconds), and there is no century bit.
The configuration and trickle charge registers are also different.
Tested on hardware with Freescale P2010 and DS1388.
Signed-off-by: Kenth Eriksson <[email protected]>
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Signed-off-by: Michal Simek <[email protected]>
Acked-by: Mike Frysinger <[email protected]>
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Add support for Numonyx N25Q128A SPI flash.
Signed-off-by: Michal Simek <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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Adds support for Numonyx's N25Q128 SPI flash. These devices
are used on (among others) Avnet Spartan-6 LX9 micro-evaluation
boards. Tested with "sf" commands and CONFIG_ENV_IS_IN_SPI_FLASH.
Signed-off-by: Stephan Linz <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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There are more than the M25Pxx serial flashs that can be
used with the stmicro driver, for example: the M25PXxx or
N25Qxx serie. All these chips have burned in the original
stmicro manufacture id 0x20 together with a standard
two-byte signature.
In preperation to support all these chips the stmicro driver
have to decode the full two-byte signature.
Signed-off-by: Stephan Linz <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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SMDK EVT1 has a different Winbond part, added its part details
to the SPI flash table.
Signed-off-by: Abhilash Kesavan <[email protected]>
Signed-off-by: Rajeshwari Shinde <[email protected]>
Signed-off-by: Mike Frysinger <[email protected]>
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Renesas SH and R-Mobile set up device using PFC.
This provide the framework. Most codes were brought from linux kernel.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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The serial device of R8A7740 has the same structure as SH7372 of SH, etc.
Signed-off-by: Hideyuki Sano <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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The serial device of SH73A0 has the same structure as SH7372 of SH, etc.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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The patch "spi: tegra2: rename tegra2_spi.* to tegra_spi.*"
(sha1: edffa63d3d6e76991998789f9fcbaa483731ca65)
renamed tegra2_spi.c to tegra_spi.c
and the patch "Merge branch 'master' of git://git.denx.de/u-boot-microblaze"
(sha1: d978780b2e676c005460cd561f4f15b5220bdf49)
has wrongly resolved confict.
This patch fix it.
Signed-off-by: Michal Simek <[email protected]>
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* 'master' of git://git.denx.de/u-boot-i2c:
km/common: remove printfs for i2c deblocking code
CONFIG: SMDK5250: I2C: Enable I2C
I2C: Add support for Multi channel
I2C: Modify the I2C driver for EXYNOS5
I2C: Move struct s3c24x0_i2c to a common place.
EXYNOS: PINMUX: Add pinmux support for I2C
EXYNOS5: define EXYNOS5_I2C_SPACING
EXYNOS: Add I2C base address.
EXYNOS: CLK: Add i2c clock
mx6qsabrelite: add i2c multi-bus support
imx-common: add i2c.c for bus recovery support
i.mx53: add definition for I2C3_BASE_ADDR
i.mx: iomux-v3.c: move to imx-common directory
i.mx: iomux-v3.h: move to imx-common include directory
iomux-v3: remove include of mx6x_pins.h
mxc_i2c: finish adding CONFIG_I2C_MULTI_BUS support
mxc_i2c: add bus recovery support
mxc_i2c: prep work for multiple busses support
mxc_i2c: add i2c_regs argument to i2c_imx_stop
mxc_i2c: add retries
mxc_i2c: check for arbitration lost
mxc_i2c: change slave addr if conflicts with destination.
mxc_i2c: don't disable controller after every transaction
mxc_i2c: place i2c_reset code inline
mxc_i2c: place imx_start code inline
mxc_i2c: remove redundant read
mxc_i2c: combine i2c_imx_bus_busy and i2c_imx_trx_complete into wait_for_sr_state
mxc_i2c.c: code i2c_probe as a 0 length i2c_write
mxc_i2c: call i2c_imx_stop on error in i2c_read/i2c_write
mxc_i2c: create i2c_init_transfer
mxc_i2c: clear i2sr before waiting for bit
mxc_i2c: create tx_byte function
mxc_i2c: remove ifdef of CONFIG_HARD_I2C
mxc_i2c: fix i2c_imx_stop
i2c: deblock i2c bus also if accessed before realocation
Signed-off-by: Wolfgang Denk <[email protected]>
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* 'master' of git://git.denx.de/u-boot-microblaze:
microblaze: Wire up SPI driver
spi: microblaze: Adds driver for Xilinx SPI controller
microblaze: intc: Clear interrupt code
microblaze: Call serial multi initialization
microblaze: Move __udelay implementation
microblaze: Remove extern from board.c
microblaze: Wire up dts configuration
fdt: Add board specific dts inclusion
microblaze: Move individual board linker scripts to common script in cpu tree.
microblaze: Add gpio.h
microblaze: Add missing undefs for UBI and UBIFS
microblaze: Expand and correct configuration comments
microblaze: Enable ubi support
microblaze: Avoid compile error on systems without cfi flash
microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTION
Conflicts:
drivers/spi/Makefile
Signed-off-by: Wolfgang Denk <[email protected]>
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This adds multiple i2c channel support for I2C.
Signed-off-by: Alim Akhtar <[email protected]>
Signed-off-by: Rajeshwari Shinde <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This patch modifies the S3C I2C driver to suppport EXYNOS5.
The cahnges made to driver are as follows:
- I2C base address is passed as a parameter to many
functions to avoid multiple #ifdef
- Channel initialisation is moved to a commom funation
as it is required by i2c_init.
- Hardcoding for I2CCON_ACKGEN removed.
- Replaced printf with debug.
- Checkpatch issues resolved.
- Pinmux setting will be done in board/samsung/smdk5250/smdk5250.c
to avoid repeated setting of gpio lines, as it have multi bus support.
Signed-off-by: Alim Akhtar <[email protected]>
Signed-off-by: Doug Anderson <[email protected]>
Signed-off-by: Rajeshwari Shinde <[email protected]>
Acked-by: Simon Glass <[email protected]>
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struct s3c24x0_i2c is being moved to common local header file so that
the same can be used by s3c series and exynos series SoCs.
Signed-off-by: Alim Akhtar <[email protected]>
Signed-off-by: Doug Anderson <[email protected]>
Signed-off-by: Rajeshwari Shinde <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Signed-off-by: Troy Kisky <[email protected]>
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Signed-off-by: Troy Kisky <[email protected]>
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Add support for calling a function that will toggle the
SCL line to return the bus to idle condition.
The actual toggling function is added in a later patch.
Signed-off-by: Troy Kisky <[email protected]>
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Signed-off-by: Troy Kisky <[email protected]>
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This is prep work for CONFIG_I2C_MULTI_BUS.
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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