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Retry unexpected hardware errors. This
will not retry a received NAK.
Signed-off-by: Troy Kisky <[email protected]>
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No need to continue waiting if arbitration lost.
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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The i2c controller cannot be both master and slave in the
same transaction.
Signed-off-by: Troy Kisky <[email protected]>
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This helps in a multiple bus master environment which
is why I also added a wait for bus idle.
Signed-off-by: Troy Kisky <[email protected]>
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imx_reset is only referenced once so
move to that location.
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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imx_start is only referenced once so
move to that location.
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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wait_for_sr_state returns i2sr on success
so no need to read again.
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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wait_for_sr_state
Not using udelay gives a more accurate timeout. The current implementation of udelay
in imx-common does not seem to wait at all for a udelay(1).
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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V2: Added WATCHDOG_RESET as suggested by Marek Vasut
add error message when stop fails
mxc_i2c: code i2c_probe as a 0 length i2c_write
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Signed-off-by: Troy Kisky <[email protected]>
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Initial code of i2c_read and i2c_write
is identical, move to subroutine.
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Let's clear the sr register before waiting for
bit to be set, instead of clearing it after
hardware sets it. No real operational difference here,
but allows combining of i2c_imx_trx_complete and
i2c_imx_bus_busy in later patches.
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Use tx_byte function instead of having 3 copies
of the code.
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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This is always selected when CONFIG_I2C_MXC is
selected, so it adds no value.
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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Instead of clearing 2 bits, all the other
bits were set because '|=' was used instead
of '&='.
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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This is an improved version of the driver patch original
submitted by Graeme Smecher <[email protected]>
The changes are:
- remove hard coded Xilinx BSP defines (XPAR_SPI_*) and
use CONFIG_SYS_SPI_BASE from config.h instead
- add extensive register struct definitions
- remove offset calculation for register access and
use the new register struct instead
- move default SPI controller configuration from
spi_setup_slave() to spi_claim_bus()
- add spi_set_speed()
- insert SPI controller deactivation in spi_release_bus()
- protect while loops in spi_xfer() with counter / timeouts
- support SPI mode flags: LSB_FIRST, CPHA, CPOL, LOOP
Come from:
http://patchwork.ozlabs.org/patch/71797/
Signed-off-by: Stephan Linz <[email protected]>
Tested-by: Michal Simek <[email protected]>
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* 'next' of git://git.denx.de/u-boot:
MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
doc: cleanup - move board READMEs into respective board directories
net: sh_eth: add support for SH7757's GETHER
net: sh_eth: modify the definitions of regsiter
net: sh_eth: add SH_ETH_TYPE_ condition
net: sh_eth: clean up for the SH7757's code
net: fec_mxc: Fix MDC for xMII
net: fec_mxc: Fix setting of RCR for xMII
net: nfs: make NFS_TIMEOUT configurable
net: Inline the new eth_setenv_enetaddr_by_index function
net: allow setting env enetaddr from net device setting
net/designware: Consecutive writes to the same register to be avoided
CACHE: net: asix: Fix asix driver to work with data cache on
net: phy: micrel: make ksz9021 phy accessible
net: abort network initialization if the PHY driver fails
phylib: phy_startup() should return an error code on failure
net: tftp: fix type of block arg to store_block
Signed-off-by: Wolfgang Denk <[email protected]>
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SH7757 has 2 ETHERs and 2 GETHERs. This patch supports the SH7757's
GETHER. If CONFIG_SH_ETHER_USE_GETHER is defined using SH7757,
the driver handles the GETHER.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Acked-by: Nobuhiro Iwamatsu <[email protected]>
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The previous code had many similar definitions in each CPU.
This patch borrows from the sh_eth driver of Linux kernel.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Acked-by: Nobuhiro Iwamatsu <[email protected]>
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At the moment, the driver supports the following CPUs:
- GETHER (Gigabit Ethernet) : SH7763, SH7734
- ETHER (Fast Ethernet) : SH7724, SH7757
And the driver had the following "#if":
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
- Those are for GETHER
#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
- This is for ETHER
So, for clean up the code, this patch adds SH_ETH_TYPE_GETHER and
SH_ETH_TYPE_ETHER. And then, the patch modifies the above "#if".
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Acked-by: Nobuhiro Iwamatsu <[email protected]>
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The SH7757's ETHER can work using the SH7724's setting. So, the patch
modifies it.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Acked-by: Nobuhiro Iwamatsu <[email protected]>
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* 'master' of git://git.denx.de/u-boot-usb:
usb_storage: fix ehci driver max transfer size
smsc95xx: align buffers to cache line size
ehci-hcd: change debug() to printf() in case of errors
usb: check return value of submit_{control, bulk}_msg
usb: pass cache-aligned buffer to usb_get_descriptor()
ehci-hcd: fix external buffer cache handling
ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment
ehci-hcd: program asynclistaddr before every transfer
common.h: Introduce DEFINE_CACHE_ALIGN_BUFFER
ehci-omap: Do not call dcache_off from omap_ehci_hcd_init
Signed-off-by: Wolfgang Denk <[email protected]>
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* 'sf' of git://git.denx.de/u-boot-blackfin:
sf: spansion: inline useless id defines
sf: drop unused/duplicate command defines
Signed-off-by: Wolfgang Denk <[email protected]>
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No need for dedicated defines when these really only get used once.
Signed-off-by: Mike Frysinger <[email protected]>
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In an effort to unify the spi flash drivers further, drop all the
unused and/or duplicate command defines.
Signed-off-by: Mike Frysinger <[email protected]>
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The MDC signal is available on all xMII (i.e. 'not 7-wire') interfaces, so
mii_speed has to be set for all these interfaces, and not only for MII.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Stefano Babic <[email protected]>
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At least on i.MX25, the RMII mode did not work, which is fixed by this patch.
The MII_MODE bit of the FEC RCR register means xMII, i.e. 'not 7-wire', so set
it accordingly.
According to the xMII and 7-wire (aka GPSI) standards, full duplex should be
available on xMII, but not on 7-wire, so set FCE accordingly. The FEC may
support full duplex for 7-wire too, but the reference manual does not say that,
so avoid an invalid assumption. Actually, the choice between half and full
duplex also depends on the endpoint/switch/repeater configuration, so a config
option could be added for that, but there has been no need for it so far.
Signed-off-by: Benoît Thébaudeau <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Stefano Babic <[email protected]>
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Now that common code doesn't declare these as volatile, we don't need to
either anymore. This fixes the build warning:
bfin_mac.c: In function 'bfin_EMAC_recv':
bfin_mac.c:193:23: warning: assignment discards qualifiers from pointer target type
Signed-off-by: Mike Frysinger <[email protected]>
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Align buffers passed to the USB code to cache line size so
they can be DMAed safely.
Signed-off-by: Ilya Yanok <[email protected]>
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Printing message could be useful if something goes really wrong.
Signed-off-by: Ilya Yanok <[email protected]>
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Buffer coming from upper layers should be cacheline aligned/padded
to perform safe cache operations. For now we don't do bounce
buffering so getting unaligned buffer is an upper layer error.
We can't check if the buffer is properly padded with current
interface so just assume it is (consider changing with in the
future). The following changes are done:
1. Remove useless length alignment check. We get actual transfer
length not the size of the underlying buffer so it's perfectly
valid for it to be unaligned.
2. Move flush_dcache_range() out of while loop or it will
flush too much.
3. Don't try to fix buffer address before calling invalidate:
if it's unaligned it's an error anyway so let cache subsystem
cry about that.
4. Fix end buffer address to be cacheline aligned assuming upper
layer reserved enough space. This is potentially dangerous
operation so upper layers should be careful about that.
Signed-off-by: Ilya Yanok <[email protected]>
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The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum. We add a cpp check to <usb.h> to define USB_DMA_MINALIGN and
make use of it in ehci-hcd.c and musb_core.h. We cannot use MAX() here
as we are not allowed to have tests inside of align(...).
Signed-off-by: Tom Rini <[email protected]>
[marek.vasut]: introduce some crazy macro voodoo
Signed-off-by: Marek Vasut <[email protected]>
[ilya.yanok]: moved external buffer fixes to separate patch,
we use {ALLOC,DEFINE}_ALIGN_BUFFER macros with alignment of USB_DMA_MINALIGN
for qh_list, qh and qtd structures to make sure they are proper aligned
for both controller and cache operations.
Signed-off-by: Ilya Yanok <[email protected]>
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Move or_asynclistaddr programming to ehci_submit_async()
function to make sure queue head is properly programmed
before every transfer. This solves the problem with changing
qh address.
Also remove unneeded qh_list->qh_link reprogramming at the
end of transfer.
Signed-off-by: Ilya Yanok <[email protected]>
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This has never been completely sufficient and now happens too late to
paper over the cache coherency problems with the current USB stack.
Cc: Marek Vasut <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Signed-off-by: Ilya Yanok <[email protected]>
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* 'next' of git://git.denx.de/u-boot-video:
ipu_common: Add ldb_clk for use in parenting the pixel clock
ipu_common: Do not hardcode the ipu_clk frequency
ipu_common: Rename MXC_CCM_BASE
ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53
ipu_common: Only apply the erratum to MX51
video: Rename CONFIG_VIDEO_MX5
mx6: Allow mx6 to access the IPUv3 registers
common lcd: minor coding style changes
Signed-off-by: Wolfgang Denk <[email protected]>
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For FSL low-end processors (VVN2.2), in order to detect the SD card,
we should enable PEREN, HCKEN and IPGEN to enable the clock.
Otherwise, after booting the u-boot, and then inserting the SD card,
the SD card can't be detected.
For SDHC VVN2.3 IP, these bits are reserved, and SDCLKEN is used.
And when accessing to these reserved bit, no any impact happened.
Signed-off-by: Jerry Huang <[email protected]>
CC: Andy Fleming <[email protected]>
CC: Marek Vasut <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Use the function 'mmc_send_status' to check the card status.
only when the card is ready, driver can send the next erase command
to the card, otherwise, the erase will failed:
=> mmc erase 0 1
MMC erase: dev # 0, block # 0, count 1 ... 1 blocks erase: OK
=> mmc erase 0 2
MMC erase: dev # 0, block # 0, count 2 ... mmc erase failed
1 blocks erase: ERROR
=> mmc erase 0 4
MMC erase: dev # 0, block # 0, count 4 ... mmc erase failed
1 blocks erase: ERROR
Signed-off-by: Jerry Huang <[email protected]>
CC: Andy Fleming <[email protected]>
CC: Marek Vasut <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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This code adds call to mmc_init(), for partition related commands (e.g.
fatls, fatinfo etc.).
It is safe to call mmc_init() multiple times since mmc->has_init flag
prevents from multiple initialization.
The FAT related code calls get_dev high level method and then uses
elements from mmc->block_dev, which is uninitialized until the mmc_init
(and thereof mmc_startup) is called.
This problem appears on boards, which don't use mmc as the default
place for envs
Signed-off-by: Lukasz Majewski <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Cc: Andy Fleming <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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mmc_set_clock is set to the hard-coding.
But i think good that use the tran_speed value.
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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Signed-off-by: Eric Nelson <[email protected]>
Signed-off-by: Andy Fleming <[email protected]>
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* 'next' of git://git.denx.de/u-boot-net:
net: Inline the new eth_setenv_enetaddr_by_index function
net: allow setting env enetaddr from net device setting
net/designware: Consecutive writes to the same register to be avoided
CACHE: net: asix: Fix asix driver to work with data cache on
net: phy: micrel: make ksz9021 phy accessible
net: abort network initialization if the PHY driver fails
phylib: phy_startup() should return an error code on failure
net: tftp: fix type of block arg to store_block
Signed-off-by: Wolfgang Denk <[email protected]>
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* 'master' of git://git.denx.de/u-boot-i2c:
mx28evk: Add I2C support
mxs-i2c: Fix internal address byte order
mxc_i2c: remove setting speed at each start
mx6qsabrelite: add i2c support
mxc_i2c: specify i2c base address in config file
Signed-off-by: Wolfgang Denk <[email protected]>
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This commit is an add-on to f6c4191f. There are a few registers where
consecutive writes to the same location should be avoided or have a delay.
According to Synopsys, here is a list of the registers and bit(s) where
consecutive writes should be avoided or a delay is required:
DMA Registers:
Register 0 Bit 7
Register 6 All bits except for 24, 16-13, 2-1.
GMAC Registers:
Registers 0-3 All bits
Registers 6-7 All bits
Register 10 All bits
Register 11 All bits except for 5-6.
Registers 16-47 All bits
Register 48 All bits except for 18-16, 14.
Register 448 Bit 4.
Register 459 Bits 0-3.
Signed-off-by: Dinh Nguyen <[email protected]>
Reviewed-by: Matthew Gerlach <[email protected]>
Acked-by: Amit Virdi <[email protected]>
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The asix driver did not align buffers, therefore it didn't work
with data cache enabled. Fix this.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
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Micrel accidentally used the same part number
for the KS8721 and KSZ9021. So, both cannot be
in the same build of u-boot. Add a config option
to handle this.
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Vladimir Zapolskiy <[email protected]>
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Now that phy_startup() can return an actual error code, check for that error
code and abort network initialization if the PHY fails.
Signed-off-by: Timur Tabi <[email protected]>
Acked-by: Nobuhiro Iwamamatsu <[email protected]> (sh_eth part)
Acked-by: Stephan Linz <[email protected]> (Xilinx part, xilinx_axi_emac and xilinx_ll_temac)
Reviewed-by: Marek Vasut <[email protected]> (FEC part)
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phy_startup() calls the PHY driver's startup function, but it ignores the
return code from that function, and so it never returns any failures.
Signed-off-by: Timur Tabi <[email protected]>
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Large EEPROMs, e.g. 24lc32, need 2 byte to address the internal memory.
These devices require that the high byte of the internal address has to be
written first.
The mxs_i2c driver currently writes the address' low byte first.
The following patch fixes the byte order of the internal address that should
be written to the I2C device.
Signed-off-by: Torsten Fleischer <[email protected]>
CC: Marek Vasut <[email protected]>
CC: Stefano Babic <[email protected]>
CC: Fabio Estevam <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Other then being very weird, this code was also wrong.
For example, say I set speed to 100K. I'll read back the speed
as 85937. But the speed is really 85937.5, so we I reset
the speed to 85937, I'll get 73660.7. After a couple of transactions
my speed is now exactly 68750 so it will remain there.
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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The following platforms had their config files changed
flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd
and mx53loco.
Signed-off-by: Troy Kisky <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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