| Age | Commit message (Collapse) | Author |
|---|
|
At this point in time, we know that with the MMC symbol enabled we will
always also have the BLK symbol enabled, so we do not need to list that
as a dependency for MMC drivers.
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
|
|
When converting to ofnode `ofnode_read_u32` was accedentally used to
replace `fdtdec_get_int` instead of `ofnode_read_u32_default`.
Use `ofnode_read_u32_default` to fix this.
Fixes: 59382d2 ("pinctrl: imx: Convert to use livetree API for fdt access")
Signed-off-by: Jesse Taube <[email protected]>
|
|
i.MX95 uses enetc version 4.1 controller. Update the enetc for i.MX95.
Add ARM-specific cache handling and i.MX95 specific register layout
handling.
Signed-off-by: Alice Guo <[email protected]>
Signed-off-by: Marek Vasut <[email protected]> # Clean up
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Tim Harvey <[email protected]>
|
|
The verdor ID and device ID of i.MX95 EMDIO are different from LS1028A
EMDIO, so add new vendor ID and device ID to pci_device_id table to
support i.MX95 EMDIO.
Signed-off-by: Alice Guo <[email protected]>
Signed-off-by: Marek Vasut <[email protected]> # Clean up
Signed-off-by: Ye Li <[email protected]>
|
|
The netc-blk-ctrl driver is used to configure Integrated Endpoint
Register Block (IERB) and Privileged Register Block (PRB) of NETC.
For i.MX platforms, it is also used to configure the NETCMIX block.
The IERB contains registers that are used for pre-boot initialization,
debug, and non-customer configuration. The PRB controls global reset
and global error handling for NETC. The NETCMIX block is mainly used
to set MII protocol and PCS protocol of the links, it also contains
settings for some other functions.
Note the IERB configuration registers can only be written after being
unlocked by PRB, otherwise, all write operations are inhibited. A warm
reset is performed when the IERB is unlocked, and it results in an FLR
to all NETC devices. Therefore, all NETC device drivers must be probed
or initialized after the warm reset is finished.
Ported from Linux 6.13-rc as of commit
fe5ba6bf91b3 ("net: enetc: add initial netc-blk-ctrl driver support")
Signed-off-by: Marek Vasut <[email protected]>
|
|
Pass struct udevice * into the register accessors, so the accessors can reach
driver data, which contain device specific register offsets.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Introduce driver data for each PCI device. The driver data carry
offsets of registers which differ between different SoCs.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Split register accessors to the port base/station interface/port/mac
registers as those are at different offsets on different SoCs. This
is a preparatory patch which will allow addition of adjusted offsets
for new SoCs easily.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Move register accessors from header files and turn them into proper
inline functions, so typechecking can be done on them. Drop no longer
enetc_port_regs() and unused enetc_read() and enetc_bdr_read().
Signed-off-by: Marek Vasut <[email protected]>
|
|
Introduce mapping function enetc_dev_id(), which converts PCIe BDF of
the ENETC into linear incrementing index usable e.g. as interface index.
This replaces the current ad-hoc calculation used in the code with a
dedicated function. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Rename the current driver structure and matching ops and PCI IDs
and add _ls suffix to indicate this content is LS specific. This
is done in preparation for addition of i.MX95 ENETCv4 which will
require slightly different structure content.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Pass udevice pointer into enetc_enable_si_port() so tests like
enetc_is_ls1028a() an be used in the function. No functional
change.
Signed-off-by: Marek Vasut <[email protected]>
|
|
The entire content of the loop can be folded into enetc_set_ierb_primary_mac(),
do it. This changes the behavior slightly such that the DT is only updated in
case of a LS1028A, which is the only SoC with ethernet MAC path in DT matching
"/soc/pcie@1f0000000/ethernet@%x,%x" anyway, so this slight change should have
no impact.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Use enetc_is_ls1028() instead of ifdef around enetc_set_ierb_primary_mac()
and clean up the function. No functional change intended.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Introduce accurate test for LS1028A compatibility based both on
IS_ENABLED(CONFIG_ARCH_LS1028A) and PCI vendor ID. This is done
in preparation for adding ENETCv4 support, which has a different
PCI vendor ID.
Signed-off-by: Marek Vasut <[email protected]>
|
|
i.MX93-11x11-EVK has switched to use upstream device tree, and use
"adi,adp5585". Since i.MX93-11x11-EVK is the only user of this driver,
so it is safe to drop "adp5585".
Signed-off-by: Peng Fan <[email protected]>
|
|
Santhosh Kumar K <[email protected]> says:
Hello,
This series adds support for Inline ECC in DDR for AM64X, AM62X,
AM62AX, AM62PX, J721E, J721S2, J722S and J784S4 devices.
Test Results: https://gist.github.com/santhosh21/88de920771ed2efa0463a5a367cb8d7b
Link: https://lore.kernel.org/r/[email protected]
|
|
The functionality of enabling Inline ECC is now controlled by
CONFIG_K3_INLINE_ECC. So, remove the support for 'ti,ecc-enable'
property to avoid redundancy and to ensure the Inline ECC feature is
mananged through build-time config.
Signed-off-by: Santhosh Kumar K <[email protected]>
Reviewed-by: Wadim Egorov <[email protected]>
|
|
Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL
only when the config has been enabled.
Signed-off-by: Neha Malcom Francis <[email protected]>
Signed-off-by: Santhosh Kumar K <[email protected]>
Reviewed-by: Wadim Egorov <[email protected]>
|
|
Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts
by setting the respective bits in the DDRSS_V2A_INT_SET_REG register.
Signed-off-by: Santhosh Kumar K <[email protected]>
|
|
Setup the ECC region's start and range using the device private data,
ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and
range of ECC regions from 32 bits to 64 bits to accommodate for
DDR greater than or equal to 4GB.
Signed-off-by: Santhosh Kumar K <[email protected]>
|
|
restricted to 32 bits' issue
As R5 is a 32 bit processor, the RAM banks' base and size calculation
is restricted to 32 bits, which results in wrong values if bank's base
is greater than 32 bits or bank's size is greater than or equal to 4GB.
So, add k3_ddrss_ddr_bank_base_size_calc() to get the base address and
size of RAM's banks from the device tree memory node, and store in a
64 bit device private data which can be used for ECC reserved memory
calculation, Setting ECC range and Fixing up bank size in device tree
when ECC is enabled.
Signed-off-by: Santhosh Kumar K <[email protected]>
Reviewed-by: Wadim Egorov <[email protected]>
|
|
The 1-bit inline ECC support in TI's DDRSS bridge requires
the configured memory regions to be preloaded with a pattern
before use. This is done by the k3-ddrss driver from the
R5 SPL in a 'for' loop. It takes around 10 seconds to fill
2GB of memory, for example. Memset can cut the time in half
and using DMA currently yields a similar result.
The BIST engine of DDR controller provides support for
initializing any memory region with a pattern. This
bypasses the DDRSS bridge, so the required inline ECC
data is not computed and populated in the memory. For
some values like zero, the computed ECC syndrome is also
zero and we can use these values to preload the memory
from the DDR controller, without the assistance of the
bridge.
The registers involved in the process are described in the
'DDR controller registers' topic in [1] AM62 and [2] J721E
reference manuals.
The patch replaces the 'for' loop memory fill function with
the BIST memory initialization procedure. This cuts the time
to preload the 2GB memory from 10 seconds down to 1 second.
The bist preload function uses the lpddr4 APIs in the k3-ddrss,
so this is compatible with devices with both 16-bit LPDDR4 and
32-bit LPDDR4 interfaces (e.g J721E).
[1] AM62x: https://www.ti.com/lit/pdf/spruiv7
[2] DRA829/TDA4VM: https://www.ti.com/lit/zip/spruil1
Signed-off-by: Georgi Vlaev <[email protected]>
Signed-off-by: Santhosh Kumar K <[email protected]>
|
|
Raymond Mao <[email protected]> says:
Motivations for changes:
Current SMBIOS library and command-line tool is not fully matching with
the requirements:
1. Missing support for other mandatory types (#7, #9, #16, #17, #19).
2. Only a few platforms support SMBIOS node from the device tree.
3. Values of some fields are hardcoded in the library other than fetching
from the device hardware.
4. Embedded data with dynamic length is not supported (E.g. Contained
Object Handles in Type #2 and Contained Elements in Type #3)
Changes:
1. Refactor the SMBIOS library and command-line tool to better align with
the SMBIOS spec.
2. Create an arch-specific driver for all aarch64-based platforms to fetch
SMBIOS private data from the device hardware (processor and cache).
3. Create a sysinfo driver to poppulate platform SMBIOS private data.
4. Add generic SMBIOS DTS file for arm64 platforms for those common strings
and values which cannot be retrieved from the system registers.
Vendors can create their own SMBIOS node using this as an example.
For those boards without SMBIOS nodes, this DTS file can be included to
have a generic SMBIOS information of the system.
5. Add support for Type #7 (Cache Information) and link its handles to
Type #4.
6. To minimize size-growth for those platforms which have not sufficient
ROM spaces or the platforms which don't need detailed SMBIOS
information, new added fields are only being built when kconfig
GENERATE_SMBIOS_TABLE_VERBOSE is selected.
Once this patch is acceptted, subsequent patch sets will add other missing
types (#9, #16, #17, #19).
Tests:
To test this with QEMU arm64, please follow the guide on dt_qemu.rst to
get a merged DT to run with.
```
qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb
cat <(dtc -I dtb qemu.dtb) <(dtc -I dtb ./dts/dt.dtb | grep -v /dts-v1/) \
| dtc - -o merged.dtb
qemu-system-aarch64 -machine virt -nographic -bios u-boot.bin \
-dtb merged.dtb
```
Link: https://lore.kernel.org/r/[email protected]
|
|
Enable sysinfo smbios by default for arm64.
When SYSINFO_SMBIOS is enabled, disable QFW_SMBIOS.
Signed-off-by: Raymond Mao <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Add sysinfo driver to retrieve smbios information (Type 4 and 7).
So that the smbios library can use it for getting values from the
hardware platform instead of device tree.
Signed-off-by: Raymond Mao <[email protected]>
|
|
Adding sysinfo_get_data into sandbox ut test dm_test_sysinfo.
Signed-off-by: Raymond Mao <[email protected]>
|
|
Add interface for sysinfo to access a data area from the platform.
This is useful to save/read a memory region of platform-specific
data.
Signed-off-by: Raymond Mao <[email protected]>
|
|
Rather than doing autoprobe within the driver model code, move it out to
the board-init code. This makes it clear that it is a separate step from
binding devices.
For now this is always done twice, before and after relocation, but we
should discuss whether it might be possible to drop the post-relocation
probe.
For boards with SPL, the autoprobe is still done there as well.
Note that with this change, autoprobe happens after the
EVT_DM_POST_INIT_R/F events are sent, rather than before.
Link: https://lore.kernel.org/u-boot/[email protected]/
Signed-off-by: Simon Glass <[email protected]>
|
|
There is no point in checking the pre_reloc flag, since devices not
marked as pre-reloc will not have been bound, so won't exist yet.
There doesn't seem to be any point in checking if the device has a
valid devicetree node either, so drop that too.
Signed-off-by: Simon Glass <[email protected]>
|
|
https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx changes for v2025.04-rc1 v2
Versal:
- Enable dfu support for SPI with multiboot
ZynqMP:
- Align multiboot reg description
- DT syncups
- Wire missing DTs in defconfig
- Kria: Remove usb hub initialization via commands
- Kria: Update DP reset in psu_init
AMD/Xilinx:
- Enable SPI_STACKED_PARALLEL configs
SPI/ZYNQMP_GQSPI:
- Update debug message to use log_debug()
RTC:
- Enable ZYNQMP_RTC for Versal SOCs
|
|
Allow the ZyncMP RTC driver to be enabled on Versal architectures.
Also, require DM_RTC since the driver uses the RTC driver model.
Signed-off-by: Vincent Fazio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
|
|
Update recent parallel memory support code to move to log_debug instead
of debug as per logging in U-Boot documentation
Signed-off-by: Ibai Erkiaga <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
|
|
Fix compatiable name for TPS65224 PMIC as defined in
dts/upstream/Bindings/mfd/ti,tps6594.yaml bindings.
Fixes: 1468fbba6d55("power: pmic: tps65941: Add TI TPS65224 PMIC")
Signed-off-by: Udit Kumar <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
|
|
Replace magic numbers in buckval2votl() & buckvolt2val() with macros to
help with clarity and correlate what the numbers correspond to in the
TPS65219 datasheet.
Signed-off-by: Shree Ramamoorthy <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
|
|
Replace printf() with pr_err() because pr_err() has a uniform print format
and takes into consideration the log levels supported.
Signed-off-by: Shree Ramamoorthy <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
|
|
- ehci-mx5/ehci-mx6 driver improvements
|
|
i.MX95 uses the same USB IP as i.MX8MM. It can then reuse the ehci-mx6
driver.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
|
|
https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/24129
- Add boards:
rk3566: FriendlyARM NanoPi R3S
rk3588s: Radxa ROCK 5C,
rk3588: Khadas Edge2
- Migrate to OF_UPSTREAM:
rk3066a/rk3188;
rk3288: tinker, miqi, firefly;
- Migrate to TPL: rk3399 kevin and bob;
|
|
The SCLK_MAC_PLL id is not exported or referenced upstream. It is also
not referenced in vendor U-Boot or vendor kernel 4.4, 4.19, 5.10 or 6.1.
Relax the check for parent id SCLK_MAC_PLL when using internal clock
source for gmac to allow use of clock/rk3288-cru.h from dts/upstream.
All in-tree and upstream rk3288 DTs use an external clock as parent,
so no functional change to boards is expected with this change.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
- rti: support SPL (or re-start) (Alexander)
- rti: drop hack manipulating WDT clock rate (Alexander)
|
|
With the commit 4fcba5d556b4 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators.
Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.
Based on 335799b7252a ("usb: dwc2: Use regulator_set_enable_if_allowed")
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
|
|
With the commit 4fcba5d556b4 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators.
Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.
Based on 335799b7252a ("usb: dwc2: Use regulator_set_enable_if_allowed")
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
|
|
|
|
The hack itself seems to be copied from Linux rti_wdt.c, but the WDT reset
principle is different in U-Boot. While Linux relies on correct frequencies
and timers and doesn't check the actual WDT counter value U-Boot driver
seems to be more robust: it does compare RTIDWDCNTR vs RTIDWDPRLD.
Now the root cause of the original motivation to manipulate the clock rate
is said to be understood and fixed in Linux commit cae58516534e
("watchdog: rti_wdt: Set min_hw_heartbeat_ms to accommodate a safety margin")
which simultaneously removed the hack itself.
While is fix part of the mentioned patch is neither applicable nor requried
for the U-Boot driver just drop the hack setting WDT clock rate to 90% of
the real rate. This has a nice effect that the WDT timeout is now as
requested and not 10% shorter.
Signed-off-by: Alexander Sverdlin <[email protected]>
Reviewed-by: Jan Kiszka <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
|
|
If the RTI watchdog has been enabled in SPL, enabling it in U-Boot proper
fails because it can only be enabled once in HW and never stopped. This
however leads to a situation that wdt_cyclic() watchdog trigger is not
being started any longer and the WDT fires at some point.
Allow for WDT re-start by not bailing out if the [previously] configured
period matches the one to be configured.
Enabling in [A53] SPL has been tested on AM62x-based HW (where [A53] SPL is
responsible for loading R5 DM firmware and not this driver).
Signed-off-by: Alexander Sverdlin <[email protected]>
Reviewed-by: Jan Kiszka <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
|
|
Add driver for Motorcomm YT8521S Gigabit ethernet phy.
Signed-off-by: Frank Sae <[email protected]>
|
|
Add driver for Motorcomm YT8531S Gigabit ethernet phy.
Signed-off-by: Frank Sae <[email protected]>
|
|
Linux DTS compatible MDIO bitbanging driver.
Both clause 22 and clause 45 MDIO supported and validated.
Heavily based on the Linux drivers (more or less the same code base).
Signed-off-by: Markus Gothe <[email protected]>
|
|
The output of ip_to_string() is a string.
Signed-off-by: Heinrich Schuchardt <[email protected]>
|
