| Age | Commit message (Collapse) | Author |
|---|
|
Fix wrong mux width for pwm2 and pwm1. Upstream have width 1 but U-Boot
have width set to 2. Change the value to follow upstream implementation.
Signed-off-by: Christian Marangi <[email protected]>
|
|
Fix a typo for infra_i2c0_ck where 0 was misspelled as O.
Signed-off-by: Christian Marangi <[email protected]>
|
|
Add missing clock for infra_ipcie_pipe to make PCIe correctly work. This
clock is a parent of the fixed clock from topckgen cb_cksq_40m.
Signed-off-by: Christian Marangi <[email protected]>
|
|
Christian Marangi <[email protected]> says:
These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
|
|
Upstream kernel linux makes use of peri clock MUX to setup UART.
Add definition for these and add remap table as in the upstream clock ID
order gates are before MUX but we require MUX first and then clocks in
our downstream driver.
Convert the peri clk tree to MUX + GATE implementation.
Signed-off-by: Christian Marangi <[email protected]>
Tested-by: Frank Wunderlich <[email protected]>
|
|
Define remap table also for apmixedsys clock ID. The clock ID starts
from 1 instead of 0 in upstream kernel linux.
Signed-off-by: Christian Marangi <[email protected]>
|
|
Define id_offs_map and use clk ID form upstream linux kernel to have a
1:1 match for the TOPCKGEN clock and permit usage of OF_UPSTREAM with
upstream dtsi.
For all the gate clock, the clk ID starts from 1 instead of zero. Define
an additional clock tree for them and set the .gates_offs to 1 to
account for this.
Signed-off-by: Christian Marangi <[email protected]>
|
|
Split clk tree to dedicated topckgen and apmixed in preparation for
remap table.
Signed-off-by: Christian Marangi <[email protected]>
|
|
Fix broken peri_cgs and infra_cgs clock with XTAL parents as they have
wrong definition of the parent type.
Correctly fix them and use CLK_PARENT_XTAL for them.
Signed-off-by: Christian Marangi <[email protected]>
|
|
Fix most of checkpatch warnings and other obvious style issues.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Reduce U-Boot footprint by reusing dev->name as a driver's displayed
name. This changes boot device name (and "mmc info" output) from "EXYNOS
DWMMC" to something like "mmc@12100000".
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
add_dwmci() is already calling dwmci_setup_cfg() internally, there is no
needed to call dwmci_setup_cfg() again in case when add_dwmci() is used
(for non-DM cases). Fix it by calling dwmci_setup_cfg() only in DM
cases, when add_dwmci() wasn't called. Also, this assignment:
host->mmc = &plat->mmc;
is wrong in non-DM case when add_dwmci() was called, as it's creating
mmc object internally. Fix that by pulling that assignment into DM case,
when add_dwmci() isn't called.
While at it, add also this missing assignment:
host->mmc->dev = dev;
Fixes: 3537ee879e04 ("mmc: exynos_dw_mmc: support the Driver mode for Exynos")
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
There is no logical sense to split the initialization code between
multiple functions. Pull both do_dwmci_init() and
exynos_dwmci_core_init() into exynos_dwmmc_probe() to make the code more
simple and obvious.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Add the compatible entry and corresponding chip data for Exynos7
compatible chips, which covers modern ARM64 based Exynos chips. They
have some differences w.r.t. old ARM32 Exynos chips:
- CLKSEL register offset is different
- 64-bit IDMAC descriptor and 64-bit IDMAC registers are used
(implemented in dw_mmc core driver)
In terms of the driver implementation, the CIU clock is obtained via CCF
framework (as opposed to ad-hoc clock driver implementation for ARM32
chips).
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
By now exynos_dw_mmc driver was relying on the correct CIU clock
frequency being set on driver init. But dw_mmc core is actually trying
to change CIU clock rate dynamically, on init and in set_ios() callback,
which it's requesting via host->get_mmc_clk() callback (the name is
misleading: although it's called "get_mmc_clk()", it can actually
request both get and set operations). Implement setting the requested
rate for CIU clock in Exynos driver to achieve the correct dw_mmc core
driver operation at all times. DDR mode requires the clock to be twice
as fast (when 8 bit bus is used), so handle this too, to make DDR
function properly.
This change makes the eMMC throughput on E850-96 board twice as fast.
That's because "clock-frequency" is set to 800 MHz in E850-96 device
tree, but for DDR52 mode it should be 416 MHz (and TRM states it should
be 400 MHz for DDR50/8bit mode). The dw_mmc core is requesting 52 MHz
bus_hz for DDR52 mode, and DDR+8bit mode means it should be x2 fast, so:
f_ciu = 2 * ciu_div * f_bus = 2 * 4 * 52e6 = 416 MHz,
where f_ciu - freq of clock fed to DW MMC block from CMU (SDCLKIN), Hz
f_bus - freq of clock fed to the card (CCLKIN), Hz
ciu_div - value of internal divider (in DW MMC block).
Another way to work that around would be overriding the
"clock-frequency" property in corresponding dts. But setting the clock
frequency dynamically as it's done here looks much neater.
This implementation follows what's done in Linux kernel dw_mmc-exynos
driver in .set_ios() callback for MMC_TIMING_MMC_DDR52 case.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
DDR timing values should be defined in "samsung,dw-mshc-ddr-timing" dts
property, and used when DDR MMC mode is selected. Read that value from
dts and use it. If it's not available, use SDR timing values instead.
This change is following upstream Linux kernel implementation.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
host->quirks field is only used internally in exynos_dw_mmc.c driver.
To avoid cluttering the scope of struct dwmci_host, move quirks field
into Exynos driver's chip data, where it can be statically defined.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Instead of using non-standard "bus_hz" dts property, read common
"clock-frequency" property used in upstream Linux kernel. It's safe to
do so, as "clock-frequency" property was already added to corresponding
nodes in all affected Exynos device tree files.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Instead of using non-standard "samsung,bus-width" dts property, read
common "bus-width" property used in upstream Linux kernel. It's safe to
do so, as "bus-width" property was already added to corresponding nodes
in all affected Exynos device tree files.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Some chips like Exynos4412 have fixed internal CIU clock divider.
Instead of reading it from non-standard "div" dts property, store its
value in the driver internally, in static chip data associated with
corresponding compatible. This makes it possible to avoid using
host->div for storing it, so the latter can be removed safely. Also
create a helper function called exynos_dwmmc_get_ciu_div() for getting
the current div value: in case the fixed div is provided in the chip
data it will be used, otherwise the current div value is being read from
CLKSEL register.
The insights for this change were taken from dw_mmc-exynos.c driver in
Linux kernel.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
CLKSEL register offset may vary between different Exynos chips, e.g. on
ARM64 vs ARM32 chips. Provide a way to specify its offset value for each
compatible instead of hard-coding its value in read/write calls.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
The obsolete "samsung,timing" dts property is now split into
"samsung,dw-mshc-ciu-div" (for holding the internal DW MMC divider
value) and "samsung,dw-mshc-sdr-timing" (for actual timing values) in
upstream Linux kernel. Rework the driver to make use of new properties
instead of the old one. All affected dts files were already updated
accordingly.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Update the driver to use livetree API instead of FDT one.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
exynos_dwmci_get_config() is called from the probe function and used to
read data from device tree. Make use of .of_to_plat driver callback
instead, and convert exynos_dwmci_get_config() to match its signature.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
New Exynos chips should implement clock drivers using CCF framework. In
that case corresponding CCF functions can be used to get/set the clock
rates. Moreover, already existing get_mmc_clk() and set_mmc_clk() calls
are only implemented for CONFIG_CPU_V7A (i.e. ARM32 chips). In case of
ARM64 chips that config option is not defined, so build will crash on
linking stage, with errors like these:
ld: drivers/mmc/exynos_dw_mmc.o:
in function `exynos_dwmci_get_sclk':
undefined reference to `get_mmc_clk'
ld: drivers/mmc/exynos_dw_mmc.o:
in function `exynos_dwmci_set_sclk':
undefined reference to `set_mmc_clk'
Fix that issue by using CCF clocks API on ARM64 platforms for getting
and setting the source clock (sclk = SDCLKIN = CIU) rate. To implement
this, first extract the existing ARM32 clock control code into helper
functions with more generic signatures to abstract getting/setting the
sclk rate. Then add CCF clock support to those functions for ARM64
platforms.
Fixes: a082a2dde061 ("EXYNOS5: DWMMC: Added FDT support for DWMMC")
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Pinmux configuration on ARM64 platforms must be performed during startup
in pinctrl driver using info from device tree. exynos_pinmux_config()
and pinmux_decode_periph_id() are only available on ARM32 platforms, so
don't call those functions on ARM64 platforms. Instead of the latter
function, use "non-removable" property from device tree to derive the
dev_index value.
This fixes next linking errors on ARM64 platforms:
ld: drivers/mmc/exynos_dw_mmc.o:
in function `exynos_dwmci_get_config':
undefined reference to `pinmux_decode_periph_id'
ld: drivers/mmc/exynos_dw_mmc.o:
in function `do_dwmci_init':
undefined reference to `exynos_pinmux_config'
Fixes: a082a2dde061 ("EXYNOS5: DWMMC: Added FDT support for DWMMC")
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
In case of CONFIG_DM_MMC, host->priv actually holds (struct udevice *),
and not (struct dwmci_exynos_priv_data *). This makes *priv pointer
invalid and may lead to Synchronous Abort during its dereference later
in exynos_dwmci_board_init(). Fix it by extracting
exynos_dwmmc_get_priv() helper from exynos_dwmci_clksel() and using it
for getting the private data in exynos_dwmci_board_init()
Fixes: 3537ee879e04 ("mmc: exynos_dw_mmc: support the Driver mode for Exynos")
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Getting the base address with outdated fdtdec_get_addr() API and further
casting it to (void *) leads to next build warning on ARM64 platforms:
In function 'exynos_dwmci_get_config':
warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
host->ioaddr = (void *)base;
Use livetree API instead (dev_read_addr_ptr()), which handles this
correctly.
Fixes: a082a2dde061 ("EXYNOS5: DWMMC: Added FDT support for DWMMC")
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Fix most of checkpatch warnings and other obvious style issues.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Replace fifoth_val property with its fifo-depth counterpart in all DW
MMC drivers. fifo-depth is a common property used in upstream Linux
kernel. The FIFOTH register value will be calculated using fifo-depth
value in DW MMC core (dw_mmc.c). This change reduces code duplication in
platform drivers, and pulls common FIFOTH register value calculation
into core dw_mmc driver where it belongs.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Some DW MMC blocks (e.g. those on modern Exynos chips) support 64-bit
DMA addressing mode. 64-bit DW MMC variants differ from their 32-bit
counterparts:
- the register layout is a bit different (because there are additional
IDMAC registers present for storing upper part of 64-bit addresses)
- DMA descriptor structure is bigger and different from 32-bit one
Introduce all necessary changes to enable support for 64-bit DMA capable
DW MMC blocks. Next changes were made:
1. Check which DMA address mode is supported in current IP-core
version. HCON register (bit 27) indicates whether it's 32-bit or
64-bit addressing. Add boolean .dma_64bit_address field to struct
dwmci_host and store the result there. dwmci_init_dma() function is
introduced for doing so, which is called on driver's init.
2. Add 64-bit DMA descriptor (struct dwmci_idmac64) and use it in
dwmci_prepare_desc() in case if .dma_64bit_address field is true.
A new dwmci_set_idma_desc64() function was added for populating that
descriptor.
3. Add registers for 64-bit DMA capable blocks. To make the access to
IDMAC registers universal between 32-bit / 64-bit cases, a new
struct dwmci_idmac_regs (and corresponding host->regs field) was
introduced, which abstracts the hardware by being set to
appropriate offset constants on init. All direct calls to IDMAC
registers were correspondingly replaced by accessing host->regs.
4. Allocate and use 64-bit DMA descriptors buffer in case when IDMAC
is 64-bit capable. Extract all the code (except for the IDMAC
descriptors buffer allocation) from dwmci_send_cmd() to
dwmci_send_cmd_common(), so that it's possible to keep IDMAC
buffer (either 32-bit or 64-bit) on stack during send_cmd routine.
The insights for this implementation were taken from Linux kernel DW MMC
driver.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Prepare for adding 64-bit IDMAC descriptors by renaming current 32-bit
descriptor and its fields accordingly. While at it, make use of
virt_to_phys() to make it more obvious in which places the physical
addresses have to be used.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Make dwmci_prepare_data() function easier to read by extracting the
preparation of IDMAC descriptor into a dedicated function.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Make dwmci_send_cmd() easier to read by moving the DMA transfer handling
code into a dedicated function.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
FIFO data transfer is implemented as quite a massive chunk of code.
Extract it into a dedicated function to make dwmci_data_transfer()
easier to read and reduce the indentation level of the code.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Extract the clock divider update into dwmci_update_div() function. It's
a procedure recommended in TRM, so it's better to keep it in a dedicated
function to make the code clearer.
While at it also extract the clock control code into a separate routine
to avoid code duplication in dwmci_setup_bus().
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Move FIFO threshold initialization into a separate function to make
dwmci_init() more readable.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
Waiting for data busy is a logically separate operation and should be
implemented as a separate routine. Follow Linux kernel example and
extract it from dwmci_send_cmd(). This way it doesn't clutter
dwmci_send_cmd() function, and can be reused later in other cases.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
struct idmac is only used in dw_mmc.c, so move it there from dwmmc.h to
avoid cluttering the interface in the header.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
|
|
ENOSYS should only be used when a subsystem is completely absent.
Convert its use in pinctrl-generic to ENOENT, which better reflects the
error condition (that a function/group/pin is missing).
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Some boards don't have chipselect lines for leds so cs-gpios is not
specified in the dts leading to probing error. Fix it by making
behavior similar to the one in Linux, parse num-chipselects and
if it is zero, ignore cs-gpios.
Signed-off-by: Michael Polyntsov <[email protected]>
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
|
|
The patch fix a missprint introduced in commit 2e9fe73a883a ("spi: soft_spi:
Support the recommended soft spi properties").
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
|
|
Now that this is always 1, remove it and the associated dead code.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
|
|
Now that this is always 0, remove it and the associated dead code.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
|
|
This is very old, predating even the legacy I2C support, so drop it.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
|
|
This is not now used by any boards, so drop it.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
|
|
Drop some old code from the mxc_i2c and ddr/fsl drivers. This will allow
removal of very old common I2C code.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
|
|
This is only used by devkit3250 which is being removed. Drop it.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
|
|
https://source.denx.de/u-boot/custodians/u-boot-rockchip
Please pull the updates for rockchip platform:
- Add board support:
RK3566: Radxa ROCK 3 Model C
Radxa ZERO 3W/3E
Xunlong Orange Pi 3B
RK3568J: Radxa ROCK 3B
RK3308B: Radxa ROCK S0
RK3588: Radxa ROCK 5 ITX
FriendlyElec CM3588 NAS board
- dw-mmc: allow 4-bit mode;
- dts and config updates;
CI:
https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/21997
|
|
The revision is different for these, add the additional check as in
xhci-dwc3 core_init code.
Equivalent upstream Linux patch:
690fb3718a70 ("usb: dwc3: Support Synopsys USB 3.1 IP")
Reviewed-by: Neil Armstrong <[email protected]>
Tested-by: Neil Armstrong <[email protected]> # on SM8550
Reviewed-by: Mattijs Korpershoek <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
|
