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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22989
- Remove unneeded USB board code and fix reset on mx6ul_14x14_evk.
- Update fastboot buffer size/address for verdin-imx8m{m|p}.
- Fix imxrt1050-evk boot and convert it to standard boot.
- Fix imx8qxp-mek and imx8qm-mek boot.
- Add support for the i.MX93 9X9 QSB board.
- Make livetree API to work on i.MX.
- Set sane default value for i.MX8M SPL_LOAD_FIT_ADDRESS.
- Deduplicate DH i.MX8MP/i.MX6 DHSOM defconfigs.
- Select default TEXT_BASE for i.MX6/i.MX7.
- Several updates for DH i.MX8MP DRC02.
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Two of the clocks required by the usdhc1 controller are missing from the
clock controller node. A recent change enables all the clocks in the
esdhc node, which fails as they are not defined in the clock controller.
Fixes: 76332fae769 ("mmc: fsl_esdhc_imx: Enable AHB/IPG clk with clk bulk API")
Signed-off-by: Jesse Taube <[email protected]>
Cc: Peng Fan <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx changes for v2025.01-rc1 v2
.mailmap:
- Switch Padmarao's email to AMD one
zynq_spi:
- Make update_stripe static
xilinx:
- Update DT description for EMMCs
zynqmp:
- Update logic around RPUs and tcm handling
- Update bootmenu selection for Kria
- Add description for SC vm-p-b1369
- Fix comment about file location in zynqmp-p-a2197-00-revA.dts
versal:
- Fix logic around USB boot
versal2:
- Disable useless features for Mini configurations
versal-net:
- Get rid of current-speed DT property from mini configuration
microblaze:
- Fix scriptaddr location
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#
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# IY1iAKCH/GKJHEXFfLvr0OGuO6c1SX9+ZQCfTjRAHrL186X6LUgjOpmtmsrVK1c=
# =4gY0
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 25 Oct 2024 08:51:36 AM CST
# gpg: using DSA key 1B3CD4CCBD79989413D1C31ECA4965CB294A0C21
# gpg: Good signature from "Michal Simek <[email protected]>" [full]
# gpg: aka "Michal Simek (Xilinx) <[email protected]>" [full]
# gpg: aka "Michal Simek (Xilinx) <[email protected]>" [full]
# gpg: aka "Michal Simek (AMD) <[email protected]>" [unknown]
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https://source.denx.de/u-boot/custodians/u-boot-dfu
CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/22962
Dfu:
- Rely on device tree for spi speed/mode on spi flash
Android Image:
- Fix booting on platforms having > 4GiB of memory
- Decompress boot image to kernel_addr_r when compression is enabled
- Honor CONFIG_SYS_LOAD_ADDR when mkbootimg uses default address
Bcb:
- Rework bcb command to use U_BOOT_LONGHELP
- Move ab_select cmd to bcb cmd
- Implement ab_dump command in bcb
- bcb: Write '_<slot>' instead of '<slot>' to misc partition
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Add missing prototype to fix the sparse warning,
warning: no previous prototype for 'update_stripe'
[-Wmissing-prototypes].
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Add dedicated getter and setter for SCLK_UART0_PMU.
This allows the driver to correctly handle UART0 clocks, and thus
it fixes the issues with UART0 not working in case DEBUG_UART is
disabled.
Unlike other Rockchip SoCs, i.e. rk3399, in the PX30 the default
clock source for UART is GPLL, instead of external oscillator.
If the DEBUG_UART is enabled, the clock source is changed in
board_debug_uart_init function to 24Mhz oscillator, which also
matches the fallback value obtained from DT node.
In case the DEBUG_UART is disabled, the UART clock source remains
default, and the DM serial driver wrongly configures the baud rate,
resulting in broken communication.
By implementing the UART clock getter/setter, the serial driver
can probe the actual configuration and corectly configure itself.
The DEBUG_UART settings now should not affect it.
The driver supports GPLL and 24M oscillator. NPLL and USBPHY480M
sources, that are managed by CRU, are not yet handled, as likely
they won't be used in real scenarios.
Signed-off-by: Lukasz Czechowski <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Convert to using livetree API functions.
Without this if livetree is enabled (OF_LIVE) the fsl_esdhc_imx
driver will fail to read vendor-specific properties from the dt.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Convert to using livetree API functions.
Without this if livetree is enabled (OF_LIVE) the mxc-i2c
driver will fail to support scl-gpios and sda-gpios for
i2c bus recovery.
Signed-off-by: Tim Harvey <[email protected]>
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Convert to using livetree API functions.
Without this if livetree is enabled (OF_LIVE) the imx8m-power-domain
driver will (silently) fail to probe its children leaving you with
no power domain support causing issues with certain devices.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Convert to using livetree API functions.
Without this if livetree is enabled (OF_LIVE) the imx8mq-pinctrl
driver will (silently) fail to probe causing issues with multiple
devices.
Signed-off-by: Tim Harvey <[email protected]>
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Add i.MX93 9x9 Quick Start Board support.
- Two ddr scripts included w/o inline ecc feature.
- SDHC/NETWORK/I2C/UART supported
- PCA9450 supported, default over drive mode
- Documentation added.
Signed-off-by: Peng Fan <[email protected]>
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There are no users of the blk_create_device() function outside the uclass.
Let's make it static. This will ensure that new block drivers will use
blk_create_devicef().
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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By using blk_create_devicef() instead of blk_create_devicef() the driver
can be simplified and brought into line with other block device drivers.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Tested-by: Johan Jonker <[email protected]>
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* Fixes a warning about implicit declaration of udelay.
Signed-off-by: Philip Balister <[email protected]>
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Add SPI NOR flash id for mt35xu01gbba which supports 4 bytes address with
octal mode read.
Signed-off-by: Han Xu <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Added support for the Puya Semiconductor chips.
The datasheet can be found here:
https://www.puyasemi.com/h_xilie715.html
Signed-off-by: Dmitry Dunaev <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Align with cmd_sf, and try to rely on DT for spi speed and mode,
and still fallback on spi_flash_probe() if it fails.
With the current scheme, spi_flash_probe() will be called
with CONFIG_SF_DEFAULT_SPEED and CONFIG_SF_DEFAULT_MODE
with are set to 0 by default on DT platforms using DM_SPI_FLASH.
Like cmd_sf, keep the option to specify the speed and mode
from the dfu_alt_mode string, but rely on DT properties
if not specified.
Using CONFIG_SF_DEFAULT_SPEED and CONFIG_SF_DEFAULT_MODE
makes the SPIFC controller on Amlogic Meson G12B & SM1
hardware fail and is unable to recover until a system reboot.
Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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Currently, enabling WDT_GPIO on a board which uses SPL, but does not
have SPL_WDT, SPL_DM_GPIO or SPL_OF_CONTROL enabled, breaks the build.
Make it possible to use the WDT_GPIO driver on such boards by
introducing a separate symbol controlling whether the driver is built
for SPL. Make it default to WDT_GPIO such that boards that already
have it enabled and all the SPL prerequisites satisfied will continue
to have it in SPL.
Signed-off-by: Rasmus Villemoes <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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These TUs currently rely on getting a declaration of schedule()
through some nested include. Include the proper header directly.
Signed-off-by: Rasmus Villemoes <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This TU currently relies on getting a declaration of schedule()
through some nested include. Include the proper header directly.
Signed-off-by: Rasmus Villemoes <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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This makes use of the cyclic API but relies on implicitly getting the
appropriate declarations through some nested include. Include the
cyclic.h header directly.
Signed-off-by: Rasmus Villemoes <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Add support for the DaVinci's watchdog timer
Signed-off-by: Bastien Curutchet <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Back when I added this driver in commit 2ac8490412c9, I wrote
The corresponding linux driver apparently has support for some
watchdog circuits which can be disabled by tri-stating the gpio, but I
have never actually encountered such a chip in the wild;
That has changed now; I have a board with just such a watchdog on my
desk currently. Add support for that.
- For a hw_algo="toggle" device, the gpio is requested as output if the
always-running flag is set, otherwise as input.
- The ->start() method is updated to change the direction to output when
required (i.e. it is not always-running).
- The ->stop() method is implemented, but of course reports failure if
always-running.
As I still haven't met any hw_algo="level" devices, I'm not entirely
sure how they fit in, but I'm borrowing logic from the corresponding
linux driver:
- In ->probe(), such devices always request the gpio as GPIOD_IS_OUT.
- In ->stop(), the linux driver has an "eternal ping" comment and sets
the gpio to (logic) high.
Stefan:
Added necessary changes in test/dm/wdt.c to fix CI build breakage, as
suggested by Rasmus.
Signed-off-by: Rasmus Villemoes <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Fix compile warning with !CONFIG_FDT_64BIT by
casting the variable in the debug print.
Signed-off-by: Eva Kurchatova <[email protected]>
Reported-by: Leo Yu-Chi Liang <[email protected]>
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Chia-Wei Wang <[email protected]> says:
Aspeed AST2700 SoCs integrates the Caliptra secure IP, where an ECDSA384
signature verification HW interface is exported for SoC crypto needs.
This patch series firstly extends the FIT image signing/verify common
code to support the ECDSA384 algorithm. For better convenience, the
device tree for ECDSA public key storage is also revised by referring
to RSA implementations.
After the FIT common code revision, the driver is implemented for
AST2700 to leverage the Caliptra ECDSA384 signature verification.
These are verified by signed FIT images with the algorithm "sha384,ecdsa384".
Link: https://lore.kernel.org/r/[email protected]
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Aspeed AST27xx SoCs integrate the CPTRA 1.0 secure IP, which export
an ECDSA384_SIGNATURE_VERIFY mailbox command service for SoC to use.
This patch is verified by the FIT signature verification using the
"sha384,ecdsa384" algorithm.
Signed-off-by: Chia-Wei Wang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Manorit Chawdhry <[email protected]> says:
This series adds support for Adaptive voltage scaling on J721S2 device [0].
[0]: https://www.ti.com/lit/pdf/spruj28 (Section 5.2.4.1 AVS Support)
AVS Test for J721S2: https://gist.github.com/manorit2001/b2fd9f6764a863294d4aa0755c83c84f
Boot Test results: https://gist.github.com/manorit2001/d44e035552cb19aadeb0d928d5cb5f26
Link: https://lore.kernel.org/r/[email protected]
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Different devices have different MPU clk and dev ID. Currently it had
been hardcoded. Move it to DT based extraction.
Signed-off-by: Manorit Chawdhry <[email protected]>
Reviewed-by: Aniket Limaye <[email protected]>
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Check if AVS could not be programmed and print a warning.
Fixes: 9d233b4e3ed6 ("misc: k3_avs: add driver for K3 Adaptive Voltage Scaling Class 0")
Reviewed-by: Udit Kumar <[email protected]>
Signed-off-by: Manorit Chawdhry <[email protected]>
Reviewed-by: Aniket Limaye <[email protected]>
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This Kconfig depends on DM_PMIC but hadn't be explicitly stated which
could cause config related issues.
Adds the dependency in Kconfig for tps65941.
Fixes: 6b86dd0c1ead ("power: pmic: tps65941: Add support for tps65941 family of PMICs")
Reviewed-by: Neha Malcom Francis <[email protected]>
Signed-off-by: Manorit Chawdhry <[email protected]>
Reviewed-by: Aniket Limaye <[email protected]>
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Siddharth Vadapalli <[email protected]> says:
Hello,
This series adds support for the Cadence PCIe controller on TI's K3
family of SoCs to which the J7200 SoC belongs. The driver is an adaptation
of the Linux driver (drivers/pci/controller/cadence/pci-j721e.c) and has
been implemented specifically for Root-Complex mode of operation on the
J7200 SoC. A minor set of changes will be sufficient to support other K3
SoCs as well with plans to implement it in the near future.
Link: https://lore.kernel.org/r/[email protected]
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Add support for the Cadence PCIe Controller present on TI's K3 SoCs.
This driver is an adaptation of the Linux driver.
Signed-off-by: Siddharth Vadapalli <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Some I2C slave devices are read-only and don't even answer with NACK.
For example FD65x segment LED controllers.
Make them usable with i2c-gpio,sda-output-only that are already supported
by Linux 6.3+.
Signed-off-by: Alex Shumsky <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Add support for the following Maxim chips using the existing PCA954x
driver:
- MAX7356
- MAX7357
- MAX7358
- MAX7367
- MAX7368
- MAX7369
All added Maxim chips behave like the PCA954x, where a single SMBUS byte
write selects up to 8 channels to be bridged to the primary bus.
Tested using the MAX7358.
Signed-off-by: Maksim Kiselev <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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When starting a new text line, an assumption is made that the current
vertical position is a multiple of the character height. When this is
not true, characters can be written after the end of the framebuffer.
This can causes crashes and strange errors from QEMU.
Adjust the scrolling check when processing a newline character, to
avoid any problems.
Add some comments to make things a little clearer.
Signed-off-by: Simon Glass <[email protected]>
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This is useful for highlighting something with a black background, as
is needed with cedit when using a white-on-black console. Add this as
a new colour.
Signed-off-by: Simon Glass <[email protected]>
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Since we are using the code from Linux, update it to the newer version
in v6.11
Signed-off-by: Simon Glass <[email protected]>
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When the clock speed is above about 4GHz, e.g. on modern PC hardware,
the timer overflows, resulting in a much lower frequency than expected.
Deal with this by capping the clock speed.
It would be possible to move to a 64-bit value for the clock, but that
is a pain to deal with. A better approach might be to express the clock
in MHz but that is left for later consideration.
Signed-off-by: Simon Glass <[email protected]>
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When bootstage is used the timer can be inited before the CPU identity
is set up, resulting in the checks for the vendor not working.
Add a special call to work around this.
Signed-off-by: Simon Glass <[email protected]>
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Co-developed-by: Cody Schuffelen <[email protected]>
Signed-off-by: Cody Schuffelen <[email protected]>
Signed-off-by: Dmitrii Merkurev <[email protected]>
Cc: Tuomas Tynkkynen <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Mattijs Korpershoek <[email protected]>
Cc: Ying-Chun Liu (PaulLiu) <[email protected]>
Tested-by: Mattijs Korpershoek <[email protected]> # sandbox
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22796
- Switch to using upstream DT on DH i.MX8MP DHCOM PDK2/PDK3.
- Add ability to build fallback DTBOs from arch/$(ARCH)/dts.
- Remove fdt_high and initrd_high env variables from imx6-dhcom.
- Add dummy clk for imx8.
- Fix DT corruption in imx8_cpu.
- Improve DDR stability on pico-imx7d.
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U-Boot device tree is padded just after U-Boot proper.
After the whole stuff loaded to DRAM space, the device tree
area is conflict with BSS region before U-Boot relocation.
So any write to BSS area before reloc_fdt will corrupt the
device tree. Without the fix, there is issue that “binman_init
failed:-2” on i.MX8MP-EVK board.
Drop 'revision' and use malloc area in cpu_imx_plat->rev.
Signed-off-by: Peng Fan <[email protected]>
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There is a dummy clk entry for i.MX8QM/QXP, so add the dummy clk enable
and get rate. Otherwise "__imx8_clk_enable(Invalid clk ID #0)".
Fixes: 76332fae769 ("mmc: fsl_esdhc_imx: Enable AHB/IPG clk with clk bulk API")
Reviewed-by: Heiko Schocher <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Tested-by: Heiko Schocher <[email protected]>
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Prasanth Babu Mantena <[email protected]> says:
The channel allocation and deallocation for dma copy was happening on every
dma transfer. This is a overhead for transactions like NAND, which does
page reads recursively for complete data.
So, moving the dma allocation to probe and implement corresponding
remove function and cleanup dma device while exiting from spl.
Enable SPL_DM_DEVICE_REMOVE, for device removal capability in SPL.
Link: https://lore.kernel.org/r/[email protected]
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Currently, the allocation of DMA channel[0] for memcpy is happening
in udma_transfer() for every transfer, which leads to a huge overhead
for each transfer, especially in case of nand page reads. So, move this
allocation to udma_probe(), as a result, the allocation is done once
during probe.
Introduce udma_remove() for the cleanup of allocated channel during
probe.
Signed-off-by: Santhosh Kumar K <[email protected]>
Signed-off-by: Prasanth Babu Mantena <[email protected]>
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The udma_probe() function was placed above many important APIs
related to bcdma, pktdma, which restricts these APIs to be accessed
during probe. So, move udma_probe() below all of them.
Signed-off-by: Santhosh Kumar K <[email protected]>
Signed-off-by: Prasanth Babu Mantena <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20241017
CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/22742
Usb Gadget:
- Fix cdns3 endpoint configuration by setting maxpacket
- Fix dwc3 cache handling when using DMA
Fastboot:
- Make AVB_VERIFY depends on FASTBOOT
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Now that the TCPM framework exists we can introduce fusb302
driver using it. This chip is a very common USB-C controller
chip with PD support, which can be found in the Radxa Rock 5B
among many other boards. Apart from Power Delivery, it also
handles detection of the cable orientation. That can be used
to control a mux for connecting the right USB3 lane pair to
the USB3 controller.
The driver is originally from the Linux kernel, but has been
adapted to the requirements of U-Boot and its TCPM framework.
Co-developed-by: Wang Jie <[email protected]>
Signed-off-by: Wang Jie <[email protected]>
Tested-by: Soeren Moch <[email protected]>
Tested-by: Anand Moon <[email protected]>
Reviewed-by: Jonas Karlman <[email protected]>
Signed-off-by: Sebastian Reichel <[email protected]>
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This adds TCPM framework in preparation for fusb302 support, which can
handle USB power delivery messages. This is needed to solve issues with
devices, that are running from a USB-C port supporting USB-PD, but not
having a battery.
Such a device currently boots to the kernel without interacting with
the power-supply at all. If there are no USB-PD message replies within
5 seconds, the power-supply assumes the peripheral is not capable of
USB-PD. It usually takes more than 5 seconds for the system to reach
the kernel and probe the I2C based fusb302 chip driver. Thus the
system always runs into this state. The power-supply's solution to
fix this error state is a hard reset, which involves removing the
power from VBUS. Boards without a battery (or huge capacitors) will
reset at this point resulting in a boot loop.
This imports the TCPM framework from the kernel. The porting has
originally been done by Rockchip using hardware timers and the Linux
kernel's TCPM code from some years ago.
I had a look at upgrading to the latest TCPM kernel code, but that
beast became a lot more complex due to adding more USB-C features.
I believe these features are not needed in U-Boot and with multiple
kthreads and hrtimers being involved it is non-trivial to port them.
Instead I worked on stripping down features from the Rockchip port
to an even more basic level. Also the TCPM code has been reworked
to avoid complete use of any timers (Rockchip used SoC specific
hardware timers + IRQ to implement delayed work mechanism). Instead
the delayed state changes are handled directly from the poll loop.
Note, that (in contrast to the original Rockchip port) the state
machine has the same hard reset quirk, that the kernel has - i.e.
it avoids disabling the CC pin resistors for devices that are not
self-powered. Without that quirk, the Radxa Rock 5B will not just
end up doing a machine reset when a hard reset is triggered, but will
not even recover, because the CPU will loose power and the FUSB302
will keep this state because of leak voltage arriving through the RX
serial pin (assuming a serial adapter is connected).
This also includes a 'tcpm' command, which can be used to get
information about the current state and the negotiated voltage
and current.
Co-developed-by: Wang Jie <[email protected]>
Signed-off-by: Wang Jie <[email protected]>
Tested-by: Soeren Moch <[email protected]>
Tested-by: Anand Moon <[email protected]>
Reviewed-by: Jonas Karlman <[email protected]>
Signed-off-by: Sebastian Reichel <[email protected]>
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