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If SPL is passing video handoff structure to U-boot then it is safe to
assume that SPL has already enabled video and that's why it is passing
video handoff structure to U-boot so that U-boot can preserve the
framebuffer.
Signed-off-by: Devarsh Thakkar <[email protected]>
Reviewed-by: Nikhil M Jain <[email protected]>
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simplefb was using old style FDT parsing which doesn't behave well in
combination with livetree. Update it to use ofnode instead and add a
missing null check for the "format" property.
Standardise the error logging while we're here.
Fixes: 971d7e64245d ("video: simplefb")
Signed-off-by: Caleb Connolly <[email protected]>
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Shift all setup stages one step earlier to better fit the
existing uclass.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Shift all setup stages one step earlier to better fit the
existing uclass.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Shift all setup stages one step earlier to better fit the
existing uclass.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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The Parade DP501 is a DP & DVI/HDMI dual-mode transmitter. It
enables an RGB/Parallel SOC output to be converted, packed and
serialized into either DP or TMDS output device. Only DisplayPort
functionality of this transmitter has been implemented and tested.
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Add initial support for the Toshiba TC358768 RGB to DSI bridge.
The driver is based on the mainline Linux Toshiba TC358768
bridge driver and implements the same set of features.
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS TF700T
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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LTL106HL02 is a color active matrix TFT (Thin Film Transistor)
liquid crystal display (LCD) that uses amorphous silicon TFT as
switching devices. This model is composed of a TFT LCD panel, a
driver circuit and a backlight unit. The resolution of a 10.6"
contains 1920 x 1080 pixels and can display up to 16,8M color
with wide viewing angle.
Co-developed-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Jonas Schwöbel <[email protected]>
Co-developed-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Signed-off-by: Anton Bambura <[email protected]>
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The LD070WX3 is a Color Active Matrix Liquid Crystal Display with
an integral Light Emitting Diode (LED) backlight system. The
matrix employs a-Si Thin Film Transistor as the active element. It
is a transmissive type display operating in the normally Black
mode. This TFT-LCD has 7.0 inches diagonally measured active
display area with WXGA resolution (800 by 1280 pixel array).
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Shift the backlight set further to prevent visual glitches on
panel init.
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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According to Thierry Reding's commit in the linux kernel
976cebc35bed0456a42bf96073a26f251d23b264
"drm/tegra: dsi: Make FIFO depths host parameters"
correct depth of the video FIFO is 1920 *words* no *bytes*
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Configuration for DC driver command mode is not required for
every panel. Removed.
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Implement reset use to discard any changes which could have been
applied to DSI before and can interfere with current configuration.
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Existing Tegra DSI driver mostly fits T114 apart MIPI calibration
which on T114 has dedicated driver. To resolve this MIPI calibration
logic was split for pre-T114 and T114+ devices.
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Dedicated MIPI calibration driver is used on T114 and newer. Before
T114 MIPI calibration registers were part of VI and CSI.
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Based on Thierry Reding's Linux commit:
'commit 1716b1891e1de05e2c20ccafa9f58550f3539717
("drm/tegra: rgb: Parameterize V- and H-sync polarities")'
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Fill the framebuffer memory with zeros to avoid visual glitches.
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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The goal of panel_set_backlight() is to enable backlight. Hence,
it should be called at the probe end.
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Framebuffer address should not be a pointer.
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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If DISP1 is a PLLD/D2 child, it cannot go over 370MHz. The cause
of this is not quite clear. This can be overcomed by further
halving the PLLD/D2 if the target parent rate is over 800MHz.
This way DISP1 and DSI clocks will have the same frequency. The
shift divider in this case has to be calculated from the
original PLLD/D2 frequency and is passed from the DSI driver.
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Tested-by: Jonas Schwöbel <[email protected]> # Microsoft Surface 2
Signed-off-by: Jonas Schwöbel <[email protected]>
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Acked-by: Thierry Reding <[email protected]>
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Add powergate use on T114 to complete resetting of DC.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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T30+ SOC have second PLLD - PLLD2 which can be actively used by
DC and act as main DISP1/2 clock parent.
Tested-by: Agneli <[email protected]> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Tegra SoC has 2 independent display controllers called DC_A and
DC_B, they are handled differently by internal video devices like
DSI and HDMI controllers so it is important for last to know
which display controller is used to properly set up registers.
To achieve this, a pipe field was added to pdata to pass display
controller id to internal Tegra SoC devices.
Tested-by: Agneli <[email protected]> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Consolidate HD headers and place the result into video/tegra20
since it is used only by devices from this directory.
Tested-by: Agneli <[email protected]> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Subtracting 1 from x and y fixes image shifting on rotated
panels.
Tested-by: Robert Eckelmann <[email protected]> # ASUS Grouper E1565
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
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Diverge DC driver setup to better fit each of supported generations
of Tegra SOC.
Tested-by: Agneli <[email protected]> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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GCC-14 find more warnings like
"make pointer from integer without a cast"
fix them by adding a type cast.
Signed-off-by: Khem Raj <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
Cc: Tom Rini <[email protected]>
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Add support for Rockchip RK3328 VOP.
Require VOP cleanup before handoff to Linux by writing reset values to
WIN registers. Without this Linux VOP trigger page fault as below
[ 0.752016] Loading compiled-in X.509 certificates
[ 0.787796] inno_hdmi_phy_rk3328_clk_recalc_rate: parent 24000000
[ 0.788391] inno-hdmi-phy ff430000.phy: inno_hdmi_phy_rk3328_clk_recalc_rate rate 148500000 vco 148500000
[ 0.798353] rockchip-drm display-subsystem: bound ff370000.vop (ops vop_component_ops)
[ 0.799403] dwhdmi-rockchip ff3c0000.hdmi: supply avdd-0v9 not found, using dummy regulator
[ 0.800288] rk_iommu ff373f00.iommu: Enable stall request timed out, status: 0x00004b
[ 0.801131] dwhdmi-rockchip ff3c0000.hdmi: supply avdd-1v8 not found, using dummy regulator
[ 0.802056] rk_iommu ff373f00.iommu: Disable paging request timed out, status: 0x00004b
[ 0.803233] dwhdmi-rockchip ff3c0000.hdmi: Detected HDMI TX controller v2.11a with HDCP (inno_dw_hdmi_phy2)
[ 0.805355] dwhdmi-rockchip ff3c0000.hdmi: registered DesignWare HDMI I2C bus driver
[ 0.808769] rockchip-drm display-subsystem: bound ff3c0000.hdmi (ops dw_hdmi_rockchip_ops)
[ 0.810869] [drm] Initialized rockchip 1.0.0 20140818 for display-subsystem on minor 0
Signed-off-by: Jagan Teki <[email protected]>
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Add Rockchip RK3328 HDMI Out driver.
Signed-off-by: Jagan Teki <[email protected]>
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Add Rockchip INNO HDMI PHY driver for RK3328.
Reference from linux-next phy-rockchip-inno-hdmi driver.
Signed-off-by: Jagan Teki <[email protected]>
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Add support to get the hdmiphy clock for RK3328 PCLK_HDMIPHY.
Signed-off-by: Jagan Teki <[email protected]>
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VOP get and set clock would needed for VOP drivers.
Add support for it.
Signed-off-by: Jagan Teki <[email protected]>
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Unlike RK3399, RK3288 the Newer Rockchip SoC's like RK3328 have
different offsets for dsp registers.
Group the dsp register set via dsp_regs pointers so that dsp_offset
would point the dsp_regs to access for any changes in the offset value.
Signed-off-by: Jagan Teki <[email protected]>
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Unlike RK3399, RK3288 the Newer Rockchip SoC's like RK3328 have
different offsets for win registers.
Group the win register set via win_regs pointers so that win_offset
would point the win_regs to access for any changes in the offset value.
Signed-off-by: Jagan Teki <[email protected]>
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Get the regs from priv pointer instead of passing it an argument.
This would simplify the code and better readability.
Signed-off-by: Jagan Teki <[email protected]>
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Add support for DW HDMI Setup HPD status.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
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Add support for DW HDMI Read HPD status.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
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HPD detection on some DW HDMI designed SoC's would need to read and
setup the HPD status explicitly.
So, extend the HPD detection code by adding the dw_hdmi_detect_hpd
function and move the default detection code caller there.
The new read and setup hdp will integrate the same function in
later patches.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
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DW HDMI support Vendor PHY like Rockchip RK3328 Inno HDMI PHY.
Extend the vendor phy handling by adding platform phy hooks.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
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HDP is a hardware connector event, so detect the same once the
controller and attached PHY initialization are done.
Signed-off-by: Jagan Teki <[email protected]>
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Support timing parsing from EDID if panel device tree node
provides DDC i2c bus instead of timings node.
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF201
Tested-by: Agneli <[email protected]> # Toshiba AC100 T20
Signed-off-by: Svyatoslav Ryhel <[email protected]>
[agust: reworked to fix dm_i2c_* build errors and to big img size]
Signed-off-by: Anatolij Gustschin <[email protected]>
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Pass MIPI DSI platform data to simple DSI panel directly
from driver data on panel probe.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Add support for the IMX8MM SoC by adding driver data with the compatible
string of the GPR controller.
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Tim Harvey <[email protected]>
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Add support for PCIe clocks required to enable PCIe support on
iMX8MM SoC.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-stm
MP1:
_ Add OHCI HCD support for STM32MP15xx DHSOM
_ Report OTP-CLOSED instead of rev.? on closed STM32MP15xx
_ Initialize TAMP_SMCR BKP..PROT fields on STM32MP15xx
_ Jump to ep on successful resume in PSCI suspend code
_ Add FASTBOOT support for STM32MP13
_ Fix/Rework key and leds management for STM32MP13/15
_ net: dwc_eth_qos: Clean up STM32 glue code and add STM32MP13xx support
MP2:
_ Add stm32-fmc-ebi support
_ Add: sdmmc2 support and fix AARCH64 compilation
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https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20240419
- new "fastboot oem board" command
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When building with AARCH64 defconfig, we got warnings, fix them.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Add compatible used for STM32MP25 family.
Signed-off-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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The "st,ext-phyclk" property is a unification of "st,eth-clk-sel"
and "st,eth-ref-clk-sel" properties. All three properties define
ETH CK clock direction, however:
- "st,eth-clk-sel" selects clock direction for GMII/RGMII mode
- "st,eth-ref-clk-sel" selects clock direction for RMII mode
- "st,ext-phyclk" selects clock direction for all RMII/GMII/RGMII modes
The "st,ext-phyclk" is the preferrable property to use.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Christophe ROULLIER <[email protected]>
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Add compatible "st,stm32mp13-dwmac" to manage STM32MP13 boards.
Reviewed-by: Patrice Chotard <[email protected]>
Signed-off-by: Christophe Roullier <[email protected]>
Signed-off-by: Marek Vasut <[email protected]> # Rebase, reshuffle, squash code
Reviewed-by: Christophe ROULLIER <[email protected]>
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