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The current glue code is specific to STM32MP15xx, the upcoming STM32MP13xx
will introduce another entry specific to the STM32MP13xx. Rename the current
entry to eqos_stm32mp15_config in preparation for STM32MP13xx addition. No
functional change.
Reviewed-by: Patrice Chotard <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Christophe ROULLIER <[email protected]>
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Move STM32 glue code into separate file to contain the STM32 specific
code outside of the DWMAC core code. No functional change.
Reviewed-by: Patrice Chotard <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Christophe ROULLIER<[email protected]>
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FMC2 IP supports up to 4 chip select. On MP1 SoC, only 2 of them are
available when on MP25 SoC, the 4 chip select are available.
Let's use a platform data structure for parameters that will differ.
Signed-off-by: Christophe Kerello <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The FMC2 revision 2 supports security and isolation compliant with
the Resource Isolation Framework (RIF). From RIF point of view,
the FMC2 is composed of several independent resources, listed below,
which can be assigned to different security and compartment domains:
- 0: Common FMC_CFGR register.
- 1: EBI controller for Chip Select 1.
- 2: EBI controller for Chip Select 2.
- 3: EBI controller for Chip Select 3.
- 4: EBI controller for Chip Select 4.
- 5: NAND controller.
Signed-off-by: Christophe Kerello <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add the support of the revision 2 of FMC2 IP.
- PCSCNTR register has been removed,
- CFGR register has been added,
- the bit used to enable the IP has moved from BCR1 to CFGR,
- the timeout for CEx deassertion has moved from PCSCNTR to BCRx,
- the continuous clock enable has moved from BCR1 to CFGR,
- the clk divide ratio has moved from BCR1 to CFGR.
The MP1 SoCs have only one signal to manage all the controllers (NWAIT).
The MP25 SOC has one RNB signal for the NAND controller and one NWAIT
signal for the memory controller.
Let's use a platform data structure for parameters that will differ
between MP1 and MP25.
Signed-off-by: Christophe Kerello <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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If a button device fails to probe, it will still be added to the uclass
device list, and therefore will still be iterated over in
button_read_keys() resulting in a UAF on the buttons private data.
Resolve this by unbinding button devices that aren't active after
probing, and print a warning so it's clear that the button is broken.
Fixes: e8779962898e ("dm: input: add button_kbd driver")
Signed-off-by: Caleb Connolly <[email protected]>
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Reading the boot mode from RTC memory requires a real time clock.
Add the missing Kconfig dependency.
Fixes: c74675bd904b ("reboot-mode: read the boot mode from RTC memory")
Signed-off-by: Heinrich Schuchardt <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-tpm
Igor says:
"The problem initially was in the TEE sandbox driver implementation
(drivers/tee/sandbox.c) and it's limitations, which doesn't
permit to have multiple simultaneous sessions with different TAs.
This is what actually happened in this CI run [1], firstly "optee_rpmb"
cmd was executed (and after execution we had one session open), and
then "scp03", which also makes calls to OP-TEE, however it fails
in sandbox_tee_open_session() because of this check:
if (state->ta) {
printf("A session is already open\n");
return -EBUSY;
}
I had two ways in mind to address that:
1. Close a session on each optee_rpmb cmd invocation.
I don't see any reason to keep this session open, as obviously
there is no other mechanism (tbh, I don't know if DM calls ".remove" for active
devices) to close it automatically before handing over control to
Linux kernel. As a result we might end up with some orphaned sessions
registered in OP-TEE OS core (obvious resource leak).
2. Extend TEE sandbox driver, add support for multiple
simultaneous sessions just to handle the case.
I've chosen the first approach, as IMO it was "kill two birds with one stone",
I could address resource leak in OP-TEE and bypass limitations of
TEE sandbox driver."
Link: https://lore.kernel.org/u-boot/CAByghJZVRbnFUwJdgU534tvGA+DX2pArf0i7ySik=BrXgADe3Q@mail.gmail.com/
The CI https://source.denx.de/u-boot/custodians/u-boot-tpm/-/pipelines/20414
showed no problems
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https://source.denx.de/u-boot/custodians/u-boot-mpc8xx
This pull request adds support for temperature sensors et FPGA loading
on boards from CS GROUP France.
CI: https://source.denx.de/u-boot/custodians/u-boot-mpc8xx/-/pipelines/20416
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enabled""
As reported by Jonas Karlman this series breaks booting on some AArch64
platforms with common use cases. For now the best path forward is to
revert the series.
This reverts commit 777c28460947371ada40868dc994dfe8537d7115, reversing
changes made to ab3453e7b12daef47b9e91da2a2a3d48615dc6fc.
Link: https://lore.kernel.org/u-boot/[email protected]/
Signed-off-by: Tom Rini <[email protected]>
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Set the speed requested through mpc8xx_spi_set_speed() instead
of hardcoding a fixed speed.
Signed-off-by: Christophe Leroy <[email protected]>
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On CPM, the RISC core is a lot more efficiant when doing transfers
in 16-bits chunks than in 8-bits chunks, but unfortunately the
words need to be byte swapped.
So, for large tranfers with an even size, allocate a temporary
buffer and byte-swap data before and after transfer.
This change allows setting higher speed for transfer. For instance
on an MPC 8xx (CPM1 comms RISC processor), the documentation tells
that transfer in byte mode at 1 kbit/s uses 0.200% of CPM load
at 25 MHz while a word transfer at the same speed uses 0.032%
of CPM load. This means the speed can be 6 times higher in
word mode for the same CPM load.
For small transfers, the load reduction is not worth the CPU load
required to allocate the temporary buffer, so do it only when data
size is over 64 bytes.
Signed-off-by: Christophe Leroy <[email protected]>
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Perform multiple transfer of size MAX_BUFFER when the data to be
transferred is longer than MAX_BUFFER.
Signed-off-by: Christophe Leroy <[email protected]>
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SDMA configuration register needs to be set up only once and doesn't
belong to drivers. Also, the value to be used is different on mpc885.
So do the init in cpu_init_f() with 0x40 for mpc885 and 0x1 for others.
Signed-off-by: Christophe Leroy <[email protected]>
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LM74 is a SPI temperature sensor.
Implement a driver to read temperature from it.
Signed-off-by: Christophe Leroy <[email protected]>
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xfer ops can be passed a NULL input or output buffer. At the
time being the driver ignores it and overwrites memory at 0.
Define a dummy buffer and use it when either input or output
buffer is NULL. Bail out when both are NULL as it shouldn't.
Also increase MAX_BUFFER len to 32k as the current is pretty
low.
Signed-off-by: Christophe Leroy <[email protected]>
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Since commit 773ad4ebb1d6 ("spi, mpc8xx: Add support for chipselect via
GPIO and fixups"), DM_GPIO is required for 8xx SPI.
Add the missing dependency to avoid build failures.
Fixes: 773ad4ebb1d6 ("spi, mpc8xx: Add support for chipselect via GPIO and fixups")
Signed-off-by: Christophe Leroy <[email protected]>
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The usage of the common.h include file is deprecated [1], and has already
been removed from several files.
Get rid of all inclusions in the "drivers/tee" directory, and replace it
with required include files directly where needed.
[1] doc/develop/codingstyle.rst
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Igor Opaniuk <[email protected]>
Reviewed-by: Sam Protsenko <[email protected]>
Signed-off-by: Ilias Apalodimas <[email protected]>
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Fix OPTEE_TA_AVB symbol description in Kconfig:
s/"write"rb"/"write_rb"/g
Reviewed-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Igor Opaniuk <[email protected]>
Signed-off-by: Ilias Apalodimas <[email protected]>
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Currently, fastboot protocol in U-Boot has no opportunity
to execute vendor custom code with verifed boot. This patch
introduce new fastboot subcommand fastboot oem board:<cmd>,
which allow to run custom oem_board function.
Default implementation is __weak. Vendor must redefine it in
board/ folder with his own logic.
For example, some vendors have their custom nand/emmc partition
flashing or erasing. Here some typical command for such use cases:
- flashing:
$ fastboot stage bootloader.img
$ fastboot oem board:write_bootloader
- erasing:
$ fastboot oem board:erase_env
Signed-off-by: Alexey Romanov <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI:
https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/20348
- Update the imx_rgpio2p to only access one address as per the
dt-schema.
- Remove unused imx9_cpu.c file.
- Only use the LPUART ipg clk for i.MX7ULP.
- Use the correct anatop base for accessing the PLL clocks on i.MX93.
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The PLL clk needs use anatop base, otherwise wrong PLL address will
be used.
Fixes: 9c153e46661b ("clk: imx: add i.MX93 CCF driver")
Signed-off-by: Peng Fan <[email protected]>
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This was wrongly committed, no user, remove it.
Signed-off-by: Peng Fan <[email protected]>
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To i.MX7ULP compatible lpuart, there is only ipg clk, no per clk.
So add a devtype check for i.MX7ULP.
Signed-off-by: Peng Fan <[email protected]>
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The i.MX8ULP/93 gpio dt-schema have been updated to only have one
address entry, update the driver to support it.
Signed-off-by: Peng Fan <[email protected]>
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Remove the unused argument about cmd_error.
Fixes: a3b2786651c7 ("mmc: Drop unused mmc_send_tuning() cmd_error parameter")
Signed-off-by: Jaehoon Chung <[email protected]>
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The value defaults to 0 and is ignored by dw_mmc code, so the other
users are not affected.
Setting this explicitly fixes some weird reading error found on Hi3798MV200.
Fixes: 8a5dc8140e62 ("mmc: hi6220_dw_mmc: add compatible for HC2910 support")
Signed-off-by: Yang Xiwen <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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As described in [1], some poor hardware or cards would fail to release
the bus and keep driving data lines low. Ignore it and send the next cmd
directly seems okay for most cases.
[1]: https://patchwork.kernel.org/project/linux-mmc/patch/[email protected]/
Signed-off-by: Yang Xiwen <[email protected]>
Tested-by: Jaehoon Chung <[email protected]>
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CONFIG_DM_RESET enabled
This can avoid hardcoding a clock rate in driver. Also can enable the
clocks and deassert the resets if the pre-bootloader does not do this
for us.
Currently only enabled for Hi3798MV200.
Signed-off-by: Yang Xiwen <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Place the SDR104/HS200/HS400 checks into the mmc_deinit() and always
call it. This simplifies the code and removes ifdeffery. No functional
change is expected.
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Dragan Simic <[email protected]>
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Do not access SCC when sending commands during tuning operation as that
will disrupt the tuning operation. The tuning operation is adjusting the
SCC settings itself in execute_tuning callback.
When renesas_sdhi_execute_tuning() is called by the MMC core code, a loop
which consists of renesas_sdhi_prepare_tuning(), mmc_send_tuning() and
renesas_sdhi_compare_scc_data() iterates over each SCC tuning tap.
The renesas_sdhi_prepare_tuning() configures the SCC tuning tap number into
hardware, mmc_send_tuning() triggers transfer of tuning block which depends
on the bus mode for which the bus is currently being tuned, this information
is supplied by the MMC core code, and finally renesas_sdhi_compare_scc_data()
tests the received tuning block for validity.
Because renesas_sdhi_prepare_tuning() configures the SCC tuning tap into
the hardware to fit the tuning operation, mmc_send_tuning() which triggers
command transfer using renesas_sdhi_send_cmd() must not manipulate with
the SCC in any way. Currently renesas_sdhi_send_cmd() does unconditionally
call renesas_sdhi_check_scc_error(), which may adjust the SCC tuning tap
position by writing RENESAS_SDHI_SCC_TAPSET, which would overwrite the
required tuning configuration set by renesas_sdhi_prepare_tuning() and
disrupt the tuning operation.
Fix this by skipping the renesas_sdhi_check_scc_error() call in case the
MMC subsystem is in tuning state. This way, the SCC settings are left
unmodified by command transfer during tuning operation.
Reviewed-by: Paul Barker <[email protected]>
Tested-by: Paul Barker <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Set generic mmc->tuning flag when performing tuning to indicate
this condition to drivers. Drivers may use this to bypass various
checks during tuning.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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This hs400_tuning is a flag, make it bool. No functional change.
This will be useful in the following patch, which adds another
more generic flag, where the compiler can better use the space
now reserved for the u8 to store more flags in it.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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The current code uses the state of tuning block received by SCC to
determine whether or not to send transmission stop command. This is
not correct. Use the state of tuning block transfer to determine
whether or not to send transmission stop command instead, because
the transmission stop command has to be sent in case the tuning
block transfer failed.
This requires two changes, separate variable to store and check the
state of tuning block received by SCC, and another separate variable
to store and check return value from transmission stop command.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
Tested-by: Paul Barker <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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In case a CRC error occurs during DMA transfer, the transfer completion
flag is not set in TMIO_SD_DMA_INFO1 and the transfer would eventually
time out. The timeout could be very long in case the transfer consists
of a large amount of blocks, the base timeout is 10 seconds and every
block adds 100 us more.
In case a CRC error does occur, a completion flag is set in a different
register, TMIO_SD_INFO1. Use this other completion flag to detect DMA
transfer ended and stop waiting for TMIO_SD_DMA_INFO1 completion flag.
This reduces the lengthy timeout in case of an error. The unconditional
check of TMIO_SD_DMA_INFO2 register for DMA related errors must not be
skipped in any case to actually recognize the DMA error and report it.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Paul Barker <[email protected]>
Tested-by: Paul Barker <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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The cmd_error parameter is not used, remove it.
Signed-off-by: Marek Vasut <[email protected]>
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The PL180/MMCI driver is implied to use CONFIG_DM and the ARM
defconfigs such as configs/vexpress_ca9x4_defconfig will get it
as well.
With a simple oneline to default to not being the v2 variant,
the original ARM MMCI variant works fine with the driver as well.
The IP version actually needs to be read out from a register on
the ARM versions, but we will simply assume we are running on the
original hardware if arm,primecell-periphid is not explicitly
specified in the device tree.
Drop the !CONFIG_DM code and depend on DM_MMC.
Tested on the Versatile Express CA9x4 board.
Signed-off-by: Linus Walleij <[email protected]>
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With MMC_PWRSEQ enabled the following link issue may happen when
building SPL and SPL_PWRSEQ is not enabled.
aarch64-linux-gnu-ld.bfd: drivers/mmc/meson_gx_mmc.o: in function `meson_mmc_probe':
drivers/mmc/meson_gx_mmc.c:295: undefined reference to `pwrseq_set_power'
Fix this by adding a SPL_MMC_PWRSEQ Kconfig option used to enable mmc
pwrseq support in SPL.
Also add depends on DM_GPIO to fix following link issue:
aarch64-linux-gnu-ld.bfd: drivers/mmc/mmc-pwrseq.o: in function `mmc_pwrseq_set_power':
drivers/mmc/mmc-pwrseq.c:26: undefined reference to `gpio_request_by_name'
aarch64-linux-gnu-ld.bfd: drivers/mmc/mmc-pwrseq.c:29: undefined reference to `dm_gpio_set_value'
aarch64-linux-gnu-ld.bfd: drivers/mmc/mmc-pwrseq.c:31: undefined reference to `dm_gpio_set_value'
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Acked-by: Ferass El Hafidi <[email protected]>
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U-Boot does not support building kernel modules.
Fixes: 3c0dbed232bd ("mmc: arm_pl180_mmci: adapt driver to DM usage")
Fixes: 36645f45a048 ("drivers: mmc: Add sdhci driver for Broadcom iProc platform")
Fixes: dadd43c14368 ("mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver")
Fixes: b312c590bcd8 ("mmc: Add MMC support for stm32h7 Socs")
Fixes: d24b69395949 ("mmc: mtk-sd: add SD/MMC host controller driver for MT7623 SoC")
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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If the CSD register contains a reserved value (4 - 7) in bits 0:2 of the
TRAN_SPEED field, a buffer overrun occurs. Resize the mapping table.
According to the original report
https://lore.kernel.org/u-boot/[email protected]/
reserved values have been observed resulting in a buffer overrun.
Reported-by: Eugeniu Rosca <[email protected]>
Fixes: 272cc70b211e ("Add MMC Framework")
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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CONFIG_SPL_SOCFPGA_DT_REG
Commit 3f190c55a4211215914126b74357344342329943
("drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA")
This commit rename CONFIG_SPL_SOCFPGA_SEC_REG to CONFIG_SPL_SOCFPGA_DT_REG
in Makefile.
Signed-off-by: Wan Yee Lau <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-nand-flash
The first patch is by Weizhao Ouyang and avoids sf probe crashes.
The second patch is by Arseniy Krasnov and adds basic support for Amlogic
Meson NAND controller on AXG.
The following four patches are by Alexander Dahl and apply some fixes to
drivers/mtd/nand/raw/ and port some changes applied in Linux.
The following patch is by Bruce Suen and adds support for XTX SPINAND.
Finally, the last patch is again by Arseniy Krasnov and adds access to
OTP region, supporting info, dump, write and lock operations.
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Add support for XTX XT26G0xA and XT26xxxD. The driver is ported from
linux-6.7.1. This driver is tested on Banana BPI-R3 with XT26G01A and
XT26G12D.
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Bruce Suen <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Introduced with commit 6a8dfd57220d ("nand: atmel: Add DM based NAND
driver") when driver was initially ported from Linux. The context
around this and especially the code itself suggests 'read' is meant
instead of write.
The fix is the same as accepted in Linux already with mainline Linux
kernel commit 1c60e027ffde ("mtd: nand: raw: atmel: Fix comment in
timings preparation").
Link: https://lore.kernel.org/all/[email protected]
Link: https://lore.kernel.org/linux-mtd/[email protected]/T/#t
Signed-off-by: Alexander Dahl <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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One tab in general. One tab plus two spaces for help text.
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Alexander Dahl <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Introduced in upstream Linux with commit 7a08dbaedd365 for release v5.0.
When the new atmel nand driver was backported to U-Boot with commit
6a8dfd57220d ("nand: atmel: Add DM based NAND driver") that definition
was added to the driver instead of the header file. Move it over to the
other definitions with the same help text it has in Linux.
Code actually using this has not been ported over to raw nand base yet.
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Alexander Dahl <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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In every other place in this file the macro is used, make it consistent.
Link: https://lore.kernel.org/all/[email protected]
Fixes: 9d1806fadc24 ("mtd: nand: Get rid of mtd variable in function calls")
Signed-off-by: Alexander Dahl <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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Basic support for Amlogic Meson NAND controller on AXG. This version
works at only first EDO mode.
Based on Linux version 6.7.0-rc4.
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Arseniy Krasnov <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Dario Binacchi <[email protected]>
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