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On the DB410c we support running as a first stage bootloader. This
requires initialising the GPIOs which are muxed to UART before they can
be used. Add DM_FLAG_PRE_RELOC to the apq8016 pinctrl driver to ensure
that we do this early enough.
This is required to prevent the first few lines of UART log from being
dropped.
Reported-by: Sumit Garg <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]> #qcs404
Signed-off-by: Caleb Connolly <[email protected]>
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Upstream devicetrees label GPIOs with "gpioX", not "GPIO_X", fix this
for SoCs where we're now using upstream DT.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]> #qcs404
Signed-off-by: Caleb Connolly <[email protected]>
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Most platforms have a handful of "special" GPIOs, like the MMC
clock/data lanes, UFS reset, etc. These don't follow the usual naming
scheme of "gpioX" and also have unique capabilities and registers. We
can get away without supporting them all for now, but DT compatibility
is still an issue.
Add support for allowing these to be specified after the other pins, and
make all pinmux/pinconf calls for them nop.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]> #qcs404
Signed-off-by: Caleb Connolly <[email protected]>
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Introduce a basic pinctrl driver for the SPMI PMIC GPIOs. This is
necessary to make proper use of upstream DT bindings specifically on the
dragonboard410c where they're used to switch between USB host and device
modes.
Only support for driving the pins as output low or high is enabled for
now.
To minimise duplicated code and allow for sharing common DT data, the
pinctrl driver is initialised as a child of the existing GPIO driver.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]> #qcs404
Signed-off-by: Caleb Connolly <[email protected]>
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Some platforms hard reset when attempting to configure PMIC GPIOs. Add
support for quirks specified in match data with a single quirk to skip
this configuration. We rely on the GPIO already be configured correctly,
which is always the case for volume up (the only current user of these
GPIOs).
This is not expected behaviour but appears to be due to a U-Boot
specific bug. This quirk at least allows for the volume buttons to be
used on platforms where this bug is apparent.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Qualcomm PMICs number their GPIOs starting from 1, implement a custom
.xlate method to handle this.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]> #qcs404
Signed-off-by: Caleb Connolly <[email protected]>
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Use the modern helpers to fetch the clock and use the correct property
("clocks" instead of "clock"). Drop the call to pinctrl_select_state()
as no boards have a "uart" pinctrl state and this prints confusing
errors.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]> #qcs404
Signed-off-by: Caleb Connolly <[email protected]>
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Introduce support for early debugging. This relies on the previous stage
bootloader to initialise the UART clocks, when running with U-Boot as
the primary bootloader this feature doesn't work. It will require a way
to configure the clocks before the driver model is available.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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We should be returning the rate that we set the clock to, drivers like
MMC rely on this. So fix it.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]> #qcs404
Signed-off-by: Caleb Connolly <[email protected]>
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Adjust the apq8016 and apq8096 drivers to use the upstream compatible
properties, and adjust the associated dts files in U-Boot.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]> #qcs404
Signed-off-by: Caleb Connolly <[email protected]>
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Use the clk_* helper functions and the correct property name for clocks.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]> #qcs404
Signed-off-by: Caleb Connolly <[email protected]>
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Add support for a vbus-supply regulator specified in devicetree. This
provides generic support to avoid hardcoded GPIO configuration in board
init code.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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SPL is cleaning bss after calling board_init_f. Setting up console is done
and little_endian global variable is cleared which caused that console
stops to work. That's why move it to data seciton now. The patch should be
reverted when bss is cleared before board_init_f is called.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/934dc8871c59265eb9d8012193aa97d9b8bd7f33.1707911544.git.michal.simek@amd.com
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Roger Quadros <[email protected]> says:
MUX driver should autoprobe if the device tree has "idle-states"
property. Drop using the custom "u-boot,mux-autoprobe" property
in TI device trees.
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Some platforms need the MUX state to be auto initialized at
boot time even if there are no explicit users for the MUX.
In these cases, the MUX device tree has "idle-states" property
which specifies what state the MUX should be initialized to.
So far we were relying on custom u-boot property "u-boot,mux-autoprobe"
to autoprobe such MUXes. This patch causes the MUX to autoprobe
if it has "idle-states" property in device tree.
This should allow us to stop using the custom "u-boot,mux-autoprobe"
property.
Signed-off-by: Roger Quadros <[email protected]>
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If SYSRESET support is enabled for the RAA215300 PMIC, we need to bind
the raa215300_sysreset driver as a child device of the PMIC.
Signed-off-by: Paul Barker <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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This patch adds support for resetting a board via the RAA215300 PMIC.
Note that the RAA215300 documentation names the available reset types
differently to u-boot:
* A "warm" reset via the RAA215300 PMIC will fully reset the SoC
(CPU & GPIOs), so this corresponds to SYSRESET_COLD.
* A "cold" reset via the RAA215300 PMIC will cycle all power supply
rails, so this corresponds to SYSRESET_POWER.
Signed-off-by: Paul Barker <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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The RZ/G2L SMARC module is powered via a Renesas RAA215300 PMIC which
provides several voltage converters, a real time clock (RTC) and reset
control. A basic driver is implemented for this device so that we can
read, write and dump the PMIC registers.
The raa215300_bind() function is added as a stub, binding of the
sysreset driver will be added in a later patch.
Additional features of this PMIC (such as reset control) may be
supported by future patches.
Signed-off-by: Paul Barker <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044)
SoC, also known as the RIIC module.
This patch is based on both the u-boot driver in the Renesas RZ BSP
3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.7 driver
(commit 0dd3ee311255).
Support for deblocking the I2C bus is included as this may be needed
after triggering a reset via the Power Management IC (PMIC) over I2C
(the PMIC asserts the reset line before the SoC completes the I2C write
transaction with obvious bus locking effects). If the SDA line is
observed to be low during initialisation, we automatically attempt to
deblock.
[1]: https://github.com/renesas-rz/renesas-u-boot-cip
Signed-off-by: Paul Barker <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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When enabling/disabling a clock or reset signal, confirm that the change
has completed before returning from the function. A somewhat arbitrary
100ms timeout is defined to ensure that the system doesn't lock up in
the case of an error.
Since we need to dynamically determine if we're waiting for a 0 bit or a
1 bit, it's easier to use wait_for_bit_32() than readl_poll_timeout().
This change is needed for reliable initialization of the I2C driver
which is added in a following patch.
Signed-off-by: Paul Barker <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon
- Two fixes for the qcom-pmic button driver
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i.MX93 uses the same USB IP as i.MX8MM. It can then reuse the ehci-mx6
driver.
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Mathieu Othacehe <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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The datasheet can be found here:
https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25Q80B_Ver.E.pdf
Signed-off-by: Frieder Schrempf <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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To prepare support for multiple register layouts pointers to register
tables where added to struct cpg_mssr_info. These pointers are suppose
to be filled in at probe time and no intended change in behavior was
intended.
However the new pointers where only filled in by some paths of the
driver implemented in clk-rcar-gen3.c. The path implemented in
clk-rcar-gen2.c was not updated leaving the pointers uninitialized
leading to a crash when trying to probe the clocks.
Fix this by filling in the pointers in the Gen2 code path with the
values used before they where moved to struct cpg_mssr_info.
Fixes: d413214fb748 ("clk: renesas: Add register pointers into struct cpg_mssr_info")
Signed-off-by: Niklas Söderlund <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Tested-by: Marek Vasut <[email protected]> # R8A7791 Porter
Reviewed-by: Geert Uytterhoeven <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2024.04-rc3
zynqmp:
- Cover missing _SE chip variants to fix fpga programming
versal:
- Enable LTO for mini configurations
versal-net:
- Enable LTO for mini configurations
- Fix GIC address to aligned with real silicon
xilinx:
- DTs cleanup and fixups
- Enable HTTP boot
- Add missing spl header to zynqmp.c
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This message isn't an error (there can be a watchdog subnode for example)
but it shouldn't be printed unless this driver is being debugged. Demote
it to a debug print.
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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The pmic_reg_read() function can return errors. Add a check for that.
Fixes: 4e8aa0065d4b ("button: qcom-pmic: introduce Qualcomm PMIC button driver")
Signed-off-by: Dan Carpenter <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
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AM64 ES2.0 bootrom seems to enable WAIT0EDGEDETECTION interrupt.
This causes a lockup at A53 SPL when accessing NAND controller
or ELM registers.
A good option would be to softrest GPMC block at probe
but this cannot be done for AM64 as SOFTRESET bit is marked
as reserved in SYSCONFIG register.
Fix the issue by disabling all IRQs at probe.
Signed-off-by: Roger Quadros <[email protected]>
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Some platforms (such as the Lichee Pi 4A) have their dwmac device
addressable only in high memory space. Storing the node's base address
on 32 bits is not possible in such case.
Use platform's physical address type to store the base address.
Signed-off-by: Nils Le Roux <[email protected]>
Cc: Andre Przywara <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI:
https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19583
- Fix the i.MX8MP SPI compatible string.
- Let the SPL clock code do the configuration on Data Modul i.MX8M Plus
eDM SBC.
- Enable secure boot on the imx93_var_som board.
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ID code is added for zu67dr_SE, zu11eg_SE, zu19eg_SE and zu47dr_SE
variants. SE is the select edition of restricted devices with the
capabilities.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Recent i.MX8MP DTs use new fsl,imx6ul-ecspi compatible string instead
of the fsl,imx51-ecspi compatible string. Add the new compatible string
to fix ECSPI operation on i.MX8MP.
For details, see Linux:
48d74376fb68 ("arm64: dts: imx8mp: update ecspi compatible and clk")
8eb1252bbedf ("spi: imx: remove ERR009165 workaround on i.mx6ul")
Fixes: 451799a6ceac ("arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4")
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Support RPC SPI on R8A779H0 V4M SoC.
Reviewed-by: Paul Barker <[email protected]>
Signed-off-by: Hai Pham <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add pinctrl tables for R8A779H0 V4M SoC.
The current version of these PFC tables is imported and squashed from:
https://lore.kernel.org/linux-renesas-soc/[email protected]/
Signed-off-by: Hai Pham <[email protected]>
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Add PLL7 support to Gen3/Gen4 common clock driver. Add initial PLL7
multiplier and divider values into table in R8A779H0 V4M clock driver.
The PLL7 is new PLL added in R8A779H0 V4M SoC. Only integer multiplication
mode is supported by PLL7. The PLL reference clock are either 16.66 MHz or
20 MHz on R8A779H0 V4M SoC, and the output frequency must be 2000 MHz. The
multiplier values fitting this requirement are calculated to 120 or 100.
Signed-off-by: Marek Vasut <[email protected]>
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Add clock tables for R8A779H0 V4M SoC.
The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be/
The current version still contains PLL7 extras from the
previous version to provide ethernet support in U-Boot.
Signed-off-by: Hai Pham <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Add USB support for phycore-imx8mp
- Fix environment corruption, reset on mx6sabresd
- Print reset cause on imx8
- Extend mkimage to support generating an image for i.MXRT FlexSPI
- Add new apalis and colibri variants
- Add support for phyBOARD-Segin-i.MX93 support
- Fix when FEC is primarily used instead of EQOS on i.MX93.
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Add implementation of sc_pm_reset_reason() call for obtaining
reset reason.
Signed-off-by: Igor Opaniuk <[email protected]>
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Add TJA1120 driver structure and report 1G speed.
Signed-off-by: "Radu Pirea (NXP OSS)" <[email protected]>
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Rename nxp_c45_tja11xx structure to nxp_c45_tja1103. The driver will
support more PHYs and nxp_c45_tja11xx is too generic.
Signed-off-by: "Radu Pirea (NXP OSS)" <[email protected]>
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Read PHY speed from hardware instead of assuming 100Mbps by default.
The TJA1103 works only at 100Mbps, but the driver will support more PHYs.
Signed-off-by: "Radu Pirea (NXP OSS)" <[email protected]>
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Use a local definition for the PHY features. PHY_100BT1_FEATURES are
not defined using the 100BaseT1 bit, so keep this workaround in the driver.
Signed-off-by: "Radu Pirea (NXP OSS)" <[email protected]>
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A number of assorted fixes
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https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add board: rv1126 Sonoff iHost board
- rv1126 ddr4 support;
- Enable BOOTSTD_FULL for RK3399 and RK3588;
- rk3036 spl stack addr fix;
- dts sync from linux v6.8-rc1 for rk356x, rk3588, rv1126;
- Enable eMMC HS200 mode by default for rk3568 and rk3588;
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This error path should return -EINVAL instead of success.
Fixes: e261fbf34785 ("blk: host_dev: Sanity check on the size of host backing file")
Signed-off-by: Dan Carpenter <[email protected]>
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Add a comment to explain the code under is_secure condition of
ti_sci_do_xfer. This will help avoid confusion amongst people who may in
future touch upon this code.
Reviewed-by: Nishanth Menon <[email protected]>
Signed-off-by: Dhruva Gole <[email protected]>
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The ti_sci driver in U-Boot has support for secure_msg as part of it's
do_xfer function. This let's U-boot send secure messages during boot up.
The protocol to send such secure messages is described as part of the
struct ti_sci_secure_msg_hdr. As part of this, there are 2 fields for
checksum and reserved that occupy the first 4 bytes of any secure
message. This is called as the secure_hdr.
As of now, the secure_hdr needs to be 0 init-ed before sending secure
messages. However the existing code was never putting the zero-inited vars
into the secure_buf, leading to possibility of the first 4 bytes of
secure_buf being possibly garbage.
Fix this by initialising the secure_hdr itself to the secure_buf
location, thus when we make secure_hdr members 0, it automatically ensures
the first 4 bytes of secure_buf are 0.
Fixes: 32cd25128bd849 ("firmware: Add basic support for TI System Control Interface (TI SCI)")
Reviewed-by: Nishanth Menon <[email protected]>
Signed-off-by: Dhruva Gole <[email protected]>
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Use ring_idx to pair rings. ring_idx will be same as tx flow_id for all
non-negative flow_ids. For negative flow_ids, ring_idx will be tchan->id
added with bchan_cnt.
Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/dma/ti/k3-udma.c?h=v6.8-rc2#n1686
Signed-off-by: MD Danish Anwar <[email protected]>
Reviewed-by: Ravi Gunasekaran <[email protected]>
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