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Fastboot unregisters the USB gadget from the completion callback of
its final OKAY response. MTU3 QMU can report that request complete
while bytes remain in the endpoint TX FIFO. Disabling the USB function
immediately can therefore disconnect the host before it receives the
response.
Before selecting the high-speed or SuperSpeed disconnect operation, poll
the FIFO state of enabled IN endpoints that have no pending requests.
Bound the wait to 1 ms. If a FIFO does not drain, reset its endpoint,
force the disconnect, and propagate -ETIMEDOUT through the gadget pullup
operation. Endpoints with pending requests are skipped so an ordinary
disconnect does not wait for an active transfer.
Fixes: e09b88cd083d ("usb: add MediaTek USB3 DRD driver")
Signed-off-by: Vitor Sato Eschholz <[email protected]>
Signed-off-by: Carlo Caione <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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A bunch of code calls info->dev, mostly dev_* messages and devm_kzalloc.
The former can be passed a NULL device and _dev_printk handles this just
fine.
The latter ignores the dev argument whenever !CONFIG_IS_ENABLED(DEVRES)
which was true in most cases until we made CONFIG_DEVRES mandatory for
U-Boot proper in commit 217cf656e249 ("dm: core: Default to using DEVRES
outside of xPL"). Failing to set info->dev before it's used by
devm_kzalloc results in crashes, therefore let's set info->dev before it
can be used.
Reported-by: Ben Schneider <[email protected]>
Closes: https://lore.kernel.org/u-boot/IRefanijM8fTzOXeGe-H5hmhRkm7pt4Q83BV6VcWKlWp0s4i8mYcONTQz-IVhvNWlGta4LtnfK7ti6gxlrqq8h8cotgG1S0Fs6_DviAHvyo=@bens.haus/
Fixes: 0871806629b5 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx")
Fixes: 217cf656e249 ("dm: core: Default to using DEVRES outside of xPL")
Signed-off-by: Quentin Schulz <[email protected]>
Tested-by: Ben Schneider <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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https://git.u-boot-project.org/u-boot/custodians/u-boot-mmc
CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-mmc/-/pipelines/781
- Enable MMC CMD23 for multi-block transfers
- Various fixes to mmc core
- Add PF9453 pmic/regulator driver
- Support SCP 4.36 map for renesas-r8a78000
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The hash command currently always uses the software implementation for
the selected algorithm, even when driver-model hash providers are
available.
Add a hash_digest_wd_lookup() helper which probes UCLASS_HASH devices in
order and uses the first provider supporting the requested algorithm.
Continue past unavailable providers and unsupported operations, but
propagate a hard digest failure once a provider accepts the operation.
Remember probe failures so they are not silently hidden by software
fallback when no later provider succeeds.
Use the helper from the hash command and retain its software fallback
when no usable provider is present. Add sandbox tests covering provider
fallback and hard-error propagation.
Signed-off-by: James Hilliard <[email protected]>
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Daniel Golle <[email protected]> says:
The Haoyu HYM8563, found for example on the Radxa ROCK 5B, is a clone of
the NXP PCF8563 with an identical timekeeping register layout, but the
pcf8563 driver does not match its compatible used in upstream DT.
Boards fitted with it end up without DM_RTC and, as a consequence,
without usable EFI GetTime and SetTime runtime services. On top of
that, when the chip reports that the time may be unreliable after a
supply voltage drop, the driver returns a bare -1, which callers
interpret as -EPERM rather than as invalid data.
This series makes the existing driver serve the HYM8563 and lets callers
distinguish an unreliable time from a permission problem.
The driver gains the additional compatible string and returns -EINVAL
when the voltage-low flag is set, matching the rv3032 driver and the
behaviour of the Linux driver for the same chips.
Link: https://lore.kernel.org/r/[email protected]
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Return a proper error code instead of a bare -1 (-EPERM) when VL
indicates the time is not reliable, matching rv3032 and the Linux
driver behaviour.
Signed-off-by: Daniel Golle <[email protected]>
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The HYM8563 is a PCF8563 clone with an identical timekeeping register
layout and is found e.g. on the Radxa ROCK 5B. Match its compatible so
DM_RTC (and with it the EFI GetTime/SetTime runtime services) can use
the existing driver with upstream DT.
Signed-off-by: Daniel Golle <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Parent lookup now probes the exact missing provider on demand, making the
eager probing of every parent provider after bind redundant. The common
bind callback also occupies a driver callback that a provider may need
for unrelated setup.
Remove the common bind callback and its use from all MediaTek parent
providers. Providers are now registered only when first needed or when
normal driver-model probing reaches them.
Signed-off-by: Carlo Caione <[email protected]>
Link: https://patch.msgid.link/20260724-ccaione-upstream-fix-clk-probe-v2-2-ebcef2e94e9d@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MediaTek clock trees can reference parents provided by a different clock
controller. The provider registry is populated when each controller
probes, so an early consumer can request a parent before its provider has
been registered.
When lookup misses, find the MediaTek clock device whose operations and
clock-tree type match the requested provider, then probe that device.
This removes the probe-order dependency without probing unrelated clock
controllers or treating a driver's bind callback as a type marker.
Co-developed-by: David Lechner <[email protected]>
Signed-off-by: Carlo Caione <[email protected]>
Link: https://patch.msgid.link/20260724-ccaione-upstream-fix-clk-probe-v2-1-ebcef2e94e9d@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Add display related clock drivers, needed for HDMI support.
Signed-off-by: Chris-QJ Chen <[email protected]>
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-mt8188-add-clk-add-display-related-clocks-v2-1-0aaf7accaeb0@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Every clock driver now stores its struct mtk_clk_tree in the compatible
data. Rename mtk_common_clk_init() to mtk_clk_probe() and make if fetch
the tree from dev_get_driver_data() instead of taking it as an argument,
so it matches the driver .probe prototype and can be used directly as
the probe callback.
Drop all the per-SoC probe wrappers that only forwarded the driver data
to mtk_clk_probe(), and point the corresponding drivers at
mtk_clk_probe() directly. The few controllers that still need a
dedicated probe for SoC specific register tweaks (some apmixedsys and
topckgen instances) keep it, but now call the single-argument
mtk_clk_probe().
This touches every MediaTek clock driver at once to keep the tree building
across the whole series.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-32-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]> (renamed mtk_common_clk_init() to mtk_clk_probe())
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Now that every MediaTek SoC describes its clock gates through struct
mtk_clk_tree and handles them with the generic topckgen ops, nothing uses
the dedicated clock gate code path anymore.
Remove struct mtk_cg_priv, the mtk_clk_gate_ops (of_xlate/enable/disable/
get_rate/dump) and mtk_common_clk_gate_init() from clk-mtk. Clock gate
controllers are now just regular mtk_clk_tree providers.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-31-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8189 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys, topckgen and vlpckgen controllers keep their own
U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind()
callback, but they now get their tree from the compatible data, like the
clock gate controllers.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-30-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT8189 already shares a single U_BOOT_DRIVER across all its clock gate
controllers, passing the per-controller gate table through the driver data
via a dedicated struct mt8189_gate_clk_data.
Now that struct mtk_clk_tree can describe the gates directly, drop that
bespoke helper: give each controller its own struct mtk_clk_tree
(.gates/.num_gates/.gates_offs) and use the generic mtk_clk_topckgen_ops.
The gate offset, previously computed at runtime from the first gate ID, is
now encoded statically in each tree.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-29-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]> (dropped _gates_offs arg from GATE_CLK_TREE)
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8512 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-28-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT8512 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for the topckgen and infracfg clock gate controllers, despite both
sharing the same implementation.
Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. Both controllers share the same DM flags and (absent)
bind() callback and are merged into a single U_BOOT_DRIVER.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-27-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8365 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-26-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Describe the infracfg gates directly in a struct mtk_clk_tree, reference the
tree from the driver data and use the generic mtk_clk_topckgen_ops instead
of the dedicated clock gate ops.
This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-25-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8195 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-24-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Describe the infracfg_ao gates directly in a struct mtk_clk_tree, reference
the tree from the driver data and use the generic mtk_clk_topckgen_ops
instead of the dedicated clock gate ops.
This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-23-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8518 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-22-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Describe the topckgen clock gates directly in a struct mtk_clk_tree,
reference the tree from the driver data and use the generic
mtk_clk_topckgen_ops instead of the dedicated clock gate ops.
This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-21-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8516 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-20-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Describe the topckgen clock gates directly in a struct mtk_clk_tree,
reference the tree from the driver data and use the generic
mtk_clk_topckgen_ops instead of the dedicated clock gate ops.
This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-19-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8183 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-18-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Describe the infracfg gates directly in a struct mtk_clk_tree, reference the
tree from the driver data and use the generic mtk_clk_topckgen_ops instead
of the dedicated clock gate ops.
This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-17-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for the MT7988 clock drivers, instead of a
dedicated probe per controller.
The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER
since they rely on dedicated ops and on the parent bind() callback, but they
now get their tree from the compatible data. The topckgen probe still
performs its SoC specific register tweaks.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-16-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT7988 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.
Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. The two sgmiisys controllers, which share the same DM
flags and (absent) bind() callback, are merged into a single U_BOOT_DRIVER;
ethdma and ethwarp keep their own drivers since they bind reset controllers
at different offsets.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-15-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for the MT7987 clock drivers, instead of a
dedicated probe per controller.
The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER
since they rely on dedicated ops and on the parent bind() callback, but they
now get their tree from the compatible data. The topckgen probe still
performs its SoC specific register tweaks.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-14-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Describe the ethsys gates directly in a struct mtk_clk_tree, reference the
tree from the driver data and use the generic mtk_clk_topckgen_ops instead
of the dedicated clock gate ops.
This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-13-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for the MT7986 clock drivers, instead of a
dedicated probe per controller.
The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER
since they rely on dedicated ops and on the parent bind() callback, but they
now get their tree from the compatible data. The topckgen probe still
performs its SoC specific register tweaks.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-12-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Describe the ethsys gates directly in a struct mtk_clk_tree, reference the
tree from the driver data and use the generic mtk_clk_topckgen_ops instead
of the dedicated clock gate ops.
This stops using mtk_common_clk_gate_init() and struct mtk_cg_priv, which
are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-11-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for the MT7981 clock drivers, instead of a
dedicated probe per controller.
The fixed-pll, topckgen and infracfg controllers keep their own U_BOOT_DRIVER
since they rely on dedicated ops and on the parent bind() callback, but they
now get their tree from the compatible data. The topckgen probe still
performs its SoC specific register tweaks.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-10-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT7981 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.
Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. The two sgmiisys controllers, which share the same DM
flags and (absent) bind() callback, are merged into a single U_BOOT_DRIVER;
ethsys keeps its own driver as it binds a reset controller.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-9-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT7629 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data. The apmixedsys probe still performs
its SoC specific register tweaks.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-8-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT7629 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.
Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. Controllers that share the same DM flags and bind()
callback are then merged: infracfg and pericfg into one pre-relocation
driver, sgmiisys and ssusbsys into another. ethsys keeps its own driver as
it binds a reset controller.
While at it, this fixes a latent off-by-one in the infracfg gate lookup: its
clock IDs start at CLK_INFRA_DBGCLK_PD (1), but the old code passed a gate
offset of 0, so requesting e.g. CLK_INFRA_TRNG_PD resolved to the wrong
gate. The offset is now taken from the first gate ID, like the other
controllers.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-7-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT7623 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data. The apmixedsys probe still performs
its SoC specific register tweaks.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-6-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT7623 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.
Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. The ethsys and hifsys controllers, which share the
same reset-binding bind() callback, are merged into a single U_BOOT_DRIVER;
infracfg keeps its own driver since it is pre-relocation and does not bind a
reset controller.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-5-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT7622 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data. The apmixedsys probe still performs
its SoC specific register tweaks. The infracfg and pericfg controllers share
the same ops, flags and (absent) bind() callback and are merged into a
single driver.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-4-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT7622 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.
Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. Clock gate controllers that share the same DM flags
and bind() callback can then share a single U_BOOT_DRIVER: the pciesys and
ethsys controllers, which both bind a reset controller at the same offset,
are merged into one driver, and the sgmiisys and ssusbsys controllers into
another.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-3-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]> (changed to CONFIG_IS_ENABLED)
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Pass each controller's struct mtk_clk_tree through the driver data and use
a single shared probe function for all the MT8188 clock drivers, instead of
a dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
share the generic probe and get their tree from the compatible data, just
like the clock gate controllers.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-2-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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MT8188 currently declares a separate U_BOOT_DRIVER, probe() function and
compatible table for each clock gate controller, despite all of them
sharing the same implementation.
Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. All the clock gate controllers can then share a
single U_BOOT_DRIVER, eliminating the duplicated code.
This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.
No functional change intended.
Suggested-by: David Lechner <[email protected]>
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-1-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
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Add regulator support for NXP PMIC pf9453 for imx91 qsb.
Reviewed-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Joy Zou <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Rebased [1] on main and LDO SNVS access / checkpatch fixed. See also [2]
[1] https://patchwork.ozlabs.org/project/uboot/patch/[email protected]/
[2] https://lists.u-boot-project.org/pipermail/u-boot/2026-July/625613.html
Signed-off-by: Krzysztof Drobiński <[email protected]>
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Support NXP PMIC pf9453.
Reviewed-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Joy Zou <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Rebased [1] on main and checkpatch fixed. See also [2]
[1] https://patchwork.ozlabs.org/project/uboot/patch/[email protected]/
[2] https://lists.u-boot-project.org/pipermail/u-boot/2026-July/625613.html
Signed-off-by: Krzysztof Drobiński <[email protected]>
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The SCMI IDs did not change between SDK SCP 4.32 and SDK SCP 4.36.
Add SDK SCP 4.36 as supported version and reuse SDK SCP 4.32 remap
table.
Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Enable the support for the CMD23 (SET_BLOCK_COUNT) command to
manage multi-block read/write operations. This allows the MMC
core to use CMD23 in preference to the legacy CMD18/CMD25 plus
CMD12 sequence, reducing command overhead and improving I/O
performance on multi-block transfers.
Signed-off-by: Eric Chung <[email protected]>
Signed-off-by: Tanmay Kathpalia <[email protected]>
[ Drop MMC_CAP_CMD32 from mvebu_mmc.h ]
Signed-off-by: Peng Fan <[email protected]>
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Commit 906ee6785b1c ("mmc: sd: Handle UHS-I voltage signaling without
power cycle") added detection of cards already operating at 1.8V
signaling via mmc_sd_card_using_v18(). This correctly handles the
warm-reboot scenario in mmc_startup().
However, mmc_deinit() strips ALL UHS capabilities from the card caps
and calls sd_select_mode_and_width() to downgrade the card before
kernel handoff. For a card that has switched to 1.8V, uhs_en is
already true (via OCR_S18R in mmc->ocr), so sd_select_mode_and_width()
attempts UHS mode selection -- but no UHS modes remain in the filtered
caps. The non-UHS fallbacks (SD_HS, MMC_LEGACY) are 3.3V speed modes
which, when selected while signaling at 1.8V, leave the card in an
inconsistent state it cannot recover from without a power cycle.
Per SD Physical Layer Specification: "Once the card enters 1.8V
signaling mode, the card cannot be switched to 3.3V signaling without
power cycle. If the card receives CMD0, card returns to Idle state but
still works with SDR12 timing."
Fix by using a UHS capability mask that preserves UHS_SDR12 when the
card is operating at 1.8V. SDR12 is the minimum valid UHS-I mode and
is always available at 1.8V signaling per the SD specification, so the
card is left in a consistent (1.8V) state at a low, safe speed.
Fixes: 906ee6785b1c ("mmc: sd: Handle UHS-I voltage signaling without power cycle")
Reviewed-by: Tanmay Kathpalia <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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mmc_bwrite() uses mmc->cfg->b_max directly to limit per-transfer block
count. The read path (mmc_bread()) correctly calls mmc_get_b_max()
which dispatches to the host driver get_b_max() callback. This callback
allows host drivers to enforce DMA boundary constraints based on the
buffer address.
Fix mmc_bwrite() to use mmc_get_b_max() to match the read path. This
requires removing the static qualifier from the non-DM mmc_get_b_max()
and adding its declaration to mmc_private.h.
Reviewed-by: Tanmay Kathpalia <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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sdhci_init() allocates a 512KB aligned bounce buffer for controllers
with SDHCI_QUIRK_32BIT_DMA_ADDR. In the non-DM code path, sdhci_init()
is registered as ops->init and called on every mmc_init(). Each call
allocates a new buffer without checking or freeing the previous one,
leaking 512KB per re-initialization.
Fix by guarding the allocation with !host->align_buffer so it only
allocates on the first call.
Reviewed-by: Tanmay Kathpalia <[email protected]>
Signed-off-by: Tanmay Kathpalia <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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In rpmb_route_frames(), the RPMB_REQ_READ_DATA case checks
"req_cnt != 1 || !req_cnt" which is tautological -- !req_cnt (req_cnt
== 0) is always a subset of req_cnt != 1. The second operand is dead
code.
Based on the pattern of all other cases in the switch (RPMB_REQ_KEY,
RPMB_REQ_WRITE_DATA, RPMB_REQ_WCOUNTER) which validate rsp_cnt, this
was meant to be "req_cnt != 1 || !rsp_cnt". Without this fix, a caller
could pass rsp_cnt=0 for a read request without validation.
Signed-off-by: Peng Fan <[email protected]>
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