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Fix confusing use of indentation.
Signed-off-by: Ondrej Jirman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The intermediate value could overflow for large periods and levels.
Signed-off-by: Matthias Schiffer <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The driver is for panels based on the Himax HX8394 controller, such as the
HannStar HSD060BHW4 720x1440 TFT LCD panel that uses a MIPI-DSI interface.
This panel is used in Pinephone Pro.
Signed-off-by: Ondrej Jirman <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
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Some callers expect to call this with NULL font name to select the
default font (eg. boot/scene.c). Without handling the NULL condition
U-Boot crashes instead of displaying a bootflow GUI menu.
Signed-off-by: Ondrej Jirman <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
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- Add xtxtech spi-nor chip parts (Bruce Suen)
- Add bcm63xx-hsspi driver fixes (William Zhang)
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- mvebu: Thecus: Misc enhancement and cleanup (Tony)
- mvebu: Add AC5X Allied Telesis x240 board support incl NAND
controller enhancements for this SoC (Chris)
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20230713
-------------------
Merge for 2023.10.
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16888
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There are some newer clocks added to the kernel recently,
so to fix prepare for resycing the device trees, update
the clock list. Since there are some minor changes to
the USB clocks, update which USB clocks are enabled
to match with the upstream kernel as well.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Tested-by: Tim Harvey <[email protected]> #imx8mp-venice-gw74xx
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This commit adds driver for iMX93 ADC.
The driver is implemented using driver model and provides
ADC uclass's methods for ADC single channel operations:
- adc_start_channel()
- adc_channel_data()
- adc_stop()
ADC features:
- channels: 4
- resolution: 12-bit
Signed-off-by: Luca Ellero <[email protected]>
Reviewed-by: Haibo Chen <[email protected]>
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On the imx8ulp A1 SoC, the ELE RNG needs to be manually started.
Signed-off-by: Clement Faure <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Extend the RX timeout value to 10s, because when authentication is failed
the ELE needs long time (>2s for 28M image) to return the result. Print
rx wait info per 1s.
Also correct TX and RX status registers in debug.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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According to SRM, the Sentinel MU has 8 TR and 4 RR registers. All
of them are used for ELE message. So update TR count to 8 and fix a
typo in receive msg
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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- Add crc computation.
- Add ele_generate_dek_blob API for encrypted boot support.
Signed-off-by: Clement Faure <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add two ELE API: ele_return_lifecycle_update and ele_write_secure_fuse
Add two cmd: ahab_return_lifecycle and ahab_sec_fuse_prog
Signed-off-by: Peng Fan <[email protected]>
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Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave
code including comment, folder and API name to ELE to align.
Signed-off-by: Peng Fan <[email protected]>
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Upgrade SCFW API to 1.16
Add more APIs:
sc_misc_get_button_status
sc_pm_reboot
sc_seco_v2x_build_info
Signed-off-by: Peng Fan <[email protected]>
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The return value is int type, not sc_err_t(u8), correct the usage.
Signed-off-by: Peng Fan <[email protected]>
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Add support for Winbond 256M-bit flash w25q256jwm.
Performed basic erase/write/readback operations on
ZynqMP zc1751+dc1 board.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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If cs gpio is requested with ACTIVE_HIGH flag, it will
be pulled low(i.e. active). This is not what we expected.
Signed-off-by: Jim Liu <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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add following XTX part numbers to the list:
xt25f08: 3V QSPI, 8Mbit
xt25f16: 3V QSPI, 16Mbit
xt25f32: 3V QSPI, 32Mbit
xt25f64: 3V QSPI, 64Mbit
xt25f128: 3V QSPI, 128Mbit
xt25f256: 3V QSPI, 256Mbit
xt25q08: 1.8V QSPI, 8Mbit
xt25q16: 1.8V QSPI, 16Mbit
xt25q32: 1.8V QSPI, 32Mbit
xt25q64: 1.8V QSPI, 64Mbit
xt25q128: 1.8V QSPI, 128Mbit
xt25q256: 1.8V QSPI, 256Mbit
xt25q512: 1.8V QSPI, 512Mbit
xt25q01g: 1.8V QSPI, 1Gbit
xt25w512: wide voltage, QSPI, 512Mbit
xt25w01g: wide voltage, QSPI, 1Gbit
remove xt25f128b and add xt25f128,because xt25f128b andxt25f128f
share same jdec id,we use xt25f128 instead.
Signed-off-by: Bruce Suen <[email protected]>
[jagan: re-edited the entire patch]
Signed-off-by: Jagan Teki <[email protected]>
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XTX changed full company name from "XTX Technology (Shenzhen) Limited
to "XTX Technology Limited" since 2020,So remove "(Shenzhen)".
Signed-off-by: Bruce Suen <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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According to Documentation/devicetree/bindings/spi/spi-gpio.yaml
from Linux, the recommended spio-gpio properties are:
sck-gpios, miso-gpios and mosi-gpios.
gpio-sck, gpio-mosi and gpio-miso are considered deprecated.
Currently, U-Boot only supports the deprecated properties.
Allow the soft_spi driver to support both the new and old properties.
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Current code expects that SPI_TX_BYTE is single bit mode
but it is wrong. It indicates byte program mode,
not single bit mode.
If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set,
the default transfer bus width is single bit.
Signed-off-by: Masahisa Kojima <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an
updated SPI controller that add the capability to allow the driver to
control chip select explicitly. Driver can control and keep cs low
between the transfers natively. Hence the dummy cs workaround or prepend
mode found in the bcm63xx-hsspi driver are no longer needed and this new
driver is much cleaner.
Port from linux patch:
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: William Zhang <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Due to the controller limitation to keep the chip select low during the
bus idle time between the transfer, a dummy cs workaround was used when
this driver was first upstreamed to the u-boot based on linux kernel
driver. It basically picks the dummy cs as !actual_cs so typically dummy
cs is 1 when most of the case only cs 0 is used in the board design.
Then invert the polarity of both cs and tell the controller to start the
transfers using dummy cs. Assuming both cs are active low before the
inversion, effectively this keeps dummy cs high and actual cs low during
the transfer and workaround the issue.
This workaround requires that dummy cs 1 pin to is set to SPI chip
selection function in the pinmux when the transfer clock is above 25MHz.
The old chips likely have default pinmux set to chip select on the dummy
cs pin so it works but this is not case for the new Broadband BCA chips
and this workaround stop working. This is specifically an issue to
support SPI NAND and SPI NOR flash because these flash devices can
typically run at or above 100MHz.
This patch utilizes the prepend feature of the controller to combine the
multiple transfers in the same message to a single transfer when
possible. This way there is no need to keep clock low between transfers
and solve the issue without any pinmux requirement.
Multiple transfers within a SPI message may be combined into one
transfer if the following are all true:
* One or more half duplex write transfer in single bit mode
* Optional full duplex read/write at the end
* No delay and cs_change between transfers
Most of the SPI device meets this requirements such as SPI NOR, SPI NAND
flash, Broadcom SPI voice card and etc. So this change switches to the
prepend mode as the default mode. For any SPI message that does not meet
the above requirement, we switch to original dummy cs mode but limit the
clock rate to the safe 25MHz.
Port from linux patch:
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: William Zhang <[email protected]>
Acked-by: Jagan Teki <[email protected]>
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New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on
dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support
this new binding.
Port from linux patch:
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: William Zhang <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Currently the driver always sets the controller to dual data bit mode
for both tx and rx data in the profile mode control register even for
single data bit transfer. Luckily the opcode is set correctly according
to SPI transfer data bit width so it does not actually cause issues.
This change fixes the problem by setting tx and rx data bit mode field
correctly according to the actual SPI transfer tx and rx data bit width.
Fixes: 29cc4368ad4b ("dm: spi: add BCM63xx HSSPI driver")
Port from linux patch:
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: William Zhang <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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ARCH_BCMBCA was introduced to cover individual Broadcom broadband SoC
for common features and IP blocks. Use this config instead of each chip
config as the Kconfig dependency for Broadcom HSSPI driver.
Signed-off-by: William Zhang <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add support for an optional external chip-select gpio.
Signed-off-by: Lukas Funke <[email protected]>
Signed-off-by: Stefan Herbrechtsmeier <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Remove the platform data header because its content is only used by the
driver.
Signed-off-by: Stefan Herbrechtsmeier <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Rename the flush function into pl022_spi_flush to avoid conflicting
types with previous declaration of the function in stdio.h header.
Signed-off-by: Stefan Herbrechtsmeier <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Align the compatible property with the kernel device tree binding [1]
by removing the '-spi' suffix.
[1] https://www.kernel.org/doc/Documentation/devicetree/bindings/spi/spi-pl022.yaml
Signed-off-by: Lukas Funke <[email protected]>
Signed-off-by: Stefan Herbrechtsmeier <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The CN9130 SoC (an ARMADA 8K type) has both a NAND Flash Controller and
a generic local bus controller (Device Bus Controller) that share common
pins.
With a board design that incorporates both a NAND flash and uses
the Device Bus (in our case for an SRAM) accessing the Device Bus device
fails unless the NfArbiterEn bit is set. Setting the bit enables
arbitration between the Device Bus and the NAND flash.
Since there is no obvious downside in enabling this for designs that
don't require arbitration, we always enable it.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The NAND flash controller (NFC) on the AC5/AC5X SoC is the same as
the NFC used on other Marvell SoCs. It does have the additional
restriction of only supporting SDR timing modes up to 3.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint timer driver to
support ACLINT mtimer device, using a per-driver data field to hold
the mtimer offset to the base address encoded in the mtimer node.
[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of
DDR capacity includes 2G/4G/8G, a DT can not support multiple
capacities, so the capacity size information is recorded to EEPROM, when
DDR initialization required capacity size information is read from
EEPROM.
If there is no information in EEPROM, it is initialized with the default
size defined in DT.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have
verified the driver on StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Before this change the FR_TXFF (Transmit FIFO full) bit (5 in
HW_UARTDBG_FR) has been used to assess if there is still data pending
to be sent via UART.
This approach is problematic, as it may happen that serial is in the
middle of transmission (so the TX FIFO is NOT full anymore) and this
test returns true infinitely. As a result, for example in _serial_flush()
DM serial function we are locked in endless while().
The fix here is to test explicitly if the TX FIFO is empty.
Signed-off-by: Lukasz Majewski <[email protected]>
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This commit prepares the pl01x serial driver to be used with
SPL_OF_PLATDATA enabled.
Signed-off-by: Lukasz Majewski <[email protected]>
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Before this change, building this driver for SPL with enabled SPL_DM_SERIAL
was problematic, as '-Wunused-const-variable=' warning was visible.
Now, the code is only considered when u-boot proper is build.
Signed-off-by: Lukasz Majewski <[email protected]>
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In the imx8m power domain kernel driver, there is an extra udelay(5)
prior to requesting the domain to power up:
https://github.com/torvalds/linux/blob/v6.3/drivers/soc/imx/gpcv2.c#L347-L375
Haven't observed any issues due to the lack of this delay in U-Boot yet,
but better to align it with the kernel driver implementation.
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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DM_GPIO depends on GPIO to be enabled but select will cause that DM_GPIO is
selected without GPIO which ends up in compilation error:
undefined reference to `dm_gpio_set_value'
undefined reference to `dm_gpio_get_value'
undefined reference to `dm_gpio_free'
undefined reference to `gpio_request_by_name'
Signed-off-by: Michal Simek <[email protected]>
[trini: Fix configs which had relied on these select's]
Signed-off-by: Tom Rini <[email protected]>
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into next
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There is a problem that the rates of PLL0 and PLL1 are set incorrectly
because the postdiv1_mask value is incorrectly entered when setting
the pll clk reg. Modify postdiv1's mask value to be put correctly.
Signed-off-by: Hoegeun Kwon <[email protected]>
Reviewed-by: Minkyu Kang <[email protected]>
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If we're building non FU540/FU740 SoC drivers, then the sifive-prci.o
is not needed. Only build this when CONFIG_CLK_SIFIVE_PRCI is selected.
Signed-off-by: Ben Dooks <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Prepare v2023.07-rc6
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The regulator core can return different codes which are not considered
a real error for this function.
Return success in such cases.
Signed-off-by: Eugen Hristev <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Simplify the subsystem by renaming `dev_pdata` to just `plat`.
No functional change, just trivial renaming.
Suggested-by: Simon Glass <[email protected]>
Signed-off-by: Eugen Hristev <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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