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2025-12-30video: display: refactor display_read_timing to avoid code duplicationJulien Stephan
Commit 2dcf143398ad ("dm: video: Repurpose the 'displayport' uclass to 'display'") left the display_read_edid() function unused by mistake. Mark the function as static and reuse it within display_read_timing() to avoid code duplication. Signed-off-by: Julien Stephan <[email protected]>
2025-12-29clk: renesas: Do not disable realtime modules on R8A77995 D3Niklas Söderlund
Later versions of the datasheet makes it clear D3 do not have any realtime module stop control registers (RMSTPCRx). Remove the manipulation of them from the module clock table to match this. Suggested-by: Marek Vasut <[email protected]> Signed-off-by: Niklas Söderlund <[email protected]>
2025-12-29clk: renesas: Do not enable MSTP4 extra modules on R8A77995 D3Niklas Söderlund
Since commit a2bd99549c61 ("clk: renesas: Tear clock controller down last before booting OS") enabling the module gated by bit 8 in MSTP4 prevents Linux from booting. The bits 8 and 7 of MSTP4 where only documented in early versions of the datasheet and have since been removed. To allow Linux to boot update the MSTP4 enable value to reflect the hardware default, 0x80. Suggested-by: Marek Vasut <[email protected]> Signed-off-by: Niklas Söderlund <[email protected]>
2025-12-29Merge tag 'u-boot-imx-next-20251229' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/28866 - Swicth imx8ulp-evk to standard boot and OF_UPSTREAM. - Cleanup of the IPUv3 video driver. - Add support for the NXP FRDM-IMX91 board. - Make flash.bin target available on i.MX9. - Fix mxsfb pixel clock polarity.
2025-12-29video: imx: ipuv3: refactor to use dm-managed stateBrian Ruley
Get rid of most globals that are spread around between TU's and place them in their own structs managed by dm. Device state is now owned by each driver instance. This design mirrors the Linux IPUv3 driver architecture. This work is done in preparation to migrate the driver to the clock framework. While not the primary intent, this change also enables multiple IPU instances to exist contemporarily. Signed-off-by: Brian Ruley <[email protected]>
2025-12-29video: imx: ipuv3: use CONFIG_IS_ENABLEDBrian Ruley
Bring driver up-to-date with U-Boot conventions, but also takes into account SPL and TPL, let compiler optimize while keeping code more readable. Signed-off-by: Brian Ruley <[email protected]>
2025-12-29video: imx: ipuv3: add names to clk function identifiersBrian Ruley
The API should provide clear distinction in the order of parameters. Signed-off-by: Brian Ruley <[email protected]>
2025-12-29video: imx: ipuv3: fix camel casesBrian Ruley
U-Boot style specifies to use snake case and checkpatch nudge to check them every time. Signed-off-by: Brian Ruley <[email protected]>
2025-12-29video: imx: ipuv3: prefer kernel typesBrian Ruley
Conform with U-Boot guidelines and pass checkpatch checks for upcoming changes. Signed-off-by: Brian Ruley <[email protected]>
2025-12-29video: imx: ipuv3: apply clang-formatBrian Ruley
Bring the code into compliance with U-Boot's coding style guidelines for upcoming changes. Sort includes to tidy things up and apply { RemoveBracesLLVM: true } to remove unnecessary blocks. Signed-off-by: Brian Ruley <[email protected]>
2025-12-29video: imx: ipuv3: remove undefined function declarationsBrian Ruley
These functions don't seem to be defined nor called anywhere so remove them. Signed-off-by: Brian Ruley <[email protected]>
2025-12-29video: mxsfb: fix pixel clock polaritySam Meredith
DISPLAY_FLAGS_PIXDATA_NEGEDGE means the controller drives the data on pixel clocks falling edge. That is DOTCLK_POL=0 (default) not 1. The mxsfb-drm driver in the Linux kernel has made the same change and it remains to this day: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?h=v6.19-rc2&id=53990e416bb7adaa59d045f325a47f31a11b75ee I found this was required on an IMX8X SoM. Without the patch a splash screen displays with aliasing-like jagged edges. Signed-off-by: Sam Meredith <[email protected]> [fabio: Put more information into the commit log] Signed-off-by: Fabio Estevam <[email protected]>
2025-12-27i2c: Avoid calling dev_read_*() if CONFIG_OF_PLATDATA=yMarek Vasut
If CONFIG_OF_PLATDATA=y , then the udevice has no valid OF node associated with it and ofnode_valid(node) evaluates to 0. The dev_read_u32_default() call ultimately reaches ofnode_read_u32_index() which invokes fdt_getprop() and passes result of ofnode_to_offset(node) as an offset parameter into it. The ofnode_to_offset(node) returns -1 for invalid node, which leads to an fdt_getprop(..., -1, ...) invocation, which will crash sandbox with SIGSEGV because libfdt can not handle negative node offsets without full tree check, which U-Boot inhibits to keep size lower. Since i2c_child_post_bind() already calls dev_has_ofnode(dev), reuse the same call and assign i2c->speed_hz = I2C_SPEED_STANDARD_RATE in case the device has no valid node associated with it, and do not call any of the dev_read_*() functions for devices without valid nodes. Signed-off-by: Marek Vasut <[email protected]>
2025-12-27i2c: Inline i2c_chip_of_to_plat() into i2c_child_post_bind()Marek Vasut
The i2c_chip_of_to_plat() is called only from i2c_child_post_bind(), inline i2c_chip_of_to_plat() into i2c_child_post_bind(). Drop the if CONFIG_IS_ENABLED(OF_REAL) and depend on if (!dev_has_ofnode(dev)) which does check CONFIG_IS_ENABLED(OF_REAL) internally too. Signed-off-by: Marek Vasut <[email protected]>
2025-12-27gpio: sandbox: Avoid calling dev_read_*() if CONFIG_OF_PLATDATA=yMarek Vasut
If CONFIG_OF_PLATDATA=y , then the udevice has no valid OF node associated with it and ofnode_valid(node) evaluates to 0. The dev_read_u32_default() call ultimately reaches ofnode_read_u32_index() which invokes fdt_getprop() and passes result of ofnode_to_offset(node) as an offset parameter into it. The ofnode_to_offset(node) returns -1 for invalid node, which leads to an fdt_getprop(..., -1, ...) invocation, which will crash sandbox with SIGSEGV because libfdt can not handle negative node offsets without full tree check, which U-Boot inhibits to keep size lower. Since gpio_sandbox_probe() already calls dev_has_ofnode(dev) and assigns uc_priv->gpio_count to CONFIG_SANDBOX_GPIO_COUNT accordingly, add matching dev_has_ofnode(dev) check into sandbox_gpio_of_to_plat() and do not call any of the dev_read_*() functions for devices without valid nodes there either. Signed-off-by: Marek Vasut <[email protected]>
2025-12-27clk: fixed_rate: Avoid calling dev_read_*() if CONFIG_OF_PLATDATA=yMarek Vasut
If CONFIG_OF_PLATDATA=y , then the udevice has no valid OF node associated with it and ofnode_valid(node) evaluates to 0. The dev_read_u32_default() call ultimately reaches ofnode_read_u32_index() which invokes fdt_getprop() and passes result of ofnode_to_offset(node) as an offset parameter into it. The ofnode_to_offset(node) returns -1 for invalid node, which leads to an fdt_getprop(..., -1, ...) invocation, which will crash sandbox with SIGSEGV because libfdt can not handle negative node offsets without full tree check, which U-Boot inhibits to keep size lower. Add dev_has_ofnode(dev) check and do not assign clock rate in case the device has no valid node associated with it, and do not call any of the dev_read_*() functions for devices without valid nodes. Signed-off-by: Marek Vasut <[email protected]>
2025-12-24power: regulator: Fix dependency of SPL_DM_REGULATOR_GPIOPeng Fan
gpio-regulator uses dm gpio API, so it depends on SPL_DM_GPIO, not SPL_GPIO. Reported-by: Tom Rini <[email protected]> Reviewed-by: Tom Rini <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2025-12-24power: regulator: remove SPL_REGULATOR_PWM due to unmeetable SPL_DM_PWM ↵Quentin Schulz
dependency SPL_DM_PWM option simply doesn't exist. Moreover, drivers/pwm is only included by drivers/Makefile for non-xPL stages so making SPL_REGULATOR_PWM properly build for SPL/xPL is more involved than just adding an SPL_DM_PWM option. Reading the original commit (ddc824f89aa8 ("power: regulator: Allow PWM regulator to be omitted from SPL."), the intent seemingly wasn't to allow building support in XPL but rather to allow removing it which is done by using $(PHASE_) ($(SPL_) at that time) in the Makefile. If anyone needs that, let them figure out what they need to do without misleading potential users of this symbol by simply removing it. Fixes: 2a846e04c622 ("power: regulator: Correct dependencies on SPL_REGULATOR_PWM") Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Anshul Dalal <[email protected]> Reviewed-by: Kory Maincent <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2025-12-24power: regulator: fix dependency for REGULATOR_PWMQuentin Schulz
The PWM regulator driver is a uclass driver, thus requiring DM_PWM to be enabled to be actually usable (and with the appropriate PWM controller driver enabled as well, but that we cannot enforce easily), so let's add this missing dependency. Fixes: 1a01695615f9 ("power: regulator: add pwm regulator") Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Udit Kumar <[email protected]> Reviewed-by: Anshul Dalal <[email protected]> Reviewed-by: Kory Maincent <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2025-12-23net: ravb: Configure CXR31 and CXR35 on rzg2lMathieu Othacehe
As in Linux with d78c0ced60 ("net: ravb: Make write access to CXR35 first before accessing other EMAC register"), configure CXR31 and CXR35 correctly on rzg2. MII mode does not work correctly unless those registers are properly configured. Signed-off-by: Mathieu Othacehe <[email protected]> Reviewed-by: Marek Vasut <[email protected]>
2025-12-22Merge tag 'v2026.01-rc5' into nextTom Rini
Prepare v2026.01-rc5
2025-12-22drivers: scsi: fix double decrement of block count in 64-bit LBA pathBalaji Selvanathan
The scsi_read function incorrectly decrements the block count twice when handling large disks that trigger the CONFIG_SYS_64BIT_LBA code path (reads beyond block 268,435,455). The variable 'blks' was being decremented both inside the 64-bit LBA block and after the successful scsi_exec() call, causing incorrect block count tracking and data abort errors on large capacity disks. Signed-off-by: Balaji Selvanathan <[email protected]> Tested-by: Tony Dinh <[email protected]>
2025-12-19Merge tag 'xilinx-for-v2026.04-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next AMD/Xilinx/FPGA changes for v2026.04-rc1 xilinx: - Sync ESRT with detected GUID - DT cleanups - Add logic for FRU information multiple times - Enable more drivers pca9541, usb5744 - Enable more commands - Cleanup firmware DT bindings firmware: - Add enhancement SMC format support clk/versal: - Various cleanups - Add support for Versal Gen 2 i2c: - cdns: Add timeout for RXDV status bit polling spi: - cadence: Remove cdns,is-dma DT property - cadence: Remove duplicated return - cadence_versal: Update flash reset delay memtop: - Update max memory reserved spaces to 64 Versal Gen 2: - Aligned addresses with default memory map - Add support for reading multiboot value MB-V: - Make SPL smaller - Add support for SPI - Move SPL to run out of BRAM ZynqMP: - Change default load address for BL32
2025-12-19Merge tag 'u-boot-amlogic-next-20251219' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-amlogic into next - Add u-boot SPL support for GX SoCs - meson_gx_mmc: reduce maximum frequency - Add support for EFI capsule updates on all Amlogic boards
2025-12-19i2c: cdns: Add timeout for RXDV status bit pollingPadmarao Begari
Add a timeout mechanism when waiting for the RXDV (Receive Data Valid) status bit to be set before reading data from the FIFO. This prevents infinite polling loops that could occur if the hardware doesn't respond as expected. The timeout is set to 1000ms (CDNS_I2C_RXDV_TIMEOUT_MS) and uses the wait_for_bit_le32() function to poll the status register. If the timeout expires, an error code is returned. Signed-off-by: Padmarao Begari <[email protected]> Reviewed-by: Heiko Schocher <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/ba53d57c179f3390b32bc6094f3ffb5f4cde931e.1764169953.git.michal.simek@amd.com
2025-12-19xilinx: versal: Get rid of xlnx-versal-power.h from bindingsMichal Simek
Remove xlnx-versal-power.h dt binding header because they should be moved directly to folder where DTs are. In the Linux kernel this shift already started by moving xlnx-zynqmp-clk.h to arch/arm64/boot/dts/xilinx/ folder. U-Boot is using only one PD_DEV_OSPI constact which is moved to zynqmp_firmware.h header. But handling around it should be fixed anyway because no driver should be calling xilinx_pm_request() directly. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/a0f0154ef89929517c3217efe025e8021a910b90.1764233963.git.michal.simek@amd.com
2025-12-19arm64: versal2: Read and show multiboot valueMichal Simek
SOC can boot from different boot medias and also different offsets that's why by default show multiboot value to be aware which image system is booting out of. It is especially useful for systems with A/B update enabled. Also limit zynqmp_pm_get_pmc_multi_boot_reg() usage only for Versal and Versal Gen 2. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/fd7564ce2f51d965c273e939e98de01beb92e6f5.1764232124.git.michal.simek@amd.com
2025-12-19cadence_qspi: Update the delays for flash resetVenkatesh Yadav Abbarapu
Updating the delays for flash reset in the mini u-boot case. These experimental delay values by looking at different flash device vendors datasheets. Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/3fd0641a164a4d628fdf28a94771829f3bf9cb0c.1764181308.git.michal.simek@amd.com
2025-12-19cadence_qspi: Remove duplicated returnMichal Simek
The commit 6d234a79e9eb ("cadence_qspi: Refactor the flash reset functionality") introduced two returns in cadence_spi_probe() that's why remove it. Fixes: 6d234a79e9eb ("cadence_qspi: Refactor the flash reset functionality") Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/5f6d6db9c301daf10ddb707a9031f1a467d6ebf1.1764180937.git.michal.simek@amd.com
2025-12-19spi: cadence: Remove cdns,is-dma DT propertyMichal Simek
cdns,is-dma is not documented property that's why setup CQSPI_DMA_MODE quirk to enable DMA mode based on compatible string. And also change compatible string for mini configurations also with recording compatible string in the driver (Compatible string is already the part of existing DT binding). Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/f109829793900e57558d98ed22caf80c1a72b232.1762787994.git.michal.simek@amd.com
2025-12-19clk: versal: Enable clock driver for Versal Gen 2Michal Simek
Versal Gen 2 is using enhancement SMC format but in near future SCMI client should be used. This patch is just bridging this gap till SCMI server is fully tested. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/e83c665408d1453a464dd02cd2a25bb0ed267131.1762788250.git.michal.simek@amd.com
2025-12-19firmware: xilinx: Add support for enhancement SMC formatMichal Simek
Versal Gen 2 is using different SMC format that's why firmware and clock drivers needs to be align with it. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/16bdee56fd75113c6d531bae7a8a34900b10280d.1762788250.git.michal.simek@amd.com
2025-12-19clk: versal: Cleanup driverMichal Simek
Remove unneeded debug messages, parenthesis and fix error message. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/5b6fbcff1025415adc97e3e17eeb18863df4383e.1762778011.git.michal.simek@amd.com
2025-12-19clk: versal: Add support for CLK_AUTO_IDMichal Simek
When CLK_AUTO_ID is enabled 8 higher bits of clk->id is unique clock identifier in clk uclass that's why it is necessary to mask lower bits which are clock ID. Also check that ID not bigger then maximum supported clock. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/647f1d2c7d274c1106558a655386ef92e0baf2c8.1762778011.git.michal.simek@amd.com
2025-12-19clk: versal: Use __data macro for moving variable to data sectionMichal Simek
The commit 1b267fe1824e ("firmware: xilinx: Prepare code for new SMC firmware format") introduce new __data macro that's why use it in clock driver too. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/eac8d0ab60a018d6c59aa28c49691839a3eec174.1762511327.git.michal.simek@amd.com
2025-12-18Merge tag 'u-boot-socfpga-next-20251217' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-socfpga into next This pull request brings together a set of fixes and enhancements across the SoCFPGA platform family, with a focus on MMC/SPL robustness, EFI boot enablement, and Agilex5 SD/eMMC support. CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/28776 Highlights: * SPL / MMC: o Fix Kconfig handling for SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE o Correct raw sector calculations and respect explicit sector values when loading U-Boot from MMC in SPL o Adjust raw MMC loading logic for SoCFPGA platforms * EFI boot: o Permit EFI booting on SoCFPGA platforms o Disable mkeficapsule tool build for Arria 10 where unsupported * Agilex5: o Upgrade SDHCI controller from SD4HC to SD6HC o Enable MMC and Cadence SDHCI support in defconfig o Add dedicated eMMC device tree and defconfig for Agilex5 SoCDK o Revert incorrect GPIO configuration for SDIO_SEL o Refine U-Boot DT handling for SD and eMMC boot variants * SPI: o Allow disabling the DesignWare SPI driver in SPL via Kconfig * Board / configuration fixes: o Enable random MAC address generation for Cyclone V o Fix DE0-Nano-SoC boot configuration o Remove obsolete or conflicting options from multiple legacy SoCFPGA defconfigs
2025-12-17spi: designware: Allow disabling designware driver in SPLRalph Siemsen
To reduce SPL size, make it possible to exclude designware driver, while keeping it enabled in the main u-boot. Signed-off-by: Ralph Siemsen <[email protected]> Reviewed-by: Sean Anderson <[email protected]>
2025-12-17arm: dts: socfpga: agilex5: Upgrade SDHCI controller from SD4HC to SD6HCTanmay Kathpalia
Upgrade the SDHCI Cadence controller from SD4HC to SD6HC for Agilex5 platform to support the newer controller version with enhanced features. Key changes: - Remove combophy0 node and associated references as SD6HC doesn't require separate PHY configuration node - Upgrade MMC controller compatible from "cdns,sd4hc" to "cdns,sd6hc" - Add Agilex5-specific compatible string "altr,agilex5-sd6hc" for platform-specific optimizations Hardware configuration updates: - Add voltage regulator support: * sd_emmc_power: Fixed 3.3V regulator for card power supply * sd_io_1v8_reg: GPIO-controlled regulator for 1.8V/3.3V I/O switching - Configure proper reset control with named resets including combophy reset - Add GPIO control via portb pin 3 for voltage switching SD card operation: - Configure for SD card specific operation (no-mmc, cap-sd-highspeed) - Set maximum frequency to 200MHz - Configure timing parameters for SD modes: * Default Speed (DS) and UHS-I SDR12 mode timing: * High Speed and UHS-I SDR25 mode timing: - Add PHY timing delays for optimal signal integrity Signed-off-by: Tanmay Kathpalia <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-12-16pinctrl: single: Add missing free in single_allocate_functionFrancois Berder
If func->pins could not be allocated, one must also free func variable that was allocated previously. Signed-off-by: Francois Berder <[email protected]> Reviewed-by: Quentin Schulz <[email protected]>
2025-12-16clk: mediatek: remove duplicate '@parent' field docDavid Lechner
Remove duplicate '@parent' field documentation in struct mtk_composite. There is no need to say the same thing twice. Also fix spelling mistake in the word "parent" while we're at it. Signed-off-by: David Lechner <[email protected]>
2025-12-14rockchip: i2c: fix illegal I2C START/STOP conditionQuentin Schulz
In the last message sent in rockchip_i2c_xfer, the controller is disabled (see rk_i2c_disable() in rk_i2c_read()/rk_i2c_write()), then the STOP condition is sent (see rk_i2c_send_stop_bit() in rockchip_i2c_xfer()) and the controller is disabled once again (see rk_i2c_disable() right after). The issue is that re-enabling the controller just to send the STOP condition doesn't work. When, the controller is disabled, the SCL and SDA lanes are not driven anymore and thus enter the idle mode where they are kept high by the external HW pull-up. To send a STOP condition, one needs to drive the SDA line so that a rising edge happens while SCL is high. Experimentally (on PX30 and RK3399), when enabling the controller to send a STOP condition after it's been disabled, the controller only drives the SDA line to trigger the rising edge for the STOP condition, leaving SCL undriven (and thus, high). This means, that because SDA is high before this happens and that we need a rising edge, the controller drives the SDA line low and then releases it, meaning we trigger a START condition followed by a STOP condition: SCL _________ _____... __ _____ _____... \/ SDA ^ STOP ^ START This is illegal in I2C protocol[1]: 5. A START condition immediately followed by a STOP condition (void message) is an illegal format. Many devices however are designed to operate properly under this condition. My guess is that the I2C controller IP knows that it makes only sense to send a STOP condition after a START condition, meaning the controller is already driving the SCL line low and neither the device nor controller drive the SDA line after the last ACK/NACK as there's no need to, then it needs to drive SDA, release SCL to make it high and then release the SDA line. However, after it's been disabled, the SCL is already released so the controller only essentially drives SDA and then releases it. It happens that this seems to be breaking the SE050 Secure Element after a few transfers in the middle of a transfer where it starts clock stretching the bus forever. It may be related to Errata 3.2[2] but the description of the setup isn't an exact match to the current situation. It seems to be required to disable the I2C controller between messages as the Linux kernel states that "The HW is actually not capable of REPEATED START. But we can get the intended effect by resetting its internal state and issuing an ordinary START.". Between messages, this logic seems fine as I get an Sr (repeated START condition) before starting the next message in the transfer without a STOP condition. However, we should NOT disable the controller after the last message in the transfer otherwise we do this illegal START condition followed by the STOP condition, hence the added check. [1] https://www.nxp.com/docs/en/user-guide/UM10204.pdf 3.1.10 The target address and R/W bit point 5 [2] https://www.nxp.com/docs/en/errata/SE050_Erratasheet.pdf Fixes: c9fca5ec8849 ("rockchip: i2c: don't sent stop bit after each message") Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Heiko Schocher <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2025-12-14rockchip: i2c: move ACK comment where it appliesQuentin Schulz
The I2C_CON_LASTACK is kind of a misnomer as setting it means sending a NACK as last byte acknowledge when the controller is in receive mode. It should therefore be used only when there's no more data to transfer after this. Move the comment in the proper if block. Sync the comment with the Linux kernel's while at it so it's more explicit. Fixes: 5deaa530280f ("rockchip: i2c: fix >32 byte reads") Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Heiko Schocher <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2025-12-14rockchip: i2c: fix incorrect STOP flag for the interrupt enable registerQuentin Schulz
I2C_CON_STOP is a flag to be used for the con register, where it is bit 4 to send the STOP condition. To enable the interrupt the controller sends to tell it's finished sending the STOP condition, it's the ien register at bit 5. Let's use the proper offset. My hunch is that enabling the interrupt is useless as the interrupt status register is always up-to-date and enabling the interrupt is just so that the interrupt is available via the GIC. However, U-Boot has no interrupt support and the logic was working well before this patch. This is just so people aren't side-tracked when debugging I2C issues on Rockchip by checking all writes are proper. Fixes: 3437469985df ("rockchip: Add I2C driver") Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Heiko Schocher <[email protected]> Reviewed-by: Kever Yang <[email protected]>
2025-12-12Merge patch series "clk: ti: Cleanup common functions and omap-cm"Tom Rini
Markus Schneider-Pargmann (TI.com) <[email protected]> says: This series cleans up the direct dependency of ARCH_OMAP2PLUS to compile ti/clk.c which holds common functions for other clock drivers. It creates its own config symbols for these common functions and for the omap-cm driver as well. The omap-cm driver config symbol is added as default enabled. Link: https://lore.kernel.org/r/20251128-topic-am33-clk-regmap-dep-v2026-01-v2-0-451b4f4e7e85@baylibre.com/
2025-12-12clk: ti: omap4-cm: Add Kconfig symbolMarkus Schneider-Pargmann (TI.com)
Add a Kconfig symbol for this stub driver to avoid clock dependencies on an architecture symbol. Enable it by default. Signed-off-by: Markus Schneider-Pargmann (TI.com) <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2025-12-12clk: ti: Split common omap2plus functions into new symbolMarkus Schneider-Pargmann (TI.com)
Create a new symbol for the common clock functions used by some of the omap2plus clock drivers. These drivers now select this new symbol when they need the functions. Note these common functions are not ARCH_OMAP2PLUS specific. Note that the common functions are using regmap, so select it here. Reviewed-by: Tom Rini <[email protected]> Signed-off-by: Markus Schneider-Pargmann (TI.com) <[email protected]>
2025-12-12power: domain: Add ti-omap-prm stubMarkus Schneider-Pargmann (TI.com)
Upstream DT uses simple-pm-bus instead of simple-bus. simple-pm-bus requires power domain support. On am33xx, PRM manages power domains but all domains are enabled at boot. Add stub driver with custom of_xlate that expects no argumetns to allow simple-pm-bus and dependent devices to probe. Signed-off-by: Markus Schneider-Pargmann (TI.com) <[email protected]>
2025-12-12simple-pm-bus: Make clocks optionalMarkus Schneider-Pargmann (TI.com)
simple-pm-bus binding requires either power-domains or clocks, not both. Allow clk_get_bulk() to return -ENOENT. When no clocks are present, bulk->count is set to 0, which works correctly with clk_enable_bulk() and other clk functions used in this driver. Reviewed-by: Kory Maincent <[email protected]> Signed-off-by: Markus Schneider-Pargmann (TI.com) <[email protected]>
2025-12-12Revert "clk: Return value calculated by ERR_PTR"Tom Rini
While this change was intended to fix a mistake in the code, of calling the ERR_PTR macro but not making use of the result, it seems that functionally platforms depend on the loop not existing here. The TI K3 families of platforms for example were broken by this commit. This reverts commit fe780310cfa8bf5a093894b5cd7fe85c6b02fd91. Reported-by: Nishanth Menon <[email protected]> Reviewed-by: Andrew Goodbody <[email protected]> Reviewed-by: Nishanth Menon <[email protected]> Signed-off-by: Tom Rini <[email protected]>
2025-12-11mmc: meson_gx_mmc: reduce maximum frequencyNick Xie
Reduce the maximum frequency to 40MHz to be compatible with more eMMC. And the Amlogic vendor U-Boot also use the maximum frequency of 40MHz. Signed-off-by: Nick Xie <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Neil Armstrong <[email protected]>
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