| Age | Commit message (Collapse) | Author |
|---|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Mark Kettenis <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Acked-by: Quentin Schulz <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
https://source.denx.de/u-boot/custodians/u-boot-snapdragon into next
- SM6125 gains initial support
- The qcom clock drivers get better support for configuring UFS clocks
- ufetch gets some aesthetic improvements
- A minor bug in the qcm2290 clock driver is fixed
- A few qcom drivers get static/constified
- The GENI serial driver has the RX watermark register properly set
|
|
This changes the vote_bit same as enable_mask in Linux clock driver.
Fixes: 3ddc67573fab ("clk/qcom: qcm2290: Add SDCC1 apps clock frequency table")
Signed-off-by: Biswapriyo Nath <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
The UFS on SM6125 can reuse SM6115 configuration, just like Linux.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Biswapriyo Nath <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Add support for TLMM pin controller block (Top Level Mode Multiplexer)
on SM6125 SoC, with support for special pins.
Signed-off-by: Biswapriyo Nath <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
soc98: input: 1 [x] [email protected]
soc98: input: 0 [x] [email protected]
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Add clock driver for the GCC block found in the SM6125 SoC.
Signed-off-by: Biswapriyo Nath <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
soc98: input: 1 [x] [email protected]
soc98: input: 0 [x] [email protected]
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
The SE_GENI_RX_WATERMARK_REG was not being programmed in the RX
setup paths. Set it to DEF_RX_WM (2) in qcom_geni_serial_start_rx(),
msm_geni_serial_setup_rx() and _debug_uart_init() to align with the
Linux kernel driver behaviour.
Without this, the RX FIFO watermark interrupt threshold is left at
its hardware reset value, which may differ from the expected value
and can cause RX data loss or missed watermark interrupts.
Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Timple Raj M <[email protected]>
Signed-off-by: Gurumoorthy Santhakumar <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Csey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
The ufs_qcom_init() function was calling ufs_qcom_setup_clocks() with
POST_CHANGE twice. The first call after setting PA_TXHSADAPTTYPE
correctly enables the device reference clock. The second call after
ufs_qcom_advertise_quirks() is redundant as the clock is already
enabled.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Neha Malcom Francis <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Move UFS clock initialization and enabling before hardware setup
to ensure clocks are running when accessing UFS registers.
Previously, U-Boot depended on earlier bootloader stages to
initialize UFS clocks. When these bootloaders failed to do so,
UFS registers became inaccessible, causing initialization to fail.
This change makes U-Boot initialize and enable UFS clocks early
in the init sequence, removing the dependency on previous
bootloaders.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Add UFS clock support for sc7280 including register definitions,
rate configuration, and gate clocks.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Add UFS clock support for qcs615 including register definitions,
rate configuration, and gate clocks.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Add UFS clock support for SA8775P including register definitions,
rate configuration, and gate clocks.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Add RPMH clock compatible strings for QCS615 and SA8775P
SoCs to enable clock framework support on these platforms.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
Reorder compatible strings in stub_clk_ids to maintain alphabetical
order for easier maintenance.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/30134
- Several conversions to OF_UPSTREAM.
- Added i.MX9 Quickboot support.
- Added support for i.MX952 in the fsl_enetc driver.
- Update i.MX91 part number detection.
|
|
Extend ENETC driver to support i.MX952 platform where 2 ENETC
controllers are located on different PCIe buses.
Key changes:
- Add enetc_dev_id_imx() to derive device ID from device tree "reg"
property for i.MX952, mapping bus_devfn values 0x0 and 0x100 to device
IDs 0 and 1 respectively
- Implement imx952_netcmix_init() to configure MII protocol and PCS
settings based on PHY mode parsed from device tree
- Add i.MX952 to FSL_ENETC_NETC_BLK_CTRL Kconfig dependencies
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
|
|
The iMX and LS platforms use different bits in the same register to
set duplex, but their logics are opposite.
The current settings will result in unexpected configurations in
RGMII mode.
Fixes: e6df2f5e22c6 ("net: fsl_enetc: Update enetc driver to support i.MX95")
Signed-off-by: Clark Wang <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Tim Harvey <[email protected]>
|
|
pmic_reg_read returns a negative value if an error occurs. This
commit adds a missing check after calling pmic_reg_read.
Signed-off-by: Francois Berder <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
|
|
DDR training data can be saved to NVM and be available
to OEI at boot time, which will trigger QuickBoot flow.
U-Boot only checks for data integrity (CRC32), while
OEI is in charge of authentication when it tries to
load the data from NVM.
On iMX95 A0/A1, 'authentication' is done via another
CRC32. On the other SoCs, authentication is done by
using ELE to check the MAC stored in the ddrphy_qb_state
structure.
Supported platforms: iMX94, iMX95, iMX952 (using OEI)
Supported storage types: eMMC, SD, SPI flash.
Signed-off-by: Viorel Suman <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Simona Toaca <[email protected]>
|
|
In bus_i2c_stop, the MSR SDF is checked in a loop after stop command
is sent. Meanwhile, some error status in MSR is also checked by
imx_lpci2c_check_clear_error. But the imx_lpci2c_check_clear_error
will clear the MSR.
It causes problem in below situation:
In current loop, SDF does not set, but error status is found by
imx_lpci2c_check_clear_error (for example, NDF), then NDF will be cleared
and result has NDF error. However, because SDF does not set in this loop,
it goes not next loop. When SDF is set in next loop,
imx_lpci2c_check_clear_error is re-executed, but as the MSR is cleared,
the result is 0. Then the stop return 0. But it should return NDF error.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
|
|
devm_kzalloc needs to pass udevice for first parameter, this phy driver
wrongly pass the priv in phy_device. And because the dev in phy_device
is only valid after phy_connect, in probe phase this dev is NULL, so
we can't use devm_kzalloc, replace it with kzalloc.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Since commit 7917c2e35604 ("spi: fsl_espi: fix din offset") MTD is
basically broken because any read transaction will get wrong data. While
the commit in question will fix simple transfers (where both
SPI_XFER_BEGIN and SPI_XFER_END is set), it will break the most common
case, where opcode and address is send first and then data comes as a
second transfer.
This basically reverts commit 7917c2e35604 ("spi: fsl_espi: fix din
offset") and make the fix particular for this simple case. Instead of
providing two buffers for reading and writing, just malloc one which is
used for both. This will work because the data is first written on the
SPI bus and then it will be read (and overwite the written data) into
the same buffer.
Suggested-by: Tomas Alvarez Vanoli <[email protected]>
Fixes: 7917c2e35604 ("spi: fsl_espi: fix din offset")
Signed-off-by: Michael Walle <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: David Lechner <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
CV1800B SDHCI controller does support 1.8V, however, boards like
MilkV-Duo 256M do not have a VCCIO 1.8V regulator (the bus is wired for
3.3V only).
These boards set 'no-1-8-v' in their device tree, and mmc_of_parse()
does respect this property. Later, when sdhci_setup_cfg() is called, it
reads SDHCI_CAPABILITIES_1 from the hardware and unconditionally adds
the UHS caps again based on what the controller advertises. Since the
board cannot switch to 1.8V, the host issues CMD11 (voltage switch
request), the card transitions, but the bus stays at 3.3V. The SD card
stops responding until the next power cycle.
Before calling sdhci_setup_cfg(), set the SDHCI_QUIRK_NO_1_8_V quirk
when 'no-1-8-v' is present. The quirk causes the SDR104/SDR50/DDR50 bits
to be masked out of the caps, allowing the card to initialize properly.
This matches the pattern used by zynq_sdhci.
Fixes: eb36f28ff721 ("mmc: cv1800b: Add sdhci driver support for cv1800b SoC")
Signed-off-by: Hiago De Franco <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Set the ops structure as static const. The structure is not accessible
from outside of this driver and is not going to be modified at runtime.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
The status polling timeout in sdhci_send_command() should measure the
time spent waiting for the command interrupt after the command has been
issued.
Do not initialize the timer at function entry, since the command inhibit
wait and setup path can consume time before SDHCI_COMMAND is written.
Start the timer immediately after issuing the command instead.
Signed-off-by: Tanmay Kathpalia <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
