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Add support for configuring the SDCC1 apps clock on QCM2290 by introducing
a frequency table and enabling dynamic rate setting. Previously, the clock
was assumed to be fixed at 384 MHz by firmware, which limited flexibility
and correctness when selecting optimal rates for SD/MMC operations.
Suggested-by: Sumit Garg <[email protected]>
Signed-off-by: Loic Poulain <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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When 'max-clk' is not specified, the SDHCI core retrieves the base clock
from the SDHCI_CAPABILITIES register (bits [15:8]). However, this field
is unreliable on MSM SDHCI controllers, as noted by the Linux driver
using the SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN flag. In addition, the field
is only 8 bits wide and cannot represent base clocks above 255 MHz.
On platforms like Agatti/QCM2290, the firmware sets the SDHCI clock to
384 MHz, but the capabilities register reports 200 MHz. As a result,
the core calculates a divider of 4, producing a 96 MHz SDCLK instead of
the intended ~52 MHz. This overclocking can cause sporadic CRC errors
with certain eMMC.
To fix this, use the actual clock rate reported by the SDHCI core clock
instead of relying on the capabilities register for divider calculation.
Signed-off-by: Loic Poulain <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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This change is imported from Linux driver and tested with SM6125 SoC.
Note, the msm8996_phy_cfg struct is same as sdm660_phy_cfg but
qusb2_phy_cfg::se_clk_scheme_default differs only.
Signed-off-by: Biswapriyo Nath <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The power on function for the phy only deasserts the reset, so the phy
might be in a weird state that we don't clean up properly.
Assert the reset in probe() so that when we power on we will have the
phy in a clean state.
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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host count
The SMEM driver was failing to resolve memory regions on some boards
because `dev_of_offset()` + `fdtdec_lookup_phandle()` did not yield a
valid DT node. Modernize the code to use driver-model/ofnode accessors
and make the probe robust for both DT styles (direct `reg` vs
`memory-region` phandle).
- qcom_smem_map_memory():
* Drop fdtdec path; use dev_read_phandle_with_args() +
ofnode_read_resource().
* Use dev_read_phandle_with_args() +
fnode_read_resource().
- qcom_smem_probe():
* Try dev_read_addr_size() first (map via <reg>), else fall back to
qcom_smem_map_memory() with "memory-region".
* Check "qcom,rpm-msg-ram" presence to add second region.
- Additionally, SMEM_HOST_COUNT is increased to support newer SMEM
versions that include more remote processors. This avoids failures
during processor ID checks.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Varadarajan Narayanan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Introduce a new Kconfig option PINCTRL_QCOM_GENERIC that, when selected,
enables all Qualcomm pinctrl drivers by default. This simplifies defconfigs
for platforms supporting multiple SoCs and avoids manual driver selection.
Individual drivers can still be disabled if required.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add pinctrl driver for QCS615. Driver code is based on the
similar U-Boot and Linux drivers.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add the PM8150, PM8350, and PM7325 regulator data found on Qualcomm
platforms. These regulator tables are imported from the Linux driver
to enable support for these PMICs in U-Boot.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Correct ARCH_QCOM to ARCH_SNAPDRAGON as ARCH_QCOM is outdated/unused
config. Using ARCH_QCOM was causing USB fastboot mode to fail.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Acked-by: Mattijs Korpershoek <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Added delays before and after setting the PIPE_UTMI_CLK_SEL and
PIPE3_PHYSTATUS_SW bits in the Qscratch GENERAL_CFG register
during UTMI clock selection for DWC3 on Qualcomm platforms.
These delays help ensure proper timing and stability of the UTMI
clock switching sequence, potentially avoiding race conditions or
unstable PHY behavior during initialization.
Tested on platforms using Qscratch-based DWC3 PHY configuration.
This change is taken from this Linux kernel implementation:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/usb/dwc3/dwc3-qcom.c?id=a4333c3a6ba9ca9cff50a3c1d1bf193dc5489e1c
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Added a check to ensure the requested timeout does not exceed the
hardware's maximum supported value. This prevents register overflow
and ensures watchdog reliability.
So, added a check in qcom_wdt_start() to ensure the requested timeout
does not exceed the hardware-supported maximum value. If the requested
value exceeds the maximum value, then the timeout is clamped
at maximum value.
The timeout is first converted to watchdog ticks and then compared
against QCOM_WDT_MAX_TIMEOUT. This helps prevent misconfiguration
and potential watchdog misbehavior due to overflow.
QCOM_WDT_MAX_TIMEOUT is set to 0xFFFFF, as Qualcomm SoCs typically
use 20 bits to store bark/bite timeout values.
This work builds upon the previous submission:
https://lore.kernel.org/u-boot/[email protected]/
Signed-off-by: Gopinath Sekar <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Ported from the Mediatek SDK. The upstream Linux kernel also has the
same register map as the SDK.
Signed-off-by: Shiji Yang <[email protected]>
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The "fixed-layout" nvmem controller subnode used to be optional wrapper
around nvmem controller cells subnodes. The "fixed-layout" node is now
mandatory in most cases, but in order to support both recent and legacy
DTs, both variants have to be supported.
Implement support for the "fixed-layout" node in the most trivial manner,
check whether the nvmem cell supernode is compatible with "fixed-layout"
and if it is, proceed one level above it to find the nvmem controller.
Signed-off-by: Marek Vasut <[email protected]>
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David Lechner <[email protected]> says:
MT8365 has different pinctrl register layout compared to other SoCs in
the family, so needs its own driver.
This is also the first SoC in this family supported in U-Boot using an
upstream devicetree that has the mediatek,pctl-regmap property, so we
need to add support for that to the common mediatek pinctrl code first.
Link: https://lore.kernel.org/r/[email protected]
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Add pinctrl support for MT8365 SoC.
Signed-off-by: Julien Masson <[email protected]>
Signed-off-by: Vitor Sato Eschholz <[email protected]>
Signed-off-by: David Lechner <[email protected]>
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Add support for the mediatek,pctl-regmap devicetree property to the
common MediaTek pinctrl driver.
In upstream devicetrees from Linux, the pinctrl nodes may be on the
interrupt controller register address space rather than the pinctrl
register address space. In this case, there is a syscon node linking to
the actual pinctrl registers. This uses a common property name of
mediatek,pctl-regmap for the phandle to the syscon node.
The logic here is that if this property is present, we look up the
syscon node and use it's address as the base address of the pinctrl
registers and ignore the pinctrl node's own reg property. (Support
for interrupts could be added later if needed.)
There is also at least one SoC in Linux that has two syscon phandles
in this property. This implementation support parsing this, but doesn't
do anything with the second syscon yet (the 2nd syscon is for interrupts
which we are saving for later).
Signed-off-by: David Lechner <[email protected]>
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Use a ID map to add clocks for the missing CLK_TOP_CLK32K and
CLK_TOP_CLK26M that were not included in the devicetree definitions.
This fixes getting the rate of any clock that had one of these as a
parent.
CLK_TOP_UNIVPLL does not appear to be a real clock, so it is omitted
now since we can do that with the ID map as well.
Signed-off-by: David Lechner <[email protected]>
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Remove the separate topckgen-cg driver for handling clock gates in the
topckgen address space. The devicetree bindings for this were not
acceptable upstream because it was creating a separate clock controller
using the same address space as the main topckgen clock controller. The
gates are moved to the topckgen tree instead.
Signed-off-by: David Lechner <[email protected]>
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Add handling for gates in the topckgen clk drivers. This avoids the need
to have separate topckgen-cg drivers and devicetree nodes for the same
address space and clock ID range.
Signed-off-by: David Lechner <[email protected]>
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Split the struct mtk_clk_tree for MT8365 into separate structures for
the apmixedsys, topckgen and infracfg clock controllers. This is needed
to support moving the topckgen gates into the struct mtk_clk_tree. Since
apmixedsys can also have gates, we need separate structures.
Signed-off-by: David Lechner <[email protected]>
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Fix a number of clock parent definitions for MT8365 clocks. Most of
these are just informational or don't make a function change.
The clocks with the new PLL_FACTOR2 macro and the change in apu_parents
are fixing actual bugs.
Signed-off-by: David Lechner <[email protected]>
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Add a flags field to struct mtk_fixed_clk to allow properly resolving
the parent clock. All chip-specific clocks are updated to populate this
field correctly.
The parent is currently only used for printing debug information, so
there are no functional bugs being fixed.
Signed-off-by: David Lechner <[email protected]>
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Add a gates_offs field to struct mtk_cg_priv and use that instead of
struct mtk_clk_tree.gates_offs.
Prior to this change, struct mtk_clk_tree.gates_offs could be the offset
of struct mtk_clk_tree.gates or struct mtk_cg_priv.gates depending on
the context. This was confusing and error-prone. For example, in mt8365
there is one set of gates that needs an offset and one that does not
that share the same struct mtk_clk_tree. This is fixed in this patch by
giving the correct offset for each gate separately.
Signed-off-by: David Lechner <[email protected]>
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Fix a few missing clocks and even more clocks in the incorrect order.
Since the clocks are looked up by index, having them out of order or
skipping an ID will lead to incorrect clocks being used.
Signed-off-by: David Lechner <[email protected]>
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David Lechner <[email protected]> says:
I started looking into fixing some bugs in the mt8365 clock driver and
realized that there was no way to inspect or debug the clock trees.
I set out to implement the dump function to help with this. The driver
architecture didn't make this easy since there was no way to know the
number of elements in each of the clock arrays. The first few patches
in this series are adding fields to the data structures to hold this
information.
Once that was fixed, I was still getting crashes due to other bugs. To
work around this, I implemented the of_xlate function to validate clk
IDs as early as possible and return errors instead of crashing when
requested IDs are invalid. This also makes use of the new size fields
to prevent out of bounds array accesses. There are a couple of drivers
that remap IDs, so there are a few extra patches to handle that as well.
Then finally, I was able to implement the dump function to print out the
clock tree information without crashing. In the v1 cover letter, there
is an example of the output (it is quite long and doesn't need to be
repeated here).
Link: https://lore.kernel.org/r/[email protected]
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Implement dump callbacks for Mediatek clocks. On these platforms, there
are 100s of clocks, so it can be easy to miss mistakes. The dump
callbacks will be useful for debugging and verifying clock configs.
Signed-off-by: David Lechner <[email protected]>
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Add range initializers to the id_offs_map arrays in the mt7623 clk
driver to set unmapped IDs to -1. This prevents accidental usage of
unmapped IDs that would otherwise map to 0.
mtk_common_clk_of_xlate() checks these values for < 0 and returns
-ENOENT in that case.
A range initializer covering the entire array is used since it is less
error-prone than manually looking up the value of each macro in the
existing initializers and checking for gaps. It is placed first so that
the specific initializers override it.
Signed-off-by: David Lechner <[email protected]>
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Update documentation comments to clarify the difference between which
.id fields are mapped (only struct clk.id) vs. unmapped (all struct
mtk_*.id and .parent fields). The unmapped IDs are the ones defined
in the devicetree bindings, while the mapped IDs are the ones used as
the index into the various clk arrays.
Also fix spelling of "parent" while we are touching this.
Signed-off-by: David Lechner <[email protected]>
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Add driver-specific of_xlate ops for MediaTek clocks. This provides
better checking of the args passed from the devicetree. Compared to
the default of_xlate implementation, this will return -EINVAL if there
are zero args (id is always required) and -ENOENT if the id is out of
range for the clock type. This will protect against out of bounds array
accesses later on when the clk->id is used to index into the clock
data arrays.
If there is a id_offs_map, then we have to do that translation first
before checking the id to see if it is in range. There is no sense in
doing the mapping multiple times, so we save the mapped ID in clk->id
and remove mtk_clk_get_id().
mtk_clk_find_parent_rate() also had to be updated since it creates a
temporary struct clk to represent the parent clock. It now has do the
translation in case the parent clock also uses an id_offs_map.
Signed-off-by: David Lechner <[email protected]>
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Move all infrasys ops and related functions next to each other in the
file for better organization.
Generally all ops functions are grouped together like this for the other
ops types (apmixedsys, topckgen, etc). However the infrasys functions
were mixed in with the other sections making them harder to find. This
will also give a logical place to add any future infrasys-specific
functions.
Signed-off-by: David Lechner <[email protected]>
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Add id_offs_map_size field to struct mtk_clk_tree and populate it for
all existing drivers.
Currently, there is no bounds checking when accessing the id_offs_map
array. Adding this field will allow for bounds checking in the future.
Signed-off-by: David Lechner <[email protected]>
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Add num_gates field to struct mtk_cg_priv and populate it for all
existing drivers.
Currently, there is no bounds checking when accessing the gates array.
Adding this field will allow for bounds checking in the future.
Signed-off-by: David Lechner <[email protected]>
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Add num_plls, num_fclks, num_fdivs, num_muxes, and num_gates fields to
the mtk_clk_tree struct and populate them in the clk trees for all
existing drivers.
Currently, there is no bounds checking when accessing the arrays in
the clk tree structs. Adding these fields will allow for bounds checking
in the future.
Signed-off-by: David Lechner <[email protected]>
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For PCIe and DisplayPort, the phy instance represents the controller's
logical lane. Wait for the instance 0 phy's PLL to lock as other
instances will never lock. We do this in xpsgtr_wait_pll_lock so callers
don't have to determine the correct lane themselves.
The original comment is wrong about cumulative wait times. Since we are
just polling a bit, all subsequent waiters will finish immediately.
Signed-off-by: Sean Anderson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
[ Linux commit 235d8b663ab9e6cc13f8374abfffa559f50b57b6 ]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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The phy "type" is just the combination of protocol and instance, and is
never used apart from that. Store the instance directly, instead of
converting to a type first. No functional change intended.
Signed-off-by: Sean Anderson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
[ Linux commit 6959d2367bc3503ac4ba3eb4ec6584a43150d6b3 ]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Lanes can use other lanes' reference clocks, as determined by refclk.
Use refclk to determine the clock to enable/disable instead of always
using the lane's own reference clock. This ensures the clock selected in
xpsgtr_configure_pll is the one enabled.
For the other half of the equation, always program REF_CLK_SEL even when
we are selecting the lane's own clock. This ensures that Linux's idea of
the reference clock matches the hardware. We use the "local" clock mux
for this instead of going through the ref clock network.
Signed-off-by: Sean Anderson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
[ Linux commit 687d6bccb28238fcfa65f7c1badfdfeac498c428 ]
Fixes: 1d78d683496 ("phy: zynqmp: Add serdes/psgtr driver")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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Due to limited available frequency ratios, the reference clock rate may
not be exactly the same as the required rate. Allow a small (100 ppm)
deviation.
Signed-off-by: Sean Anderson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
[ Linux commit 76009ee76e05e30e29aade02e788aebe9ce9ffd2 ]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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The ECAM will return a slave error if we access non-root devices while
the link is down. Add a check for this like Linux does so we don't
crash.
Fixes: 2f5ad77cfea ("PCI: zynqmp: Add ZynqMP NWL PCIe root port driver")
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Align reset names with DT binding.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/e1082054610fe73d4487d12f4274315030592c77.1765813212.git.michal.simek@amd.com
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Align clockt name with DT binding.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/eadc8d159b6d822077549722c9ec5a96a4d16c2a.1765973221.git.michal.simek@amd.com
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Tom Rini <[email protected]> says:
As seen by a number of patches fixing memory leaks, U-Boot has a problem
with developer expectations around devm_kmalloc and friends. Namely,
whereas in Linux these memory allocations will be freed automatically in
most cases, in U-Boot this is only true if DEVRES is enabled. Now,
intentionally, in xPL phases, we do not (and do not offer as an option)
enabling DEVRES. However in full U-Boot this is left either to the user,
or some drivers have select'd DEVRES on their own. This inconsistency is
a problem. This series goes and deals with two small issues that were
shown by having all drivers that use devm_.alloc to allocate memory also
select DEVRES and then we make DEVRES no longer be a prompted option and
instead select'd as needed. We do not make this unconditional as it
would result in growing the resulting binary on the many platforms which
have no users of the devm_.alloc family of functions.
Link: https://lore.kernel.org/r/[email protected]
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The devm alloc functions that we have may follow the Linux kernel model
where allocations are (almost always) automatically free()'d. However,
quite often we don't enable, in full U-Boot, the tracking and free()'ing
functionality. This in turn leads to memory leaks because the driver
author expects that since the functions have the same name as in the
Linux Kernel they have the same behavior. In turn we then get
functionally correct commits such as commit 00e1fed93c8c ("firmware:
ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually
add these calls. Rather than manually tracking allocations and
implementing free()s, rework things so that we follow expectations by
enabling the DEVRES functionality (outside of xPL phases).
This turns DEVRES from a prompted symbol to a symbol that must be
select'd, and we now remove our non-managed alloc/free functions from
outside of xPL builds.
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Make a note in an unexpected situation, e.g. queuing a request
on a disabled endpoint, enabling an enabled endpoint...
Reviewed-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: Petr Beneš <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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There are two places where ci_ep->desc could be accessed despite it is
not valid at that moment. Either the endpoint has not been enabled yet
or it has been disabled meanwhile (The ethernet gadged behaves this way
at least.). That results in dereferencing a null pointer.
Moreover, the patch gets rid of possible outstanding requests if the
endpoint's state changes to disabled.
Signed-off-by: Petr Beneš <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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- DWC3 for exynos7870
- Avoid a noisy message on xhci controllers
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handling"
This reverts commit aebb523a23818a8ee4199c9532b51e3d4020696f.
The change to use dev_read_u32_default() with a default value of 0
causes regression for host controller drivers that hardcode f_max
before calling mmc_of_parse().
When the "max-frequency" property is not specified in the device tree,
dev_read_u32_default() returns 0, which overwrites the previously
configured f_max value set by the driver. This effectively resets
the maximum frequency to 0, breaking MMC functionality for those
controllers.
Revert to the original dev_read_u32() behavior which only updates
cfg->f_max when the "max-frequency" property is explicitly present
in the device tree, preserving driver-configured values otherwise.
Signed-off-by: Tanmay Kathpalia <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Exynos7870's DWC3 glue layer is quite simple, consisting of a few
clocks, which is handled by this driver. Add the compatible string in
here.
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Kaustabh Chakraborty <[email protected]>
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Documentation [1] states that the default value of the dr_mode property
is "otg". It also isn't marked a mandatory node, so it may or may not be
set. So, accordingly if dr_mode is not mentioned in the devicetree node,
OTG mode must be assumed.
In this driver however, this case is not handled. If dr_mode is not
mentioned, USB_DR_MODE_UNKNOWN is set. The logic implemented raises an
error, instead of falling back to USB_DR_MODE_OTG. Correct this to
conform to the specification.
Link: https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/tree/Bindings/usb/usb-drd.yaml?h=v6.18-dts [1]
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Kaustabh Chakraborty <[email protected]>
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We should avoid overwhelming users with non-essential messages.
The message 'Starting the controller' is not written for EHCI.
We should not write it for XHCI either.
Adjust the Python test accordingly.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
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Currently CRC16 is not selected when CRC checking is enabled and
if it wasn't enabled in the config otherwise the build will fail
because of references to crc16_ccitt() that doesn't exist.
Signed-off-by: Daniel Palmer <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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