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According to the TI DP83869HM datasheet Revision D (June 2025), section
7.6.1.41 STRAP_STS Register, the STRAP_OPMODE bitmask is bit [11:9].
Fix this.
In case the PHY is auto-detected via PHY ID registers, or not described
in DT, or, in case the PHY is described in DT but the optional DT property
"ti,op-mode" is not present, then the driver reads out the PHY functional
mode (RGMII, SGMII, ...) from hardware straps.
Currently, all upstream users of this PHY specify both DT compatible string
"ethernet-phy-id2000.a0f1" and ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>
property, therefore it seems no upstream users are affected by this bug.
The driver currently interprets bits [2:0] of STRAP_STS register as PHY
functional mode. Those bits are controlled by ANEG_DIS, ANEGSEL_0 straps
and an always-zero reserved bit. Systems that use RGMII-to-Copper functional
mode are unlikely to disable auto-negotiation via ANEG_DIS strap, or change
auto-negotiation behavior via ANEGSEL_0 strap. Therefore, even with this bug
in place, the STRAP_STS register content is likely going to be interpreted
by the driver as RGMII-to-Copper mode.
However, for a system with PHY functional mode strapping set to other mode
than RGMII-to-Copper, the driver is likely to misinterpret the strapping
as RGMII-to-Copper and misconfigure the PHY.
For example, on a system with SGMII-to-Copper strapping, the STRAP_STS
register reads as 0x0c20, but the PHY ends up being configured for
incompatible RGMII-to-Copper mode.
Fixes: f3e22eea815d ("net: phy: add TI DP83869HM ethernet driver")
Signed-off-by: Thanh Quan <[email protected]>
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]> # Use FIELD_GET()
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Restore legacy implementation of retrieving clkmgr base address from
mach-socfpga/misc.c driver for our legacy devices.
Excluding Agilex7/7M from this implementation as these devices' clock
driver is already following clock driver model and is supporting
enable/disable APIs.
The legacy devices' clock driver will have to be refactored to support
driver model which enables us to support enable/disable APIs for these
devices.
Fixes: ab27182cac8f ("mmc: socfpga_dw_mmc: Enable/disable SDMMC clock via API")
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Enable ONFI parameter page detection for SoCFPGA SoC64 devices by
selecting SYS_NAND_ONFI_DETECTION in the NAND_DENALI Kconfig entry.
This allows SoCFPGA SoC64 platforms using the Denali NAND controller
to automatically detect NAND parameters via the ONFI interface instead
of relying on hardcoded configuration values.
The selection is limited to TARGET_SOCFPGA_SOC64 to avoid affecting
non-SoC64 platforms that use legacy NAND handling.
Signed-off-by: Dinesh Maniyam <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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This patch ports the Cadence xSPI controller driver from
the Linux kernel. The controller supports three operating modes:
1. ACMD (Auto Command) mode
- Includes PIO and CDMA submodes.
- CDMA mode uses linked descriptors for high-performance,
low-overhead operation.
- PIO mode is suitable for simple, single-command transactions.
2. STIG (Software Triggered Instruction Generator) mode
- Issues low-level 128-bit instructions to memory.
- Uses the Slave DMA interface for data transfers.
3. Direct mode
- Enables direct data access through the slave interface
without commands.
Currently, only the STIG work mode is enabled. Additional modes will be
supported in future updates.
At the same time, also enabling the kconfig option for xSPI driver.
This driver has been ported and functionally verified on the Intel Simics
platform. It is intended for evaluation and experimental use at this stage.
Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Boon Khai Ng <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Add SPL_DWAPB_GPIO configuration option to enable the Designware APB
GPIO driver in SPL builds.
Changes:
- Add SPL_DWAPB_GPIO Kconfig option with SPL_DM_GPIO dependency
- Update Makefile to use CONFIG_$(PHASE_)DWAPB_GPIO pattern for
conditional compilation in both SPL and main U-Boot builds
Signed-off-by: Tanmay Kathpalia <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Currently, clause-22 format is supported. This change adds
support for clause-45 format.
Signed-off-by: Nikunj Kela <[email protected]>
Reviewed-by: Boon Khai Ng <[email protected]>
Tested-by: Boon Khai Ng <[email protected]>
Reviewed-by: Boon Khai Ng <[email protected]>
Tested-by: Boon Khai Ng <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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The last parameter to device_bind_driver_to_node is optional.
Since the returned information is not used and overwritten by
uclass_get_device_by_ofnode just provide NULL as parameter.
Signed-off-by: Markus Niebel <[email protected]>
Signed-off-by: Alexander Stein <[email protected]>
Signed-off-by: Alexander Feilke <[email protected]>
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When using DM_MDIO on SOC with more than one FEC and not sharing the MDIO
bus the name of the driver and the bus needs to be unique. Since name
used in device_bind_driver_to_node needs to be a static string, add the
string to the fec_priv struct and reuse fec_set_dev_name to generate the
name with the device sequence number.
Fixes: 3b8f99a3e762 ("net: fec: add support for DM_MDIO")
Signed-off-by: Markus Niebel <[email protected]>
Signed-off-by: Alexander Stein <[email protected]>
Signed-off-by: Alexander Feilke <[email protected]>
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If DM_ETH_PHY is used and the FEC instance owns the shared MDIO bus,
eth_phy_get_mdio_bus returns NULL. If DM_MDIO bus is used, the
mdio_register API is called from dm_mdio_post_probe. Therefore the
bus should must be queried by name in this case.
For DM_MDIO case fec_mii_setspeed has already being called in
dm_fec_mdio_probe(), so skip setting this again.
Fixes: 3b8f99a3e762 ("net: fec: add support for DM_MDIO")
Fixes: e75d08821574 ("net: fec-mxc: prevent crash if no MAC address is set")
Signed-off-by: Markus Niebel <[email protected]>
Signed-off-by: Alexander Stein <[email protected]>
Signed-off-by: Alexander Feilke <[email protected]>
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The code should only be executed if MDIO bus is not assigned.
Otherwise the already assigned / allocated bus will be overwritten.
Add condition check and simplify the code to make it more readable.
Signed-off-by: Markus Niebel <[email protected]>
Signed-off-by: Alexander Stein <[email protected]>
Signed-off-by: Alexander Feilke <[email protected]>
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If DM_MDIO is used and the FEC device is removed the mdio API
must not be used to remove the bus structure. Store pointer the
the udevice for MDIO bus created by dm_fec_bind_mdio and use DM
functions to cleanup the device in fecmxc_remove.
Fixes: 3b8f99a3e762 ("net: fec: add support for DM_MDIO")
Signed-off-by: Markus Niebel <[email protected]>
Signed-off-by: Alexander Stein <[email protected]>
Signed-off-by: Alexander Feilke <[email protected]>
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When initializing the MDIO bus the MDC signal needs to be configured.
Otherwise the communication over the bus may fail. Add the call to
fec_mii_setspeed to the DM_MDIO probe handler.
Fixes: 3b8f99a3e762 ("net: fec: add support for DM_MDIO")
Signed-off-by: Markus Niebel <[email protected]>
Signed-off-by: Alexander Stein <[email protected]>
Signed-off-by: Alexander Feilke <[email protected]>
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If no MAC address can be found (either in ROM, device tree or env),
the post_probe of an ethernet device will fail and therefore
the device cannot be instantiated.
The DM_ETH_PHY (eth-phy-uclass) use case must not be mixed with
using CONFIG_FEC_MXC_MDIO_BASE.
This prevents following error for MAC not fused, no eth[1]addr
env is present and providing a random MAC is disabled:
Net:
Error: ethernet@5b040000 address not set.
Error: ethernet@5b040000 address not set.
FEC: can't find phy-handle
"Error" handler, esr 0xbf000002
elr: 000000008004e4b8 lr : 000000008004e4b4 (reloc)
elr: 00000000bfe984b8 lr : 00000000bfe984b4
x0 : 0000000000000000 x1 : 0000000000000020
x2 : 00000000bbe61e50 x3 : 00000000bbe6e1a0
x4 : 0000000000000020 x5 : 0000000000000020
x6 : 000000000000000a x7 : 0000000000000000
x8 : 0000000000000000 x9 : 0000000000000008
x10: 00000000ffffffd8 x11: 0000000000000006
x12: 000000000001869f x13: 0000000000002c50
x14: 0000000000000000 x15: 00000000ffffffff
x16: 0000000000000000 x17: 0000000000000000
x18: 00000000bbe61d98 x19: 00000000bbe4fa68
x20: 00000000bbe78c10 x21: 00000000bbe6e460
x22: 00000000bbe78c10 x23: 00000000bbe91780
x24: 00000000bbe6e510 x25: 00000000000001f8
x26: 00000000ffff8000 x27: 0000000000000000
x28: 0000000000000000 x29: 00000000bbe4fa10
Code: f900003f 9100a3a1 97ffff6e 35000100 (f94017a1)
Resetting CPU ...
Signed-off-by: Markus Niebel <[email protected]>
Signed-off-by: Alexander Feilke <[email protected]>
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phy_config may fail - for instance in parsing device tree.
This should be handled correctly. So return errors from
phy_config to caller.
Signed-off-by: Markus Niebel <[email protected]>
Signed-off-by: Alexander Feilke <[email protected]>
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Add support for the Microcrystal RV3032 RTC.
Signed-off-by: Michael Walle <[email protected]>
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Add support for the Microcrystal RV8263 and compatible RTCs. The
driver's name was taken from linux. It should work with any NXP PCF85063
compatible RTCs. It was tested with a RV8263.
Signed-off-by: Michael Walle <[email protected]>
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As u-boot doesn't have any loadable modules, tristate doesn't make
sense. Convert it to bool.
Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
Updates for RPi for 2026.01-rc4:
- rpi: Fix DRAM size reporting to show total RAM
- rpi: Use the U-Boot control FDT for fdt_addr
- pinctrl: bcm283x: Add GPIO pull-up/down control for BCM2835 and BCM2711
- rpi: Fix compilation with larger configs
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We should avoid overwhelming users with non-essential messages.
'Register NbrPorts' is a debug message for EHCI. Do the same for XHCI.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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CONFIG_USB_EHCI_PCI cannot work without CONFIG_PCI.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Currently, the bind callback of the driver namely am65_cpsw_nuss_bind()
registers all ethernet ports including the ones that have been disabled
in the device-tree. Since the ports that have been disabled are ought to
be ignored, fix the implementation to register only the enabled ports as
indicated by their 'status' in their respective device-tree node.
Fixes: 3943531a5468 ("net: ti: am65-cpsw-nuss: Define bind method for CPSW driver")
Reported-by: Wadim Egorov <[email protected]>
Closes: https://patch.msgid.link/[email protected]
Signed-off-by: Siddharth Vadapalli <[email protected]>
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The helper function "ti_pd_get()" is responsible for powering on a
domain if it is powered off. In the current implementation, if a power
domain is determined to be powered off - no prior users and the PDCTL
register indicates that the user desired state is OFF, then powering on
the domain constitutes setting 'PDCTL_STATE_ON' field of the PDCTL
register.
While the current implementation indeed requests the power domain to be
transition to the ON state, the helper function "ti_pd_get()" doesn't
verify that the power domain has 'transitioned' to the ON state before
returning to its caller. As a result, it is possible that the device(s)
belonging to the power domain may be accessed before it is truly powered
on, leading to a bus abort.
Fix this by waiting for the power domain to transition to the ON state
by using "ti_pd_wait()" before returning from "ti_pd_get()".
Fixes: 144464bd2c67 ("power: domain: Introduce driver for raw TI K3 PDs")
Signed-off-by: Siddharth Vadapalli <[email protected]>
Tested-by: Hrushikesh Salunke <[email protected]>
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Align the Kconfig option with the rest of the subsystem, use
CONFIG_UFS_<vendor> format for the Kconfig option.
Signed-off-by: Marek Vasut <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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Align the Kconfig option with the rest of the subsystem, use
CONFIG_UFS_<vendor> format for the Kconfig option.
Signed-off-by: Marek Vasut <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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Align the Kconfig option with the rest of the subsystem, use
CONFIG_UFS_<vendor> format for the Kconfig option.
Signed-off-by: Marek Vasut <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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Align the Kconfig option with the rest of the subsystem, use
CONFIG_UFS_<vendor> format for the Kconfig option.
Signed-off-by: Marek Vasut <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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There is a condition guard which ensures that the GPIO node, indeed
describes a GPIO controller.
if (!fdtdec_get_bool(blob, node, "gpio-controller"))
continue;
Since the bank base is being incremented in the loop, it is done so
irrespective of whether the node is a GPIO controller or not. This leads
to the incorrect resolution of bank base addresses.
Move it out of the loop, and instead increment the bank base address
only if the driver successfully binds a GPIO controller.
Reviewed-by: Henrik Grimler <[email protected]>
Fixes: b8809e60cdb5 ("dm: exynos: gpio: Convert to driver model")
Signed-off-by: Kaustabh Chakraborty <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This patch adds support for configuring GPIO pull-up and pull-down
resistors in the BCM283x pinctrl driver. It implements the brcm,pull
device tree property to control pin bias settings.
The implementation follows the hardware-specific pull control
mechanisms:
- BCM2835: two-step GPPUD register sequence
- BCM2711: direct per-pin control registers
This enables device tree configurations to specify pull-up, pull-down,
or no bias for individual GPIO pins.
Tested on Raspberry Pi boards with both BCM2835 and BCM2711 SoCs.
Signed-off-by: Cibil Pankiras <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
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Prepare v2026.01-rc3
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1. Get partition info/size
2. Erase partition
3. Flash partition
4. BCB
Make FASTBOOT_FLASH also depend on BLK, but make sure
it doesn't affect SUNXI and ROCKCHIP platforms since they
default to y already.
Make it only default on SUNXI when MMC or NAND is enabled,
so it doesn't break the CHIP & Nintendo boards, and for ROCKCHIP
when MMC is enabled.
Signed-off-by: Dmitrii Merkurev <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Tested-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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Switch the mmc backend to this new shared block helpers,
reducing block logic and only leaving MMC specific logic.
Signed-off-by: Dmitrii Merkurev <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Tested-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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Introduce fastboot block flashing functions and helpers
to be shared with the MMC implementation.
The write logic comes from the mmc implementation, while
the partition lookup is much simpler and could be extended.
For the erase logic, allmost no block drivers exposes the
erase operation, except mmc & virtio, so in order to allow
erasiong any partition a soft-erase logic has been added
to write zero-ed buffers in a loop.
Signed-off-by: Dmitrii Merkurev <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Tested-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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"timing" and "timing_res_idx" are unused and not exist in Linux driver,
let's remove them.
Signed-off-by: Zixun LI <[email protected]>
Acked-by: Alexander Dahl <[email protected]>
Reviewed-by: Eugen Hristev <[email protected]>
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Setup the pmecc data setup time as 3 clock cycles for 133MHz as
recommended by the datasheet.
Backported from Linux: f55f552a7c7e0a1 ("mtd: rawnand: atmel: set pmecc
data setup time")
Fixes: a490e1b7c017c ("nand: atmel: Add pmecc driver")
Signed-off-by: Zixun LI <[email protected]>
Tested-by: Alexander Dahl <[email protected]>
Reviewed-by: Eugen Hristev <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-snapdragon into next
- Qualcomm RPMh cmd_db_read_slave_id() & cmd_db_read_aux_data()
- Initial Interconnect implementation + Qualcomm RPMh support
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Add Interconnect voting on the UFS probe to ask for the largest
bandwidth possible.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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Add the SM8650 Interconnect nodes definitions, this is heavily based
on the Linux driver without the QoS definitions.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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The Qualcomm SoCs votes for common resources via the RPMh subsystem.
Implement the necessary helpers for Interconnect providers to add the
nodes and vote via the RPPh "BCM" voters, which are vote endpoints for
each SoC subsystems. The APPS (ARM subsystem) has a dedicated endpoint.
The BCM voter will aggregate all the bandwidth for all the nodes
associated with a BCM voter, and internally the RPMh with also
aggregate all the votes from all the SoC subsystems for the same
BCM voter.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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Add a test suite exercising the whole lifetime and callbacks
of interconnect with a fake 5 providers with a split node graph.
The test suite checks the calculus are right and goes to the correct
nodes, and the lifetime of the node is correct.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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Let's introduce the Generic System Interconnect subsystem based on
the counterpart Linux framework which is used to vote for bandwidth
across multiple SoC busses.
Documentation for the Linux Generic System Interconnect Subsystem can
be found at [1].
Each bus endpoints are materialised as "nodes" which are linked together,
and the DT will specify a pair of nodes to enable and set a bandwidth
on the route between those endpoints.
The hardware resources that provide those nodes and provides the way
to vote for the bandwidth are called "providers".
The Interconnect uclass code is heavily based on the Linux one, with
some small differences:
- nodes are allocated as udevices instead of Linux idr_alloc()
- tag management is minimal, only normal xlate is supported
- getting nodes states at probe is not implemented
- providers are probed on demand while the nodes links are traversed
- nodes are populated on bind
- id management is simplified, static IDs and dynamics IDs can be used
- identical consume API as Linux, only implementation differs
Fully tested with associated DM test suite.
[1] https://docs.kernel.org/driver-api/interconnect.html
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-ufs
- Sort again the UFS Kconfig & Makefile
- Use unique name for the rcar-gen5 ufs driver
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
CI: https://source.denx.de/u-boot/custodians/u-boot-microblaze/-/pipelines/28413
AMD/Xilinx/FPGA changes for v2026.01-rc3
- Align brcp1 boot.bin location
- Fix MB-V compilation warning when AXI enet is enabled
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Fix compiler warnings about casting integers to pointers of different
sizes by using uintptr_t as intermediate type. This ensures proper
type conversion across 32-bit and 64-bit architectures.
Signed-off-by: Sai Varun Venkatapuram <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/11b1d9b1a5589d06cff724e807832f366794c075.1762510401.git.michal.simek@amd.com
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We found that some serial console may pull TX line to GROUND during board
boot time. Airoha uses TX line as one of it's BOOT pins. This will lead
to booting in RESERVED boot mode.
It was found that some flashes operates incorrectly in RESERVED mode.
Micron and Skyhigh flashes are definitely affected by the issue,
Winbond flashes are NOT affected.
Details:
--------
DMA reading of odd pages on affected flashes operates incorrectly. Page
reading offset (start of the page) on hardware level is replaced by 0x10.
Thus results in incorrect data reading. Usage of UBI make things even
worse. Any attempt to access UBI leads to ubi damaging. As result OS loading
becomes impossible.
Non-DMA reading is OK.
This patch detects booting in reserved mode, turn off DMA and print big
fat warning.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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The spinand driver do 3 type of dirmap requests:
* read/write whole flash page without oob
(offs = 0, len = page_size)
* read/write whole flash page including oob
(offs = 0, len = page_size + oob_size)
* read/write oob area only
(offs = page_size, len = oob_size)
The trick is:
* read/write a single "sector"
* set a custom sector size equal to offs + len. It's a bit safer to
round up "sector size" value 64.
* set the transfer length equal to custom sector size
And it works!
Thus we can find all data directly from dirmap request, so flash specific
parameters is not needed anymore. Also
* airoha_snand_nfi_config(),
* airoha_snand_nfi_setup()
functions becomes unnecessary.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Set custom sector size equal to flash page size including oob. Thus we
will always read a single sector. The maximum custom sector size is
8187, so all possible flash sector sizes are supported.
This patch is a necessary step to avoid usage of flash specific
parameters.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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REG_SPI_NFI_SECCUS_SIZE registers
This just reduce the number of modification of REG_SPI_NFI_CNFG and
REG_SPI_NFI_SECCUS_SIZE registers during dirmap operation.
This patch is a necessary step to avoid usage of flash specific
parameters.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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spi-airoha-snfi uses custom sector size in REG_SPI_NFI_SECCUS_SIZE
register, so setting of page/oob sizes in REG_SPI_NFI_PAGEFMT is not
required.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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During writing, the entire flash page (including OOB) will be updated
with the values from the temporary buffer, so we need to fill the
untouched areas of the buffer with 0xff value to prevent accidental
data overwriting.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Airoha snfi spi controller supports acceleration of DUAL/QUAD
operations, but does not supports DUAL_IO/QUAD_IO operations.
Luckily DUAL/QUAD operations do the same as DUAL_IO/QUAD_IO ones,
so we can issue corresponding DUAL/QUAD operation instead of
DUAL_IO/QUAD_IO one.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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