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2022-06-25video: stm32: remove test on CONFIG_DM_REGULATORPatrick Delaunay
The tests on CONFIG_DM_REGULATOR, added to avoid compilation issues, can now be removed, they are no more needed since the commit 16cc5ad0b439 ("power: regulator: add dummy helper"). Signed-off-by: Patrick Delaunay <[email protected]>
2022-06-25driver: video: Check allocated pointersBin Meng
The codes that call STBTT_malloc() / stbtt__new_active() do not check the return value at present which may cause segfault. Signed-off-by: Bin Meng <[email protected]>
2022-06-24soc: xilinx: zynqmp: Add machine identification supportStefan Herbrechtsmeier
Add machine identification support based on the zynqmp_get_silicon_idcode_name function and use the soc_get_machine function of the soc uclass to get silicon idcode name for the fpga init. Signed-off-by: Stefan Herbrechtsmeier <[email protected]> Link: https://lore.kernel.org/r/20220620163650.18756-8-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <[email protected]>
2022-06-24soc: xilinx: zynqmp: Remove redundant checks for zynqmp_mmio_readStefan Herbrechtsmeier
Remove the redundant SPL and CurrentEL checks for the zynqmp_mmio_read function call because the function itself runs the same checks. Signed-off-by: Stefan Herbrechtsmeier <[email protected]> Link: https://lore.kernel.org/r/20220620163650.18756-7-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <[email protected]>
2022-06-24firmware: zynqmp: Probe driver before useStefan Herbrechtsmeier
Probe the driver before use to ensure that the driver is always available and the global data are valid. Initialize the global data with zero and probe the driver if the global data are still zero. This allows a usage of the firmware functions from other drivers with arbitrary order between the drivers. Signed-off-by: Stefan Herbrechtsmeier <[email protected]> Link: https://lore.kernel.org/r/20220620163650.18756-2-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <[email protected]>
2022-06-24firmware: zynqmp: Check if rx channel dev pointer is validStefan Herbrechtsmeier
Check if rx channel dev pointer is valid and not if the address of the pointer is valid. Signed-off-by: Stefan Herbrechtsmeier <[email protected]> Link: https://lore.kernel.org/r/20220620163650.18756-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <[email protected]>
2022-06-24microblaze: Convert axi timer to DM driverMichal Simek
Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <[email protected]> Tested-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
2022-06-24cpu: add CPU driver for microblazeOvidiu Panait
Add a basic CPU driver that retrieves information about the microblaze CPU core. cpu_ops handlers are implemented so that the "cpu" command can work properly: U-Boot-mONStR> cpu list 0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000 U-Boot-mONStR> cpu detail 0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000 ID = 0, freq = 50 MHz: L1 cache, MMU Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from linux. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-06-24microblaze: cache: introduce flush_dcache_range()Ovidiu Panait
Align microblaze with the other architectures and provide an implementation for flush_dcache_range(). Also, remove the microblaze exception in drivers/core/device.c. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-06-24cpu-uclass: relocate ops pointers for CONFIG_NEEDS_MANUAL_RELOCOvidiu Panait
Relocate cpu_ops pointers when CONFIG_NEEDS_MANUAL_RELOC is enabled. The (gd->flags & GD_FLG_RELOC) check was added to make sure the reloc_done logic works for drivers that use DM_FLAG_PRE_RELOC. Signed-off-by: Ovidiu Panait <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2022-06-24pinctrl: zynqmp: Add support for output-enable and bias-high-impedanceAshok Reddy Soma
Add support to handle 'output-enable' and 'bias-high-impedance' configurations. DT property output-enable brings out the pins from tri-state, whereas bias-high-impedance changes the pins state to tri-state. Signed-off-by: Ashok Reddy Soma <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/1a02cd41d183d397ebce23c497178281c7286692.1655286745.git.michal.simek@amd.com
2022-06-24serial: Setup serial base and freq for zynq/zynqmpMichal Simek
Setup default values for debug console, base address and frequency. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/ce93efd3ed67aa6390810ce0b79e0d00e7c36b4b.1652871485.git.michal.simek@amd.com
2022-06-24net: xilinx: axi_emaclite: Use shared MDIO bus support for axi emaclite driverT Karthik Reddy
CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy framework. Though if ethernet PHY node is in other ethernet node, it will use shared MDIO to access the PHY of other ethernet. Move ethernet print info statement from plat function to probe function, as phyaddr is not enumerated when CONFIG_DM_ETH_PHY is enabled. Signed-off-by: T Karthik Reddy <[email protected]> Signed-off-by: Michal Simek <[email protected]> Reviewed-by: Ramon Fried <[email protected]> Acked-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/93e11ccca56b6e52b2dcc283d08d5042537f828f.1652181968.git.michal.simek@amd.com
2022-06-24net: xilinx: axi_emac: Use shared MDIO bus support for axi emac driverT Karthik Reddy
CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy framework. Though if ethernet PHY node is in other ethernet node, it will use shared MDIO to access the PHY of other ethernet. Move ethernet print info statement from plat function to probe function, as phyaddr is not enumerated when CONFIG_DM_ETH_PHY is enabled. Signed-off-by: T Karthik Reddy <[email protected]> Signed-off-by: Michal Simek <[email protected]> Reviewed-by: Ramon Fried <[email protected]> Acked-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/ecfec78234233fefdc172c141c207b2d78ef70c5.1652181968.git.michal.simek@amd.com
2022-06-23Merge branch '2022-06-23-scmi-optee-and-smccc-updates' into nextTom Rini
This consists of two slightly related series. For the first, to quote the author: This series implements 2 features in driver/firmware/scmi. First, a single change adds support for SCMI OP-TEE transport to use OP-TEE native shared memory. See the 1st patch in this series: "firmware: scmi: optee: use TEE shared memory for SCMI messages". Then come changes for supporting multi-channel in the SCMI drivers. I've split the implementation in 11 several small incremental changes in the hope it helps the review. Few minor fixup commits are also inserted in the series. And the second series implements some smccc improvements.
2022-06-23drivers: rng: add smccc trng driverEtienne Carriere
Adds random number generator driver using Arm SMCCC TRNG interface to get entropy bytes from secure monitor. The driver registers as an Arm SMCCC feature driver to allow PSCI driver to bind a device for when secure monitor exposes RNG support from Arm SMCCC TRNG interface. Cc: Sughosh Ganu <[email protected]> Cc: Heinrich Schuchardt <[email protected]> Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23firmware: psci: bind arm smccc features when discoveredEtienne Carriere
Use PSCI device to query Arm SMCCC v1.1 support from secure monitor and if so, bind drivers for the SMCCC features that monitor supports. Drivers willing to be bound from Arm SMCCC features discovery can use macro ARM_SMCCC_FEATURE_DRIVER() to register to smccc feature discovery, providing target driver name and a callback function that returns whether or not the SMCCC feature is supported by the system. Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23firmware: psci: reorder header files inclusionEtienne Carriere
Fixes ordering of header files inclusion in PSCI firmware driver. Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23firmware: scmi: use multi channel in mailbox, optee and smccc agentsEtienne Carriere
Updates .process_msg operators of the SCMI transport drivers that supports multi-channel to use it now that drivers do provide the reference through channel argument. These are the mailbox agent, the optee agent and the smccc agent. Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23power: regulator: scmi: simplify scmi_voltd_set_enable()Etienne Carriere
Simplify scmi_voltd_set_enable() exit sequence. Cc: Jaehoon Chung <[email protected]> Signed-off-by: Etienne Carriere <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]>
2022-06-23power: regulator: scmi: support SCMI multi-channelEtienne Carriere
Update SCMI regulator controller driver to get its assigned SCMI channel during initialization. This change allows SCMI voltage domain protocol to use a dedicated channel when defined in the DT. The reference is saved in SCMI regulator controller driver private data. Cc: Jaehoon Chung <[email protected]> Signed-off-by: Etienne Carriere <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]>
2022-06-23reset: scmi: support SCMI multi-channelEtienne Carriere
Update SCMI reset controller driver to get its assigned SCMI channel during initialization. This change allows SCMI reset domain protocol to use a dedicated channel when defined in the DT. The reference is saved in SCMI reset controller driver private data. Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23clk: scmi: support SCMI multi-channelEtienne Carriere
Update SCMI clock driver to get its assigned SCMI channel during initialization. This change allows SCMI clock protocol to use a dedicated channel when defined in the DT. The reference is saved in SCMI clock driver private data. Cc: Lukasz Majewski <[email protected]> Cc: Sean Anderson <[email protected]> Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23firmware: scmi: optee transport: implement multi-channelEtienne Carriere
Implements multi SCMI channel support in OP-TEE SCMI transport. An SCMI protocol may use a dedicated channel, specified by the DT. Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23firmware: scmi: smccc transport: implement multi-channelEtienne Carriere
Updates SCMI SMCCC transport driver to get SCMI channel reference at initialization and use when posting SCMI messages. Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23firmware: scmi: mailbox transport: implement multi-channelEtienne Carriere
Updates SCMI mailbox transport driver to get SCMI channel reference at initialization and use when posting SCMI messages. Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23firmware: scmi: add multi-channel supportEtienne Carriere
Adds resources for SCMI protocols to possibly use a dedicated SCMI channel instead of the default channel allocated by the SCMI agent during initialization. As per DT binding documentation, some SCMI transports can define a specific SCMI communication channel for given SCMI protocols. It allows SCMI protocols to pass messages concurrently each other. This change introduces new scmi agent uclass API function devm_scmi_of_get_channel() for SCMI drivers probe sequences to get a reference to the SCMI channel assigned to its related SCMI protocol. The function queries the channel reference to its SCMI transport driver through new scmi agent uclass operator .of_get_channel that uses Device Tree information from related SCMI agent node. Operator .of_get_channel returns a reference to the SCMI channel assigned to SCMI protocol used by the caller device. SCMI transport drivers that do not support multi-channel are not mandated to register this operator. When so, API function devm_scmi_of_get_channel() returns NULL and SCMI transport driver are expected to retrieve by their own means the reference to the unique SCMI channel, for example using platform data as these drivers currently do in U-Boot source tree. Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23firmware: scmi: factorize scmi transport look upEtienne Carriere
Defines local helper function find_scmi_transport_device() with the instructions to find the SCMI transport device from a SCMI protocol device. Cc: Patrick Delaunay <[email protected]> Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23firmware: scmi: prepare uclass to pass channel referenceEtienne Carriere
Changes SCMI transport operator ::process_msg to pass the SCMI channel reference provided by caller SCMI protocol device. Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23firmware: scmi: prepare scmi uclass API to multi-channelEtienne Carriere
Changes SCMI driver API function devm_scmi_process_msg() to add an SCMI channel reference argument for when SCMI agent supports SCMI protocol specific channels. First argument of devm_scmi_process_msg() is also change to point to the caller SCMI protocol device rather than its parent device (the SCMI agent device). The argument is a pointer to opaque struct scmi_channel known from the SCMI transport drivers. It is currently unused and caller a pass NULL value. A later change will enable such support once SCMI protocol drivers have means to get the channel reference during initialization. Cc: Lukasz Majewski <[email protected]> Cc: Sean Anderson <[email protected]> Cc: Jaehoon Chung <[email protected]> Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23firmware: scmi: optee: fix inline description of PTA_SCMI_CMD_GET_CHANNELEtienne Carriere
Removes inaccurate inline description of OP-TEE SCMI PTA command PTA_SCMI_CMD_GET_CHANNEL. Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23firmware: scmi: optee: use TEE shared memory for SCMI messagesEtienne Carriere
Changes implementation when using TEE dynamically allocated shared memory to synchronize with the Linux implementation where the legacy SMT protocol cannot be used with such memory since it is expected from device mapped memory whereas OP-TEE shared memory is cached and hence should not be accessed using memcpy_toio()/memcpy_fromio(). This change implements the MSG shared memory protocol introduced in Linux [1]. The protocol uses a simplified SMT header of 32bit named MSG_SMT to carry SCMI protocol information and uses side channel means to carry exchanged buffer size information, as TEE invocation API parameters when used in the SCMI OP-TEE transport. Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f301bba0ca7392d16a6ea4f1d264a91f1fadea1a Signed-off-by: Etienne Carriere <[email protected]>
2022-06-23sandbox: Implement fuzzing engine driverAndrew Scull
Add a fuzzing engine driver for the sandbox to take inputs from libfuzzer and expose them to the fuzz tests. Signed-off-by: Andrew Scull <[email protected]>
2022-06-23fuzzing_engine: Add fuzzing engine uclassAndrew Scull
This new class of device will provide fuzzing inputs from a fuzzing engine. Signed-off-by: Andrew Scull <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2022-06-23serial: sandbox: Fix buffer underflow in putsAndrew Scull
Fix the buffer underflow that would occur if puts is called with length of zero. Fixes: efa51f2bd64 ("serial: sandbox: Implement puts") Cc: Sean Anderson <[email protected]> Cc: Simon Glass <[email protected]> Reviewed-by: Sean Anderson <[email protected]>
2022-06-23arm: apple: nvme: Add SART support and RTKit buffer managementJanne Grunau
The NVMe firmware in the macOS 13 beta blocks or crashes with u-boot's current minimal RTKit implementation. It does not provide buffers for the firmware's buffer requests. The ANS2 firmware included in macOS 11 and 12 tolerates this. The firmware included in the first macOS 13 beta requires buffers for the crashlog and ioreport endpoints to function. In the case of the NVMe the buffers are physical memory. Access to physical memory is guarded by what Apple calls SART. Import m1n1's SART driver (exclusively used for the NVMe controller). Implement buffer management helpers for RTKit. These are generic since other devices (none in u-boot so far) require different handling. Signed-off-by: Janne Grunau <[email protected]> Reviewed-by: Mark Kettenis <[email protected]> Tested-by: Mark Kettenis <[email protected]>
2022-06-22misc: nuvoton: Add NPCM7xx otp controller driverJim Liu
Add Nuvoton BMC npcm750 otp driver Signed-off-by: Jim Liu <[email protected]>
2022-06-22crypto: nuvoton: Add NPCM7xx SHA driverJim Liu
add nuvoton BMC npcm750 SHA driver Signed-off-by: Jim Liu <[email protected]>
2022-06-22crypto: nuvoton: Add NPCM7xx AES driverJim Liu
add nuvoton BMC npcm750 AES driver Signed-off-by: Jim Liu <[email protected]>
2022-06-22spi: gxp_spi: Add GXP SPI controller driverNick Hawkins
The GXP supports 3 separate SPI interfaces to accommodate the system flash, core flash, and other functions. The SPI engine supports variable clock frequency, selectable 3-byte or 4-byte addressing and a configurable x1, x2, and x4 command/address/data modes. The memory buffer for reading and writing ranges between 256 bytes and 8KB. This driver supports access to the core flash. Signed-off-by: Nick Hawkins <[email protected]>
2022-06-22timer: gxp: Add HPE GXP timer supportNick Hawkins
Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <[email protected]>
2022-06-20Merge branch 'master' into nextTom Rini
Merge in v2022.07-rc5.
2022-06-20Merge tag 'u-boot-stm32-20220620' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-stm into next - Add STM32MP13 SoCs support with associated board STM32M135F-DK - Correct livetree support in stm32mp1 boards - Activate livetree for stm32mp15 DHSOM boards
2022-06-20mmc: fsl_esdhc: Add new config option for default fallback modePali Rohár
Currently default fallback SDHC mode is 1-bit. Add new config option CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH to allow specifying default fallback mode. This is useful e.g. for SPL builds which loads other parts from SD card during boot process. Signed-off-by: Pali Rohár <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]>
2022-06-20mmc: fsl_esdhc: Set fallback mode to 1-bitPali Rohár
8-bit mode is not supported by SD cards and on P2020 are four SDHC pins shared with SPI (so if P2020 board have also SPI then only 4-bit SDHC mode is provided). So 8-bit SDHC mode is really bad default. When max bus width is not provided then set mode to 1-bit. This mode is supported by all cards, so it is the best option for fallback mode. Also P2020 bootrom sets mode to 1-bit when booting from SD/MMC card. Signed-off-by: Pali Rohár <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]>
2022-06-20mtd: rawnand: fsl_elbc: Fix DM support in DTS code pathPali Rohár
For proper DM support it is required to fill also mtd->dev member. Otherwise DM would not see nand device at all. Signed-off-by: Pali Rohár <[email protected]>
2022-06-20arm: layerscape: Add sfp driverSean Anderson
This adds a driver for the Security Fuse Processor (SFP) present on LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and other "security" related fuses. Similar devices (sharing the same name) are present on other processors, but for the moment this just supports the LS2 variants. The mirror registers are loaded during power-on reset. All mirror registers must be programmed or read at once. Because of this, `fuse prog` will program all fuses, even though only one might be specified. To prevent accidentally burning through all your fuse programming cycles with something like `fuse prog 0 0 A B C D`, we limit ourselves to one programming cycle per reset. Fuses are numbered based on their address. The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc. The TA_PROG_SFP supply must be enabled when programming fuses, but must be disabled when reading them. Typically this supply is enabled by inserting a jumper or by setting a register in the board's FPGA. I've also added support for using a regulator. This could be helpful for automatically issuing the FPGA write, or for toggling a GPIO controlling the supply. I suggest using the following procedure for programming: 1. Override the fuses you wish to program => fuse override 0 2 A B C D 2. Inspect the values and ensure that they are what you expect => fuse sense 0 2 4 3. Enable TA_PROG_SFP 4. Issue a program command using OSPR0 as a dummy. Since it contains the write-protect bit you will usually want to write it last anyway. => fuse prog 0 0 0 5. Disable TA_PROG_SFP 6. Read back the fuses and ensure they are correct => fuse read 0 2 4 Signed-off-by: Sean Anderson <[email protected]>
2022-06-17Merge commit '32e0379143b433e29d76404f5f4c279067e48853' of ↵Tom Rini
https://github.com/tienfong/uboot_mainline
2022-06-17stm32mp1: fix reference for STMicroelectronicsPatrick Delaunay
Replace reference to the correct name STMicroelectronics Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Heiko Schocher <[email protected]> Reviewed-by: Patrice Chotard <[email protected]>
2022-06-17misc: stm32mp13: introduce STM32MP13 RCC driverPatrick Delaunay
Add the MISC RCC driver for STM32MP13, and bind it to the RCC reset driver, required for initial support. Signed-off-by: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]> Acked-by: Sean Anderson <[email protected]> Change-Id: Ida11c15462caf140f87b1e3239efa2b8a689acb9
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