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In some cases two devices are related and the only way to tell is to
check that the names partially patch. Add a way to check this without
needing to create a new string for the comparison.
Fix the comment for device_find_child_by_namelen() while we are here.
Signed-off-by: Simon Glass <[email protected]>
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It seems that namelen is more common in U-Boot. Rename this function to
fit in better. Also fix a bug where it breaks the operation of
uclass_get_by_name() and add a test.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Patrick Delaunay <[email protected]>
Reported-by: Tim Harvey <[email protected]>
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Add support for the SARADC variant found on the AXG SoCs family.
Signed-off-by: Vyacheslav Bocharov <[email protected]>
Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Update g12a-ao clk driver:
- move clk->id check to .request function
- remove unnecessary check (gate->reg == 0)
Signed-off-by: Vyacheslav Bocharov <[email protected]>
Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Update the clk-g12a-ao driver from "axg" to "g12a"
Signed-off-by: Vyacheslav Bocharov <[email protected]>
Acked-by: Neil Armstrong <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add minimal driver AO clocks on meson AXG family. Only ADC related clocks
are supported.
Signed-off-by: Vyacheslav Bocharov <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Now that all the block device drivers have enable a probe hook, we will
call part_create_block_devices() to enumerate all the partitions and
create associated udevices when a block device is detected.
Signed-off-by: AKASHI Takahiro <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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ENOMEM is a more common error code for memory starvation.
Signed-off-by: AKASHI Takahiro <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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If dev_count_phandle_with_args returns 0 or another error, then pd will never
have been initialized by power_domain_get_by_index. Avoid comparing against
pd.dev in this situation.
Fixes: 3e4fcfa4bc ("power-domain: fix hang in endless loop on i.MX8")
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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- device-tree-bindings: watchdog: document common properties (Philippe)
- nuvoton: Add support for Nuvoton (Jim)
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20220422
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- Switch to DM_SERIAL
- Drop MMCROOT
- several cleanup
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/11815
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Reviewed-by: Ramon Fried <[email protected]>
Signed-off-by: Oleksii Titov <[email protected]>
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When usb3-phy label is found, PHY driver is called and serdes line is
initialized. This is preparation for serdes/psgtr driver to configure GT
lines based on description in DT.
Signed-off-by: Michal Simek <[email protected]>
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ci_udc_ops and ci_ep_ops do not change their operations.
Mark them as const.
Signed-off-by: Adam Ford <[email protected]>
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Add watchdog controller driver for NPCM7xx/npcm8xx
the wdt design of npcm750 and npcm845 is the same.
so the driver can work on npcm750 and npcm845.
about npcm845 wdt dtsi i will followed kernel dts name
to use nuvoton,npcm750-wdt.
Signed-off-by: Jim Liu <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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ATSHA204A uses bit-reversed checksum of standard CRC-16 with polynomial
x^16 + x^15 + x^2 + 1.
This ATSHA204A specific checksum can be calculated just by using common
U-Boot functions bitrev16() and crc16().
So replace custom driver CRC-16 implementation by common U-Boot functions.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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HW accelerated hash operations are giving incorrect hash output.
so invalidate cache lines to avoid cache overwriting in DDR memory region.
caam_hash()
-moved address alignment check in the beginning of function.
-added invalidate_dcache_range for pout buffer before running descriptor.
Fixes: d7af2baa49 (crypto/fsl: Fix HW accelerated hash commands)
Signed-off-by: Gaurav Jain <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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issue: blob decapsulation operation store the decrypted data
in memory even if ICV check failed.
fix: clear the blob data output memory.
Fixes: c5de15cbc8 (crypto/fsl: Add command for encapsulating/decapsulating blobs)
Signed-off-by: Gaurav Jain <[email protected]>
Reviewed-by: Kshitiz Varshney <[email protected]>
Tested-by: Kshitiz Varshney <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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There are no users of the imx6_pcie_toggle_power and imx6_pcie_toggle_reset
weak overrides and as these functions are able to be handled now via dt
properties lets remove these.
Cc: Marek Vasut <[email protected]>
Signed-off-by: Tim Harvey <[email protected]>
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If vpcie-supply is defined by device-tree use that if
CONFIG_PCIE_IMX_POWER_GPIO is not defined.
Note that after this the following boards which define
CONFIG_PCIE_IMX_POWER_GPIO in their board header file as well as their
device-tree should be able to remove CONFIG_PCIE_IMX_PERST_GPIO without
consequence:
- mx6sabresd
- mx6sxsabresd
- novena
Note that the ge_bx50v3 board uses CONFIG_PCIE_IMX_POWER_GPIO and does
not have vpcie-supply defined in it's pcie node in the dt thus removing
CONFIG_PCIE_IMX_POWER_GPIO globally can't be done until that board adds
vpcie-supply.
Cc: Ian Ray <[email protected]> (maintainer:GE BX50V3 BOARD)
Cc: Sebastian Reichel <[email protected]> (maintainer:GE BX50V3 BOARD)
Cc: Fabio Estevam <[email protected]> (maintainer:MX6SABRESD BOARD)
Cc: Marek Vasut <[email protected]> (maintainer:NOVENA BOARD)
Signed-off-by: Tim Harvey <[email protected]>
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The i.MX8MP glue needs to be configured based on a couple of DT
properties, implement .glue_configure callback to parse those DT
properties and configure the glue accordingly.
Tested-By: Tim Harvey <[email protected]> #imx8mp-venice-gw74xx
Signed-off-by: Marek Vasut <[email protected]>
Cc: Angus Ainslie <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Kunihiko Hayashi <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Rename the select_dr_mode callback to glue_configure, the callback is
used for more than enforcing controller mode even on the TI chips, so
change the name to a more generic one. No functional change.
Tested-By: Tim Harvey <[email protected]> #imx8mp-venice-gw74xx
Signed-off-by: Marek Vasut <[email protected]>
Cc: Angus Ainslie <[email protected]>
Cc: Bin Meng <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Kunihiko Hayashi <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add trivial driver for i.MX8MP HSIOMIX handling. This is responsible
for enabling the GPCv2 power domains and clock for USB 3.0 and PCIe
in the correct order. Currently supported is the USB 3.0 part which
can be tested, PCIe support should be easy to add.
Tested-By: Tim Harvey <[email protected]> #imx8mp-venice-gw74xx
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add i.MX8MP power domain handling into the driver. This is based on the
Linux GPCv2 driver state which is soon to be in Linux next.
Tested-By: Tim Harvey <[email protected]> #imx8mp-venice-gw74xx
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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Implement power_domain_get_by_name() convenience function which parses
DT property 'power-domain-names' and looks up power domain by matching
name.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: Simon Glass <[email protected]>
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This driver is the only SMCCC dependency in iMX8M U-Boot port. Rework
the driver based on Linux GPCv2 driver to directly control the GPCv2
block instead of using SMCCC calls. This way, U-Boot can operate the
i.MX8M power domains without depending on anything else.
This is losely based on Linux GPCv2 driver. The GPU, VPU, MIPI power
domains are not supported to save space, since they are not useful in
the bootloader. The only domains kept are ones for HSIO, PCIe, USB.
Tested-By: Tim Harvey <[email protected]> #imx8mp-venice-defconfig
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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The arch/arm/include/asm/arch-imx8m/power-domain.h is not included
anywhere except in drivers/power/domain/imx8m-power-domain.c, just
inline the content and drop the header. No functional change.
Tested-By: Tim Harvey <[email protected]> #imx8mp-venice-defconfig
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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In case the power domain node structure is gpc@303a0000/pgc/power-domain@N,
do not bind power domain driver to the 'pgc' node, but rather descend into
it and only bind power domain drivers to power-domain@N subnodes. This way
we do not waste one useless driver instance associated with 'pgc' node.
Tested-By: Tim Harvey <[email protected]> #imx8mp-venice-defconfig
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
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In case the ops is not implemented, return 0 in the core right away.
This is better than having multiple copies of functions which just
return 0 in each power domain driver. Drop all those empty functions.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: Simon Glass <[email protected]>
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Add support for handling SFP TX disable for MVNETA in the same fashion as
to what MVPP2 is doing in order to enable using SFP-s.
This allows using ethernet on SFP only boards.
Signed-off-by: Robert Marko <[email protected]>
Reviewed-by: Marek Behún <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR
frequency that is set for lpddr4 before initialization of the
controller. Make this optional and continue to use PLL bypass frequency
as is done currently if ti,ddr-freq0 is not provided.
Signed-off-by: Dave Gerlach <[email protected]>
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The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect
the maximum possible SDRAM of 2 GB for AM64x (instead of the register's
default that says 8 GB, which the AM64x DDR controller wouldn't support).
The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG
was that of the next register at offset 0x24.
Signed-off-by: Dominic Rath <[email protected]>
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The offset of the current read back register is the value of the gpio pin,
not the value written for the gpio output.
This patch fix it to avoid the other gpio output value controlled by the
same register being set incorrectly.
Fixes: 7ad889b0f37a ("gpio: Add Aspeed GPIO driver")
Signed-off-by: Billy Tsai <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add rk3066 SoC support;
- Add rk3066 MK808 board support;
- dts sync from kernel for rk322x, rk3288;
- some other board level config update;
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When every member of a linker list is aligned by the compiler, we can no
longer rely on the sizeof of the struct to determine the number of
entries.
For example, if the struct size is 0x90 but every entry is aligned to 0xa0
by the compiler, the linker list entries takes more space in memory and
the calculation of the number of entries is incorrect. For example, we may
see 0x12 entries when there are only 0x11.
This is a real problem. There may be a general solution, although I cannot
currently think of one. So far it only bites with OF_PLATDATA_RT which
creates a pointer to each entry of the 'struct udevice' linker_list. This
does not happen without that option, so it only affects SPL.
Work around it by manually calculating the aligned size of struct udevice,
then using that for the n_ent calculation.
Note: the alignment fix to linker list was here:
0b2fa98aa5e linker_lists: Fix alignment issue
Signed-off-by: Simon Glass <[email protected]>
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At present if devres is enabled in U-Boot proper it is enabled in SPL.
We don't normally want it there, so disable it.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Angus Ainslie <[email protected]>
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The rk3288/RK3399 DT synced from Linux contains some different
compatible strings in the mipi node then origanal used in U-boot.
Allow both options to be backwards compatible and to be able
to handle recent rk3288.dtsi and rk3399.dtsi files.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The rk3288 DT synced from Linux contains some different
properties in the edp node then origanal used in U-boot.
Allow both options to be backwards compatible and to be able
to handle recent rk3288.dtsi files.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add rockchip rk3066 sdram driver
Signed-off-by: Paweł Jarosz <[email protected]>
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add driver supporting pin multiplexing on rk3066 platform.
Signed-off-by: Paweł Jarosz <[email protected]>
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add the clock driver for the rk3066 platform.
Derived from the rk3288 and rk3188 driver it
supports only a bare minimum to bring up the system
to reduce the TPL size for:
SDRAM clock configuration.
The boot devices NAND, EMMC, SDMMC, SPI.
A UART for the debug messages (fixed) at 115200n8.
A SARADC for the recovery button.
A TIMER for the delays (fixed).
There's support for two possible frequencies,
the safe 600MHz which will work with default pmic settings and
will be set to get away from the 24MHz default and
the maximum of 1.416Ghz, which boards can set if they
were able to get pmic support for it.
After the clock tree is set during the TPL probe
there's no parent update support.
In OF_REAL mode the drivers ns16550.c and dw-apb-timer.c
obtain the (fixed) clk_get_rate from the clock driver
instead of platdata.
The rk3066 cru node has a number of assigned-clocks properties
that call the .set_rate() function. Add them to the list so that
they return a 0 instead of -ENOENT.
Signed-off-by: Paweł Jarosz <[email protected]>
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The serial_rockchip.c driver converts platdata to the data structure
used in the ns16550.c file and then calls the function
ns16550_serial_probe().
When compiled with OF_REAL the serial_rockchip.c driver returns
now -ENODEV when probed and does no harm.
The config ROCKCHIP_SERIAL is currently depends on SPL_OF_PLATDATA.
Allow serial port use for both SPL and TPL by removing this
dependency and SPL_BUILD restriction.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The Rockchip serial driver depends on an enabled NS16550 driver,
so add select SYS_NS16550 to config ROCKCHIP_SERIAL.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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When a defconfig for rk3288 is compiled it gives the warning:
rockchip_rk3288_uart: Missing .compatible in
./drivers/serial/serial_rockchip.c
: WARNING: the driver rockchip_rk3288_uart
was not found in the driver list
Fix by renaming U_BOOT_DRIVER name of serial_rockchip.c
to rockchip_uart. Add rk3288 serial support with
a DM_DRIVER_ALIAS define.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The Rockchip uart DT nodes have "snps,dw-apb-uart" as
fall back string. The driver ns16550.c has CONFIG_IS_ENABLED(OF_REAL)
as condition to of_match and does not copy dtplat data.
For TPL/SPL the driver serial_rockchip.c
is used. Move driver alias to correct driver.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The ns16550.c driver has the following conditions for .of_match:
CONFIG_IS_ENABLED(OF_REAL)
For Rockchip SoCs with TPL/SPL and platform data that need serial
support the serial_rockchip.c driver was made. It copies this data
and then calls ns16550_serial_probe(). With the addition of yet an other
SoC type this driver is in need for a little restyle.
Simplify struct rockchip_uart_plat and add extra SoCs with
DM_DRIVER_ALIAS(). Return -ENODEV when the ns16550.c driver
probe function is available.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The Rockchip SoCs rk3066/rk3188 have MMC DT nodes
with as compatible string "rockchip,rk2928-dw-mshc".
Add OF_PLATDATA support to the existing driver with
help of a DM_DRIVER_ALIAS.
This type needs a permanent enabled fifo.
The other Rockchip SoCs always have the property
"u-boot,spl-fifo-mode" in the MMC DT nodes,
because MMC to SRAM can't do DMA.
Make this property a requirement for MMC OF_PLATDATA
structures. The property "fifo-mode" must be added
for all other compile modes.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The document rockchip-dw-mshc.yaml decribes a maximum of 4 clocks.
In the rockchip_dw_mmc driver the clock name in use was "fixed"
to "ciu" with index 1, but later reverted back to index 0.
The clock drivers can handle both, but the calling driver
should submit correct data as a standard practice.
Fix the "ciu" clock index by setting it back to 1.
clock-names:
minItems: 2
items:
- const: biu
- const: ciu
- const: ciu-drive
- const: ciu-sample
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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