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Fix Kconfig entry indent to be always consistently indented with
leading tabs, never with leading spaces. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Add support for the GPIO controller block in the R-Car Gen5 SoC family.
The GPIO controller has a General Input Enable Register (INEN), whose
reset state is to have all input disabled. The GPIO controller also has
updated offsets for its control registers. U-Boot uses three registers,
INDT, POSNEG, INEN, which have updated offsets, those are handled by the
driver.
Signed-off-by: Huy Bui <[email protected]>
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
[Marek: - Access Gen5 specific registers via driver data offsets,
- Update commit message]
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The Renesas R-Car Gen5 GPIO controller has INDT, POSNEG, INEN registers
at different offsets compared to previous generations. Introduce three
new entries in struct rcar_gpio_data {} match data to describe these
register offsets for each GPIO controller. Update the driver to access
these three registers through the match data offsets. No functional
change.
Signed-off-by: Marek Vasut <[email protected]>
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Wrap the RCAR_GPIO_HAS_INEN quirk in more flexible struct rcar_gpio_data {}
in preparation for addition of Renesas R-Car Gen5 GPIO controller support.
The Renesas R-Car Gen5 GPIO controller requires more than a single quirk
to properly describe it, therefore increase the flexibility and introduce
full match data structure, and use it throughout the driver. No functional
change.
Signed-off-by: Marek Vasut <[email protected]>
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Remove register macros for registers which are not used by this driver.
This makes it easier to get an overview of which registers are really
used by the driver. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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The PFC offset is no longer used directly in the driver since commit
fbf26bea3964 ("gpio: renesas: Migrate to pinctrl GPIO accessors")
Drop the pfc_offset parsing.
Fixes: fbf26bea3964 ("gpio: renesas: Migrate to pinctrl GPIO accessors")
Signed-off-by: Marek Vasut <[email protected]>
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Add PHY driver for Multi-Protocol PHY present on Renesas R-Car X5H
R8A78000 SoC. Currently, the PHY driver only supports configuring
the MPPHY for ethernet operation.
Signed-off-by: Thanh Quan <[email protected]>
Signed-off-by: Phong Hoang <[email protected]>
Signed-off-by: Hai Pham <[email protected]> #Fix License-Identifier
Signed-off-by: Marek Vasut <[email protected]>
[Marek: Clean up macros, indent, clock and reset handling in probe,
rename the driver and add r8a78000- into compatible string,
update commit message.]
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Add support for the Ethernet Physical Coding Sublayer (PCS) controller
on R-Car Gen5 SoCs, specifically the Renesas R-Car X5H R8A78000.
The controller is based on the SERDES infrastructure used in previous
R-Car generations, with updates for Gen5 register layout and features.
Because majority of this driver is SoC-specific register programming,
the majority of this driver is different enough from R8A779F0 SerDes
driver to justify its own driver. Deduplication of the remaining bits
of code does not yield any improvement.
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Phong Hoang <[email protected]>
Signed-off-by: Tam Nguyen <[email protected]>
Signed-off-by: Thanh Quan <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
[Marek: Add missing clk_bulk_disable() in fail path.
Drop always-true aneg_on setting.
Reduce poll delay from 100s to 100ms.
Use bulk reset operations to finalize reset handling.]
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Add support for the Renesas Ethernet Switch3 (RSW3) controller,
present in R-Car Gen5 SoCs such as R-Car X5H (R8A78000). The
hardware offset differences are handled via driver match data.
The driver newly detects whether the switch prot is connected
to xPCS or not, and if so, turns on MIOC bit 3. This is new on
R-Car X5H. GWCKSC register is also programmed only on X5H. The
rest of the operation is identical to RSwitch2.
Signed-off-by: Marek Vasut <[email protected]>
Signed-off-by: Tam Nguyen <[email protected]>
Signed-off-by: Phong Hoang <[email protected]>
Signed-off-by: Thanh Quan <[email protected]>
Signed-off-by: Hai Pham <[email protected]>
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The MPIC_MDC_CLK clock setting value differs between R-Car S4
and R-Car X5H. Parametrize the value in preparation for R-Car
X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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The GWDCBAC0, GWDCBAC1, FWPBFCSDC, CABPIRM register offsets changed
between R-Car S4 and R-Car X5H. Parametrize their offsets in preparation
for R-Car X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Inline FWRO, CARO, GWRO, TARO, RMRO macros directly into the
follow up register macros. FWRO, CARO, GWRO, TARO are already
zero, drop them. RMRO is 0x1000, increment all registers which
add RMRO by 0x1000 directly. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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The forwarding engine CSD register offset changed between the
R-Car S4 and R-Car X5H. Parametrize this offset in preparation
for R-Car X5H addition into this driver. Clean up the macro
parameter names and make them more obvious. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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The total port counts differ across variants of this IP in
R-Car S4 and R-Car X5H. Parametrize port count in preparation
for R-Car X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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The COMA, ETHA, GWCA offsets differ across variants of this IP in
R-Car S4 and R-Car X5H. Parametrize these offsets in preparation
for R-Car X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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This IP does support operating MII and SerDes via different ports.
Currently, the driver assumes that MII and SerDes are always bound
together on the same port, but this may not be the case. Implement
support for controlling MII and SerDes separately.
While the change is extensive, the gist of the change is to pass
pointer to the selected port registers to MII or SerDes functions,
depending on which port and operations should be done on that port.
Each combined ETHA instance contains both MII and SerDes register
pointers, which may not point to the same port, and passes those
registers to MII and SerDes functions respectively to control the
MII or SerDes of each port.
Signed-off-by: Marek Vasut <[email protected]>
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The new version of RSwitch3 in Renesas R-Car Gen5 uses multiple
clock to supply the IP. Convert the driver to bulk clock API to
cater for both single clock of R-Car S4 and multiple clock of
R-Car Gen5. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Empty RX DMA descriptor must contain .die_dt field set to DT_FEMPTY,
because hardware DMA overwrites this field to non-DT_FEMPTY when data
are received, and the .recv callback tests the content of RX descriptor
.die_dt field to determine whether hardware did receive any data and
updated the .die_dt field, and based on that information, receives a
packet or not. Fix the incorrect RX DMA descriptor initialization to
assure the .recv callback always works correctly.
Signed-off-by: Marek Vasut <[email protected]>
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Remove macros which are not used in the driver. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Fix indent from multiple spaces to tabs, to be consistent with
coding style and the rest of the driver. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Rockchip boards may depend on a working MMC regulator in SPL to
successfully load FIT payload from MMC. Typically, these boards only
include the vmmc-supply regulator and not its vin-supply in SPL control
FDT.
The commit f98d812e5353 ("power: regulator: Add vin-supply for GPIO and
Fixed regulators") breaks loading FIT from MMC in SPL on some of these
boards due to now requiring the vin-supply to be included in the SPL
control FDT.
The commit also strangely enables any found vin-supply in
regulator_common_of_to_plat() and not when a regulator is enabled or as
part of regulator_autoset().
Revert the commit to fix FIT loading in SPL on broken boards.
If a board needs to have its vin-supply enabled, two options come to
mind:
- Add regulator-always-on prop to the regulator in the -u-boot.dtsi for
any board.
- Implement full support for reference counting of regulators and then
update the regulator-uclass to enable any found vin-supply when a
regulator is enabled.
This reverts commit f98d812e5353408ef77a46bad1f1cdc793ff8a03.
Reported-by: Dang Huynh <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Dragan Simic <[email protected]>
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If CONFIG_GPIO_HOG is not set, then gpio_hog_lookup_name() is empty,
and thus does not initialize any of its parameters. It does still
return 0 though, and so any calling function might assume that the
parameters have been initialized successfully.
Change the return value to -ENODEV in this case, as the function
would in the case when CONFIG_GPIO_HOG is set but the gpio hog
could not be found.
Signed-off-by: Wolfgang Wallner <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Introduces support for Device Firmware Upgrade (DFU) over PCIe in
U-Boot. Traditionally, the DFU protocol is used over USB, where a
device enters DFU mode and allows a host to upload firmware or binary
images directly via the USB interface. This is a widely adopted and
convenient method for updating firmware.
In the context of Texas Instruments (TI) SoCs, PCIe can be used as a
boot interface in a manner that differs from the conventional
"PCIe Boot" process, which typically refers to booting an OS or
firmware image from an NVMe SSD or other PCIe-attached storage devices.
Instead, TI SoCs can be configured as a PCIe Endpoint, allowing a
connected PCIe Root Complex (host) to transfer images directly into the
device’s memory over the PCIe bus for boot purposes. This mechanism is
analogous to DFU over USB, but leverages the high-speed PCIe link and
does not depend on traditional storage devices.
By extending the DFU framework in U-Boot to support PCIe, it will be
possible to flash images over PCIe. While this implementation is
motivated by TI SoC use cases, the framework is generic and can be
adopted by everyone for platforms that support PCIe Endpoint mode.
Platforms with hardware support for PCIe-based memory loading can use
this to implement PCIe as a boot mode, as well as to enable flashing
and recovery scenarios similar to DFU over USB.
In summary, enable support for:
- DFU-style flashing of firmware/images over PCIe, analogous to existing
USB DFU workflows
- PCIe as a boot mode where a host can load images directly into device
memory using DFU over PCIe
Signed-off-by: Hrushikesh Salunke <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/28144
- Extend USB support for the i.MX9 family.
- Update memory controller for imx6ulz_smm_m2.
- Add remoteproc support for several i.MX boards.
- Add support for iMX95 15x15 EVK.
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Introduce remote processor configuration for the i.MX93 Cortex-M33 core.
This patch adds:
- Address translation table (ATT) for i.MX93, including TCM
(secure and non-secure) and DDR regions.
- A new device configuration structure `imx_rproc_cfg_imx93` using SMC
method and ARM SMC ops.
- Device tree match entry for "fsl,imx93-cm33"
This enables remoteproc framework to properly initialize and manage the
Cortex-M33 core on i.MX93 platforms.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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i.MX8MQ/M use MMIO based method to directly configure SRC registers
to start/stop M4.
Add mmio ops to start/stop/is_running.
Add i.MX8MQ cfg data, i.MX8MN reuses i.MX8MQ data.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Support i.MX8MP/N with start/stop/device_to_virt/is_running/load
implemented. The device static configuration is mostly reused from
Linux Kernel with adapation to U-Boot dm_rproc_ops.
The booting method:
- load mmc 2:2 0x90000000 /lib/firmware/imx8mp_m7_DDR_rpmsg_lite_str_echo_
rtos.elf
- rproc load 0 0x90000000 ${filesize}
- rproc start 0
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Some areas needs to be initialized by using memcpy_toio and memset_io.
Following Linux Kernel commit: 40df0a91b2a5 ("remoteproc: add is_iomem to
da_to_va"), add this to U-Boot.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add support for the optional 'phy-supply' property in the ENETC MDIO
driver. This allows the driver to enable and manage the PHY's power
supply via the regulator framework when specified in device tree.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
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Extend the NETC block control driver to support the i.MX94 SoC.
Acked-by: Peng Fan <[email protected]>
Reviewed-by: Jacky Bai <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
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USB3.0 PHY
This patch adds SPL Kconfig option (SPL_PHY_IMX8MQ_USB) for the i.MX8MQ,
i.MX8MP, i.MX95, and i.MX94 USB3.0 PHY driver, allowing the driver to be
compiled and probed in SPL stage.
Signed-off-by: Alice Guo <[email protected]>
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Since PQC container has changed version to 0x2 in container header,
update the header's check.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Acked-by: Peng Fan <[email protected]>
Reviewed-by: Jacky Bai <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
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Since the EHCI USB driver is shared across i.MX91, i.MX93, i.MX94, and
i.MX95, the condition check is updated to use IMX9.
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Typos found via codespell utility.
Signed-off-by: Yegor Yefremov <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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If OF_CONTROL is on, ti-musb.c registers a "ti-musb-wrapper" driver
that requires UCLASS_MISC. Hence, select MISC if both OF_CONTROL
and USB_MUSB_TI are selected.
Signed-off-by: Yegor Yefremov <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/28119
- New Boards support:
rk3588: MNT Reform2
rk3528: Radxa ROCK 2A/2F
rk3576: ArmSoM Sige1, Luckfox Omni3576, FriendlyElec NanoPi M5,
Radxa ROCK 4D
rk3568: Lunzn FastRhino R66S
- Other board level updates.
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eMMC erase and write support on RK3528 is somewhat unreliable, sometime
e.g. mmc erase and write commands will fail with an error.
Use the delay line lock value for half card clock cycle, DLL_LOCK_VALUE,
to set a manual xx_TAP_VALUE to fix the unreliable eMMC support.
This is only enabled for RK3528, remaining SoCs still use the automatic
tap value, (DLL_LOCK_VALUE * 2) % 256, same value we configure manually
for RK3528.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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SFC after version 8 supports dtr mode, so the IO is the binary output of
the controller clock.
Signed-off-by: Jon Lin <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add dummy implementation of set_rate for SCLK_GPU and SCLK_WIFI_PMU to
allow use of dts/upstream assigned-clocks in cru and pmucru nodes.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/28092
- Fix a i.MX6ULL regression related to the REFTOP_VBGADJ setting.
- Shrink SPL size for the Liebherr BTT board.
- Add suppot for Toradex SMARC iMX95.
- Fix Aquila imx95 0098 Product ID.
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ti-sysc.c includes clk.h and requires its functionality to
manage clocks.
Signed-off-by: Yegor Yefremov <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-snapdragon
A variety of Qualcomm features/fixes for this cycle, notably with a few
new platforms gaining support:
* Initial support for SDM670 (similar to SDM845), SM6350, and SM7150
platforms is added
* USB and UART issues on MSM8916 are addressed (improving stability/
reliability)
* Firmware loading is implemented for the GENI serial engine, this is
used on some platforms to load firmware for i2c/spi/uart to work
Some additional patches like binman support for building MBN files still
need some additional work.
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/8ef6ac07b35e39a57501554680bbf452e818d3e3/pipelines?ref=qcom-main
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Currently vendor/product id are both 0, and that might not as we want.
Set to some arbitrary known value that we can make it work more smoothly.
Reviewed-by: Mattijs Korpershoek <[email protected]>
Acked-by: Mattijs Korpershoek <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: George Chan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add basic compatible string for sc7180 family soc.
Signed-off-by: Vitalii Skorkin <[email protected]>
Co-developed-by: George Chan <[email protected]>
Signed-off-by: George Chan <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The UCLASS_USB device is removed and rebound each time you run "usb stop"
followed by "usb start", or when you switch between USB device and USB host
mode. Unfortunately, this causes issues with the current ehci-msm driver:
In ehci_usb_remove() we call generic_shutdown_phy(), but at that point the
ULPI PHY we registered in ehci_usb_of_bind() was already removed again by
the DM core.
Fix this by adding a UCLASS_NOP driver that keeps the PHY driver bound
permanently, and then just re-probe the actual USB part.
Reported-by: Jianfeng Zhu <[email protected]>
Closes: https://lore.kernel.org/u-boot/OSQPR04MB774067EBEEADD714EFE18C2A90882@OSQPR04MB7740.apcprd04.prod.outlook.com/
Signed-off-by: Stephan Gerhold <[email protected]>
Acked-by: Caleb Connolly <[email protected]>
Tested-by: Sam Day <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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ehci_unregister() already clears the CMD_RUN bit with more careful checks.
It also ensures that we only do this in case we were actually in USB host
(rather than USB device) mode. It's not clear what the extra register
writes in the Qualcomm-specific ehci-msm driver are supposed to do, so just
drop them.
Signed-off-by: Stephan Gerhold <[email protected]>
Acked-by: Caleb Connolly <[email protected]>
Tested-by: Sam Day <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The enable order for the clocks does not matter much, we just need to
enable all the USB clocks. Use the clk bulk helpers to simplify the code.
Signed-off-by: Stephan Gerhold <[email protected]>
Acked-by: Caleb Connolly <[email protected]>
Tested-by: Sam Day <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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We need the USB clocks to do accesses like
wait_for_bit_le32(&ehci->usbcmd, CMD_RESET, ...)
so we should disable them only after all of them are done.
At the moment this works only because the clock driver doesn't actually
disabling these clocks in U-Boot.
Fixes: 9b3a9f896e66 ("ehci: msm: bring up iface + core clocks")
Signed-off-by: Stephan Gerhold <[email protected]>
Acked-by: Caleb Connolly <[email protected]>
Tested-by: Sam Day <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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