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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
i.MX
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- mx7ulp : fix WDOG
- imx8 : Phytec
- USB3 support for i.MX8
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
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According to i.MX7ULP Reference Manual we should wait for WDOG unlock
and reconfiguration to complete.
Section "59.5.3 Configure Watchdog" provides the following example:
DisableInterrupts; //disable global interrupt
WDOG_CNT = 0xD928C520; //unlock watchdog
while(WDOG_CS[ULK]==0); //wait until registers are unlocked
WDOG_TOVAL = 256; //set timeout value
WDOG_CS = WDOG_CS_EN(1) | WDOG_CS_CLK(1) | WDOG_CS_INT(1) |
WDOG_CS_WIN(0) | WDOG_CS_UPDATE(1);
while(WDOG_CS[RCS]==0); //wait until new configuration takes effect
EnableInterrupts; //enable global interrupt
Update U-Boot WDOG driver to align with i.MX7ULP reference manual.
Use 32 bits accessing to CS register. According to RM, the bits in
this register only can write once after unlock. So using 8 bits access
will cause problem.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Breno Lima <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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According to i.MX7ULP Reference Manual the second word write for both
UNLOCK and REFRESH operations must occur in maximum 16 bus clock.
The current code is using writel() function which has a DMB barrier to
order the memory access. The DMB between two words write may introduce
some delay in certain circumstance, causing a WDOG timeout due to 16 bus
clock window requirement.
Replace writel() function by __raw_writel() to achieve a faster memory
access and avoid such issue.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Breno Lima <[email protected]>
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Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Patrick Wildt <[email protected]>
Tested-by: Patrick Wildt <[email protected]>
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- Large number of Coverity reported issues addressed
- m41t62 bugfix
- Support more Android image compression formats
- FIT + DTO bugfix
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- designware_wdt: reset watchdog in designware_wdt_stop() function
(Meng)
- socfpga_stratix10: enable wdt command (Meng)
- wdt-uclass: Use IS_ENABLED for WATCHDOG_AUTOSTART (Teresa)
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There is no separate SPL/TPL config for WATCHDOG_AUTOSTART.
So use IS_ENABLED instead of CONFIG_IS_ENABLED to make watchdog
working in SPL again.
Fixes: 830d29ac3721 ("watchdog: Allow to use CONFIG_WDT without starting watchdog")
Signed-off-by: Teresa Remmet <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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In uboot command line environment, watchdog is not able to be
stopped with below commands:
SOCFPGA_STRATIX10 # wdt dev watchdog@ffd00200
SOCFPGA_STRATIX10 # wdt stop
Refer to watchdog driver in linux kernel, it is also need to reset
watchdog after disable it so that the disable action takes effect.
Signed-off-by: Meng Li <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
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Add the support of SYSCFG clock used by syscon driver
to prepare the clock management of STM32MP_SYSCON_SYSCFG.
This clock is already defined in kernel device tree,
stm32mp151.dtsi but not yet supported in the syscon driver:
syscfg: syscon@50020000 {
compatible = "st,stm32mp157-syscfg", "syscon";
reg = <0x50020000 0x400>;
clocks = <&rcc SYSCFG>;
};
It is safe to support this clock in U-Boot driver with
RCC_MC_APB3ENSETR, Bit 11 SYSCFGEN: SYSCFG peripheral clocks
enable.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Fix wrong register use when set/reset ST bit.
ST bit is in register M41T62_REG_SEC not in M41T62_REG_ALARM_HOUR.
I have not actually tested this. But this seemed buggy from inspection.
Fixes: 9bbe210512c4539 ("rtc: m41t62: add oscillator fail bit reset support")
Signed-off-by: Max Yang <[email protected]>
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When the default clocks cannot be set, the clock is silently probed and
the error is ignored. This is incorrect, since having the clocks at the
correct speed may be important for operation of the system.
Fix it by checking the return code.
Signed-off-by: Simon Glass <[email protected]>
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The width is set up in single_of_to_plat() and can only have three values,
all of which result in a non-zero divisor. Add a comment.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 331154)
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At present the return value of ofnode_get_property() is not checked, which
causes a coverity warning. While we are here, use logging for the errors.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 331157)
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Update dm_dump_drivers() to use the return value from uclass_get() to
check the validity of uc. This is equivalent and should be more attractive
to Coverity.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 316601)
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The devres_alloc() function is intended to avoid the need for freeing
memory, although in practice it may not be enabled, thus leading to a true
leak.
Nevertheless this is intended. Add a comment.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 312951)
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The devres_alloc() function is intended to avoid the need for freeing
memory, although in practice it may not be enabled, thus leading to a true
leak.
Nevertheless this is intended. Add a comment to explain this.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 312952)
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This cannot actually fail, but check the value anyway to keep coverity
happy.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 316351)
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At present if ifname is exactly IFNAMSIZ characters then it will result
in an unterminated string. Fix this by using strlcpy() instead.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 316358)
Acked-by: Ramon Fried <[email protected]>
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- x86: various improvements made in getting Chromium OS verified boot
running on top of coreboot, booting into U-Boot.
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TI J7200 EVM has lp876441 pmic that is similar to tps65941. Add support
for same with existing driver with new compatible.
Signed-off-by: Gowtham Tammana <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Acked-by: Jaehoon Chung <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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The K3 AM65x family of SoCs have the next generation of the PRU-ICSS
processor subsystem, commonly referred to as ICSSG. Each ICSSG processor
subsystem on AM65x SR1.0 contains two primary PRU cores and two new
auxiliary PRU cores called RTUs. The AM65x SR2.0 SoCs have a revised
ICSSG IP that is based off the subsequent IP revision used on J721E
SoCs. This IP instance has two new custom auxiliary PRU cores called
Transmit PRUs (Tx_PRUs) in addition to the existing PRUs and RTUs.
Each RTU and Tx_PRU cores have their own dedicated IRAM (smaller than
a PRU), Control and debug feature sets, but is different in terms of
sub-modules integrated around it and does not have the full capabilities
associated with a PRU core. The RTU core is typically used to aid a
PRU core in accelerating data transfers, while the Tx_PRU cores is
normally used to control the TX L2 FIFO if enabled in Ethernet
applications. Both can also be used to run independent applications.
The RTU and Tx_PRU cores though share the same Data RAMs as the PRU
cores, so the memories have to be partitioned carefully between different
applications. The new cores also support a new sub-module called Task
Manager to support two different context thread executions.
The driver currently supports the AM65xx SoC
Signed-off-by: Keerthy <[email protected]>
Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Murali Karicheri <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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The Programmable Real-Time Unit - Industrial Communication
Subsystem (PRU-ICSS) is present of various TI SoCs such as
AM335x or AM437x or the AM654x family. Each SoC can have
one or more PRUSS instances that may or may not be identical.
The PRUSS consists of dual 32-bit RISC cores called the
Programmable Real-Time Units (PRUs), some shared, data and
instruction memories, some internal peripheral modules, and
an interrupt controller. The programmable nature of the PRUs
provide flexibility to implement custom peripheral interfaces,
fast real-time responses, or specialized data handling.
Add support for pruss driver. Currently am654x family
is supported.
Signed-off-by: Keerthy <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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scracth register
RTC second scratch register[32-bit]:
-zero byte hold boot count value
-first byte hold update available state
-second byte hold version
-third byte hold magic number
Signed-off-by: Gireesh Hiremath <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Gbp-Pq: Topic apertis/guardian
Gbp-Pq: Name am335x-guardian-software-update-available-status-is-store.patch
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update panel driver hx8238
fix build bug
Signed-off-by: Gireesh Hiremath <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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These headers are not actually used. Drop them so that this driver can
be used by other boards, e.g. coreboot.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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When booting from coreboot we may not have a PCH driver available. The
SPI driver can operate without the PCH but currently complains in this
case. Update it to continue to work normally. The only missing feature
is memory-mapping of SPI-flash contents, which is not essential.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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At present only bridge devices are bound before relocation, to save space
in pre-relocation memory. In some cases we do actually want to bind a
device, e.g. because it provides the console UART. Add a devicetree
binding to support this.
Use the PCI_VENDEV() macro to encode the cell value. This is present in
U-Boot but not used, so move it to the binding header-file.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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These functions don't modify the device-ID struct that is passed in, so
mark the argument as const, so the data structure can be declared that
way. This allows it to be placed in the rodata section.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Add a new 'quiet' argument to mmc_get_op_cond() function which avoids
printing error message when SD/eMMC card is not detected.
Espressobin and mx6cuboxi boards use this function for detecting presence
of eMMC and therefore it is expected and normal that eMMC does not have to
be connected. So error message "Card did not respond to voltage select!"
should be skipped in this case as it is not an error.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Acked-by: Jaehoon Chung <[email protected]>
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The config option CONFIG_DEBUG_UART_CLOCK is not used by Armada 3720's
serial driver (it wasn't even before the recent update of that driver).
Even if it was used, the value was incorrect (the frequency of the clock
is 25 MHz, not 25.8048 MHz).
Remove it from config files and set the default value to 0.
Signed-off-by: Marek Behún <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Pali Rohár <[email protected]>
Reviewed-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Konstantin Porotchkin <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Remapped address of PCIe outbound window may have set only bits from the
mask. Add additional check that remapped address which is calculated from
PCIe bus address specified in DTS file is valid.
Remove also useless clearing of low 16 bits in win_mask. As win_size is
power of two and is at least 0x10000 it means that it always has zero low
16 bits.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Konstantin Porotchkin <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Function rtc_to_tm() is needed for FAT file system support even if we don't
have a real time clock. So move it from drivers/ to lib/.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The ST-Ericsson DB8500 SoC contains a MUSB OTG controller which
supports both host and gadget mode. For some reason there is
nothing special about it - add a simple glue driver for Ux500
that literally just sets up MUSB together with a generic PHY.
There are no SoC-specific registers etc needed to make USB work.
The new Ux500 glue driver is only tested to work with DM_USB
and DM_USB_GADGET. Both host and gadget mode work fine on
the u8500 "stemmy" board that is already present in U-Boot.
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Stephan Gerhold <[email protected]>
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The AB8500 PMIC contains an USB PHY that needs to be set up in
device or host mode to make USB work properly. Add a simple driver
for the generic PHY uclass that allows enabling it.
The if (CONFIG_IS_ENABLED(USB_MUSB_HOST)) might be a bit strange.
The USB PHY must be configured in either host or device mode and
somehow the USB PHY driver must be made aware of the mode.
Actually, the MUSB driver used together with this PHY does not
support dynamic selection of host/device mode in U-Boot at the moment.
Therefore, one very simple approach that works fine is to select
the mode to configure at compile time. When the MUSB driver is
configured in host mode the PHY is configured in host mode, and
similarly when the MUSB driver is configured in device/gadget mode.
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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All devices based on ST-Ericsson Ux500 use a PMIC similar to AB8500
(Analog Baseband). There is AB8500, AB8505, AB9540 and AB8540
although in practice only AB8500 and AB8505 are relevant since the
platforms with AB9540 and AB8540 were cancelled and never used in
production.
In general, the AB8500 PMIC uses I2C as control interface, where the
different register banks are represented as separate I2C devices.
However, in practice AB8500 is always connected to a special I2C bus
on the DB8500 SoC that is controlled by the power/reset/clock
management unit (PRCMU) firmware.
Add a simple driver that allows reading/writing registers of the
AB8500 PMIC. The driver directly accesses registers from the PRCMU
parent device (represented by syscon in U-Boot). Abstracting it
further (e.g. with the i2c uclass) would not provide any advantage
because the PRCMU I2C bus is always just connected to AB8500 and
vice-versa.
The ab8500.h header is mostly taken as-is from Linux (with some
minor adjustments) to allow using similar code in both Linux and
U-Boot.
Cc: Linus Walleij <[email protected]>
Signed-off-by: Stephan Gerhold <[email protected]>
Acked-by: Jaehoon Chung <[email protected]>
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Add PCIe driver for UniPhier SoCs. This PCIe controller is based on
Synopsys DesignWare Core IP.
This version doesn't apply common DW functions because supported
controller doesn't have unroll version of iATU.
Signed-off-by: Kunihiko Hayashi <[email protected]>
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Add PCIe PHY driver support for Pro5, LD20 and PXs3 SoCs.
Signed-off-by: Kunihiko Hayashi <[email protected]>
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Add reset control for PCIe controller on each SoC.
Signed-off-by: Kunihiko Hayashi <[email protected]>
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Add clock control for PCIe controller on each SoC.
Signed-off-by: Kunihiko Hayashi <[email protected]>
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Linux kernel binding is using atmel,24c01 compatible string. On the
other hand there is atmel,24c01a which is not listed in the kernel.
Add compatible string without "a" suffix to be compatible with Linux
kernel binding.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Michal Simek <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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Simplify the code a bit by using dev_read_addr_ptr() instead of
dev_read_addr(). This avoids having to cast explicitly to the
struct nomadik_mtu_regs.
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
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Nomadik GPIO is a fairly simple GPIO module used in the ST-Ericsson
Ux500 SoCs (and some older Nomadik SoCs). It uses registers where
each GPIO is represented as a single bit, plus "set" and "clear"
registers that allow updating the state without having to read the
existing state.
The driver implements support for it for use together with DM_GPIO
and the existing ste-dbx5x0.dtsi device tree.
Cc: Linus Walleij <[email protected]>
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
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The original U-Boot port for the ST-Ericsson U8500 SoC was dropped
in commit 68282f55b846 ("arm: Remove unused ST-Ericsson u8500 arch").
Most of the drivers related to the old port were removed, but the
db8500_gpio.c driver was forgotten for some reason. There is no way
to select it and it does not compile anymore because of missing
headers, so let's just remove it.
The new port for U8500 introduced in commit 689088f9dae8
("arm: Add support for ST-Ericsson U8500 SoC") fully embraces the
new Driver Model and device trees where possible, so this is
preparation to add a new, simplified GPIO driver based on DM_GPIO.
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
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Following warnings (unused variables) are raised:
drivers/spi/mxc_spi.c: In function 'mxc_spi_probe':
drivers/spi/mxc_spi.c:595:14: error: unused variable 'blob' [-Werror=unused-variable]
595 | const void *blob = gd->fdt_blob;
| ^~~~
drivers/spi/mxc_spi.c:594:6: error: unused variable 'node' [-Werror=unused-variable]
594 | int node = dev_of_offset(bus);
Move the variable declaration inside the code where they are used.
Signed-off-by: Stefano Babic <[email protected]>
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The Microchip KSZ9477/KSZ9897/KSZ9567 7-Port Gigabit Ethernet Switches
support SGMII/RGMII/MII/RMII with register access via SPI, I2C, or MDIO.
This driver currently supports I2C register access but SPI or MDIO register
access can be easily added at a later time.
Tagging is not implemented and instead the active port is tracked to
avoid needing a tag to store port information.
This was tested with the imx8mm-venice-gw7901 board which has a
KSZ9897S switch with an IMX8MM FEC MAC master connected via RGMII_ID.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Enabling promiscuous mode is necessary if FEC is the master of a DSA
switch driver where each port has their own MAC address.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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If the FEC is connected to a fixed-link (upstream switch port for
example) the phy_of_node should be set to the fixed-link node
so that speed and other properties can be found properly.
In addition fix a typo in the debug string.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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When using uclass_get_device* to get the FEC device we need to use
device sequence instead of index into UCLASS_ETH. In systems where for
example a I2C based DSA switch exists it will probe before the FEC
master and its ports will be registered first and have the first
indexes yet the FEC's sequence comes from the device-tree alias.
Take for example the imx8mm-venice-gw7901 board which has an i2c based
DSA switch:
u-boot=> net list
eth1 : lan1 00:0d:8d:aa:00:2f
eth2 : lan2 00:0d:8d:aa:00:30
eth3 : lan3 00:0d:8d:aa:00:31
eth4 : lan4 00:0d:8d:aa:00:32
eth0 : ethernet@30be0000 00:0d:8d:aa:00:2e active
Thus in this case uclass_get_device(UCLASS_ETH, 0, &dev) returns lan1
which is wrong but uclass_get_device_seq(UCLASS_ETH, 0, &dev) returns
ethernet@30be000 which is correct.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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The driver depends on DM_SPI and if it's not available (e. g. in SPL),
then we should not try to build it as this will fail.
Signed-off-by: Frieder Schrempf <[email protected]>
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