| Age | Commit message (Collapse) | Author |
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Set up opcode extension and enable/disable DTR mode based on whether the
command is DTR or not.
xSPI flashes can have a 4-byte dummy address associated with some
commands like the Read Status Register command in octal DTR mode. Since
the flash does not support sending the dummy address, we can not use
automatic write completion polling in DTR mode. Further, no write
completion polling makes it impossible to use DAC mode for DTR writes.
In that mode, the controller does not know beforehand how long a write
will be and so it can de-assert Chip Select (CS#) at any time. Once CS#
is de-assert, the flash will go into burning phase. But since the
controller does not do write completion polling, it does not know when
the flash is busy and might send in writes while the flash is not ready.
So, disable write completion polling and make writes go through indirect
mode for DTR writes and let spi-mem take care of polling the SR.
Signed-off-by: Pratyush Yadav <[email protected]>
Acked-by: Jagan Teki <[email protected]>
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Once the start bit is toggled it takes a small amount of time before it
is internally synchronized. This means we can't start writing during
that part. So add a small delay to allow the bit to be synchronized.
Signed-off-by: Pratyush Yadav <[email protected]>
Acked-by: Jagan Teki <[email protected]>
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If the device tree provides a read delay value, use that directly and do
not perform the calibration procedure.
This allows the device tree to over-ride the read delay value in cases
where the read delay value obtained via calibration is incorrect. One
such example is the Cypress Semper flash. It needs a read delay of 4 in
octal DTR mode. But since the calibration procedure is run before the
flash is switched in octal DTR mode, it yields a read delay of 2. A
value of 4 works for both octal DTR and legacy modes.
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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spi_mem_default_supports_op() rejects DTR ops by default to ensure that
the controller drivers that haven't been updated with DTR support
continue to reject them. It also makes sure that controllers that don't
support DTR mode at all (which is most of them at the moment) also
reject them.
This means that controller drivers that want to support DTR mode can't
use spi_mem_default_supports_op(). Driver authors have to roll their own
supports_op() function and mimic the buswidth checks. Or even worse,
driver authors might skip it completely or get it wrong.
Add spi_mem_dtr_supports_op(). It provides a basic sanity check for DTR
ops and performs the buswidth requirement check. Move the logic for
checking buswidth in spi_mem_default_supports_op() to a separate
function so the logic is not repeated twice.
Signed-off-by: Pratyush Yadav <[email protected]>
Acked-by: Jagan Teki <[email protected]>
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In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", the second byte is the
inverse of the opcode. When it is "hex" an additional opcode byte based
is sent with the command whose value can be anything.
So, make opcode a 16-bit value and add a 'nbytes', similar to how
multiple address widths are handled.
All usages of sizeof(op->cmd.opcode) also need to be changed to be
op->cmd.nbytes because that is the actual indicator of opcode size.
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add a driver for Macronix SPI controller IP.
This patch referred from linux spi-mxic.c. The difference from the
linux version is described here.
1. To adapt uboot spi framework, modify some functions naming.
2. Remove the incompatible functions of Uboot.
3. Add dummy byte recalculattion function to support dummy buswidth
not align data buswidth operation.(ex: 1-1-4, 1-1-8)
4. Add Octal mode support.
Signed-off-by: Zhengxun <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
[jagan: fixed file permission, comment line, kconfig]
Signed-off-by: Jagan Teki <[email protected]>
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Unlike imx6, on imx7 the USB PHY is described as:
usbphynop1: usbphynop1 {
compatible = "usb-nop-xceiv";
clocks = <&clks IMX7D_USB_PHY1_CLK>;
clock-names = "main_clk";
#phy-cells = <0>;
};
which does not have the 'reg' property.
Do not return an error when the 'reg' property is not found
for the USB PHY.
This fixes USB gadget regression on a imx7s-warp board.
Successfully tested the "ums 0 mmc 0" command on two boards:
imx7s-warp and imx6dl-pico-pi.
Signed-off-by: Fabio Estevam <[email protected]>
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On a imx7s-warp board the fdtdec_get_alias_seq() function
always fails.
As priv->portnr is only used on i.MX6, move fdtdec_get_alias_seq()
inside the CONFIG_MX6 block.
Signed-off-by: Fabio Estevam <[email protected]>
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Import R8A779A0 V3U PFC tables from Linux 5.12, commit 9f4ad9e425a1
("Linux 5.12") . Add parts of PFC table integration from
pinctrl: renesas: Add R8A779A0 V3U PFC tables
by Hai Pham <[email protected]>" .
Signed-off-by: Marek Vasut <[email protected]>
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The R8A779A0 V3U GPIO block has additional "General Input Enable" INEN
register. Add new R8A779A0 compatible string with a new quirk and also
a handler for this quirk which toggles the INEN register in the right
place. INEN register handling is based on "gpio: renesas: Add R8A779A0
V3U support" by Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Add clock tables for R8A779A0 V3U SoC from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12")
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
--
Marek: - Add .reset_modemr_offset
- Sync tables from Linux 5.12
- Rebase on latest u-boot
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On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value
from cpg_pll_configs table while PLL{20,21,30,31,4} use
different control offset. Introduce new types to handle
this and handle those types in the Gen3 clock code.
Based on "clk: renesas: Add support for R8A779A0 V3U PLLn"
by Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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The get_mtd_device_nm() function (code imported from Linux) simply
iterates all registered MTD devices and compares the given name with
all MTDs' names.
With SPI_FLASH_MTD enabled U-Boot registers a SPI-NOR as a MTD device
with name identical to the SPI flash chip name (from SPI ID table). Thus
for a board with multiple same SPI-NORs it registers multiple MTDs, but
all with the same name (such as "s25fl164k"). We do not want to change
this behaviour, since such a change could break existing boot scripts,
which can rely on a hardcoded name.
In order to allow somehow to uniqely select a MTD device, change
get_mtd_device_nm() function as such:
- if first character of name is '/', try interpreting it as OF path
- otherwise compare the name with MTDs name and MTDs device name.
In the following example a board has two "s25fl164k" SPI-NORs. They both
have name "s25fl164k", thus cannot be uniquely selected via this name.
With this change, the user can select the second SPI-NOR either with
"spi-nor@1" or "/soc/spi@10600/spi-nor@1".
Example:
=> mtd list
List of MTD devices:
* s25fl164k
- device: spi-nor@0
- parent: spi@10600
- driver: jedec_spi_nor
- path: /soc/spi@10600/spi-nor@0
- type: NOR flash
- block size: 0x1000 bytes
- min I/O: 0x1 bytes
- 0x000000000000-0x000000800000 : "s25fl164k"
* s25fl164k
- device: spi-nor@1
- parent: spi@10600
- driver: jedec_spi_nor
- path: /soc/spi@10600/spi-nor@1
- type: NOR flash
- block size: 0x1000 bytes
- min I/O: 0x1 bytes
- 0x000000000000-0x000000800000 : "s25fl164k"
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Cc: Priyanka Jain <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Patrick Delaunay <[email protected]>
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In order for `mtd list` U-Boot command to list SPI NOR devices without
the need to run `sf probe` before, we have to probe SPI NOR devices in
mtd_probe_devices().
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Pali Rohár <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Cc: Priyanka Jain <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Patrick Delaunay <[email protected]>
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The device_probe() function does the same thing as mtd_probe() and
mtd_probe() is only used in mtd_probe_uclass_mtd_devs(), where the
probing can be made simpler by using uclass_foreach_dev_probe macro.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Pali Rohár <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Cc: Priyanka Jain <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Patrick Delaunay <[email protected]>
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Fill in mtd->dev member with nor->dev.
This can be used by MTD OF partition parser.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Pali Rohár <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Cc: Priyanka Jain <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Patrick Delaunay <[email protected]>
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Currently when the SPI_FLASH_MTD config option is enabled, only one SPI
can be registered as MTD at any time - it is the last one probed (since
with old non-DM model only one SPI NOR could be probed at any time).
When DM is enabled, allow for registering multiple SPI NORs as MTDs by
utilizing the nor->mtd structure, which is filled in by spi_nor_scan
anyway, instead of filling a separate struct mtd_info.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Pali Rohár <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Cc: Priyanka Jain <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Patrick Delaunay <[email protected]>
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Add support for parsing partitions defined in device-trees via the
`partitions` node with `fixed-partitions` compatible.
The `mtdparts`/`mtdids` mechanism takes precedence. If some partitions
are defined for a MTD device via this mechanism, the code won't register
partitions for that MTD device from OF, even if they are defined.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Patrick Delaunay <[email protected]>
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Add function for retrieving full node path of a given ofnode.
This uses np->full_name if OF is live, otherwise a call to
fdt_get_path() is made.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add functions ofnode_get_addr_size_index_notrans(), which is a
non-translating version of ofnode_get_addr_size_index().
Some addresses are not meant to be translated, for example those of MTD
fixed-partitions.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Macronix NAND Flash devices are available in different configurations
and densities.
MX"35" means SPI NAND
MX35"UF" , UF meands 1.8V
MX35LF"2G" , 2G means 2Gbits
MX35LF2G"E4" , E4 means internal ECC and Quad I/O(x4)
MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial
NAND flash device with 8-bit on-die ECC
https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/MX35UF4GE4AD,%201.8V,%204Gb,%20v0.00.pdf
MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial
NAND flash device with 8-bit on-die ECC
https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/MX35UF2GE4AC,%201.8V,%202Gb,%20v1.0.pdf
Validated via normal(default) and QUAD mode by read, erase, read back,
on Xilinx Zynq PicoZed FPGA board which included Macronix
SPI Host(drivers/spi/spi-mxic.c).
Signed-off-by: Jaime Liao <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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- x86: Discard .note.gnu.property sections
- nvme: Skip block device creation for inactive namespaces
- nvme: Convert NVMe doc to reST, and various minor fixes
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A udevice's priv space is cleared in alloc_priv() in the DM core.
Don't do it again in its probe() routine.
Signed-off-by: Bin Meng <[email protected]>
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mode_select_num_blocks and mode_select_block_len in 'struct nvme_ns'
are not useful. Drop them.
Signed-off-by: Bin Meng <[email protected]>
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At present there is an offset of one added during the creation of
block device. This can be very confusing as we wanted to encode the
namespace id in the block device name but namespae id cannot be zero.
This changes to use the namespace id directly in the block device
name, eliminating the offset of one effectively.
Suggested-by: Heinrich Schuchardt <[email protected]>
Signed-off-by: Bin Meng <[email protected]>
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At present for each namespace there is a block device created for it.
There is no issue if the number of supported namespaces reported from
the NVMe device is only 1.
Since QEMU commit 7f0f1acedf15 ("hw/block/nvme: support multiple namespaces"),
the number of supported namespaces reported has been changed from 1
to 256, but not all of them are active namespaces. The actual active
one depends on the QEMU command line parameters. A common case is
that namespace 1 being active and all other 255 being inactive.
If a namespace is inactive, the namespace identify command returns a
zero filled data structure. We can use field NSZE (namespace size) to
decide whether a block device should be created for it.
Reported-by: Heinrich Schuchardt <[email protected]>
Signed-off-by: Bin Meng <[email protected]>
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At present the block device creation happens in the NVMe uclass
driver post_probe() phase. In preparation to support multiple
namespaces, we should issue namespace identify before creating
block devices but that touches the underlying hardware hence it
is not appropriate to do such in the uclass driver post_probe().
Let's move it to driver probe() phase instead.
Signed-off-by: Bin Meng <[email protected]>
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AQA (Admin Queue Attributes) register is a dword size with
lower word of ASQS, and higher word of ACQS.
The code set the variable aqa twice, but it is redundant.
Signed-off-by: Wesley Sheng <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Each prp is 8 bytes, calculate the number of prps
per page should just divide page size by 8
there is no need to minus 1
Signed-off-by: Wesley Sheng <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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writel() and co. already include the endian swap; doing the swap twice
is, er, unhelpful.
Tested on a P4080DS, which boots perfectly fine off NVMe with this.
Signed-off-by: David Lamparter <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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The Clocking Wizard IP supports clock circuits customized
to your clocking requirements. The wizard support for
dynamically reconfiguring the clocking primitives for
Multiply, Divide, Phase Shift/Offset, or Duty Cycle.
Limited by U-Boot clk uclass without set_phase API, this
patch only provides set_rate to modify the frequency.
Signed-off-by: Zhengxun <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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pca953x also depends on i2c that's why add dependency to Kconfig.
Where GPIO is enabled but I2C compilation error pops up.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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The MX66UW2G345G is Macronix Flash with SINGLE and OCTAL I/O. Hence,
add SPI_NOR_OCTAL_READ flag for this flash.
Reviewed-by: Jagan Teki <[email protected]>
[jagan: change order of id flags]
Signed-off-by: Jagan Teki <[email protected]>
Signed-off-by: zhengxun <[email protected]>
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clock output"
This reverts commit 63756575b42b8b4fb3f59cbbf0cedf03331bc2d2.
Since this commit a imx6qdl-pico board boots extremely slowly
in both SPL as well as U-Boot proper.
Fix this regression by reverting the offending commit for now.
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Tested-by: Pierre-Jean Texier <[email protected]>
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Change to static about dm function.
They can be used with wrapper functions.
Signed-off-by: Jaehoon Chung <[email protected]>
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Use mmc_send_cmd instead of dm_mmc_send_cmd.
It doesn't need to distinguish this function.
Signed-off-by: Jaehoon Chung <[email protected]>
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Add FIFO mode support for SoCFPGA dwmmc, read "fifo-mode" property from DT.
Signed-off-by: Ley Foon Tan <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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The data read is not working when using FIFO mode.
From DesignWare databook, when a Data_Transfer_Over (DTO) interrupt is
received, the software should read the remaining data from FIFO.
Add DTO interrupt checking on data read path and clear interrupts before
start reading from FIFO. So, it doesn't clear the next pending
interrupts unintentionally after read from FIFO.
Signed-off-by: Ley Foon Tan <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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With a 48MHz input clock, the lowest bus frequency can be as low as
48000000 / (4 * 4095) = 2930Hz. Such an extremely low frequency will cause
the mmc framework take seconds to finish the initialization.
Limiting the minimum bus frequency to a slightly higher value can solve the
issue without any side effects.
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-rockchip into next
- New SoC platform support: rk3568;
- rockchip pcie Code compile issue fix;
- Board fix for rk3399 Khadas Edge;
- Add Rockchip NFC driver;
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clean up octeontx_smi_probe by using the live-tree API.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Commit 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency") leads to
network failure on the OrangePi PC.
=> dhcp
sun8i_emac_eth_start: Timeout
According to the commit message the change of the MDIO frequency is only
required for external PHYs.
Fixes: 4f0278dac56a ("net: sun8i-emac: Lower MDIO frequency")
Signed-off-by: Heinrich Schuchardt <[email protected]>
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Add SynQuacer's NETSEC GbE controller driver.
Since this driver will load the firmware from SPI NOR flash,
this depends on CONFIG_SYNQUACER_SPI=y.
Signed-off-by: Jassi Brar <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Revert some changes of commit 3a97da12ee7b ("net: dwc_eth_qos: add dwc
eqos for imx support") that were probably added by mistake.
One of these changes can lead to received data corruption (enabling
FUP and FEP bits). Another causes invalid register rxq_ctrl0 settings
for some platforms. And another makes some writes at unknown memory
location.
Fixes: 3a97da12ee7b ("net: dwc_eth_qos: add dwc eqos for imx support")
Signed-off-by: Daniil Stas <[email protected]>
Cc: Ye Li <[email protected]>
Cc: Fugang Duan <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Ramon Fried <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Patrice Chotard <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Disabling clk_ck clock leads to link up status loss in phy, which
leads to auto-negotiation restart before each network command
execution.
This issue is especially big for PXE boot protocol because of
auto-negotiation restarts before each configuration filename trial.
To avoid this issue don't disable clk_ck clock after it was enabled.
Signed-off-by: Daniil Stas <[email protected]>
Cc: Ramon Fried <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Cc: Patrice Chotard <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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commit f1bcad22dd19 ("net: e1000: add support for writing to EEPROM")
adds support for storing hwaddr in EEPROM however i210 devices do not
support this and thus results in errors such as:
Warning: e1000#0 failed to set MAC address'
Check if a flash device is present and if not return -ENOSYS indicating
this is not supported.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Remove the tab in clk_get_bulk to respect the coding rules.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add error callback in dfu stack to manage some board specific
behavior on DFU targets.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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