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CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC)
requires a different setting procedure. Make struct cpg_mssr_info
accessible to handle the clock setting in that case.
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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The MODEMR register offset changed on R8A779A0, make the MODEMR offset
configurable. Fill the offset in on all clock drivers. No functional
change.
Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from
struct cpg_mssr_info" by Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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This supports RPCD2 clock handling. While at it, add the check point
for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd
number
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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This patch fixes Realtime Module Stop Control Register (RMSTPCR) offsets
based on R-Car Gen3, H2/M2/M2N/E2/E2X hardware user's manual.
The r8a73a4 only has RMSTPCR0 - RMSTPCR5 so this calculation change
doesn't affect it.
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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RPC clk_get_rate will return error code instead of expected clock rate.
Fix this.
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Reinstate RPC clock on D3/E3 after Linux 5.12 synchronization.
The D3 and E3 clock drivers do not contain RPC clock entries
mainline Linux yet.
Signed-off-by: Marek Vasut <[email protected]>
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Synchronize R-Car Gen3 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut <[email protected]>
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Synchronize R-Car Gen2 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut <[email protected]>
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Synchronize RZ/G2 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut <[email protected]>
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Until now the mvpp2 driver used an extra 'phy-speed'
DT property in order to differentiate between the
SGMII and SGMII @2.5GHz. As there is a dedicated
PHY_INTERFACE_MODE_SGMII_2500 flag to mark the latter
start using it and drop the custom flag.
Signed-off-by: Marcin Wojtas <[email protected]>
Reviewed-by: Stefan Chulski <[email protected]>
Reviewed-by: Nadav Haklai <[email protected]>
Tested-by: Nadav Haklai <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Currently, there are 2 valid cases for interface, PHY
and mdio relation:
- If an interface has PHY handler, it'll call
mdio_mii_bus_get_from_phy(), which will register
MDIO bus.
- If we want to use fixed-link for an interface,
PHY handle is not defined in the DTS, and no
MDIO is registered.
There is a third case, for some boards (with switch),
the MDIO is used for switch configuration, but the interface
itself uses fixed link. This patch allows this option by
checking if fixed-link subnode is defined, in this case,
MDIO bus is registers, but the PHY address is set to
PHY_MAX_ADDR for this interface, so this interface will
not try to access the PHY later on.
Signed-off-by: Stefan Chulski <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Ben Peled <[email protected]>
Reviewed-by: Stefan Chulski <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Signed-off-by: Ben Peled <[email protected]>
Reviewed-by: Stefan Chulski <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Signed-off-by: Ben Peled <[email protected]>
Reviewed-by: Stefan Chulski <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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GMII_SPEED should be enabled for 2.5G speed
Signed-off-by: Stefan Chulski <[email protected]>
Reviewed-by: Yan Markman <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Because the mvpp2 driver now relies on the PHYLIB and
the external MDIO driver, configuring low level
SMI bus settings is redundant.
Signed-off-by: Marcin Wojtas <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Reviewed-by: Stefan Chulski <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Signed-off-by: Stefan Chulski <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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1. Differ between Port1 RGMII and SFI modes in Netcomplex config.
2. Remove XPCS config from SFI mode.
Port1 doesn't XPCS domain, XPCS config should be removed.
Access to Port1 XPCS can cause stall.
3. Add Port1 MPCS configurations.
Signed-off-by: Stefan Chulski <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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s/psci_features/request_psci_features/g for the case when both
ARCH_SUPPORT_PSCI=y and ARM_PSCI_FW=y, that leads to these
compilation issues:
drivers/firmware/psci.c:69:12: error: conflicting types for 'psci_features'
69 | static int psci_features(u32 psci_func_id)
| ^~~~~~~~~~~~~
In file included from drivers/firmware/psci.c:23:
./arch/arm/include/asm/system.h:548:5: note: previous declaration of 'psci_features' was here
548 | s32 psci_features(u32 function_id, u32 psci_fid);
| ^~~~~~~~~~~~~
Tested-by: Alexandru Gagniuc <[email protected]>
Reported-by: Alexandru Gagniuc <[email protected]>
Fixes: b7135b034f ("psci: add features/reset2 support")
Signed-off-by: Igor Opaniuk <[email protected]>
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- Add base support for Marvell OcteonTX2 CN9130 DB (mostly done
by Kostya)
- Sync Armada 8k MMU setup with Marvell version (misc Marvell
authors)
- spi: kirkwood: Some fixes especially for baudrate generation
(misc Marvell authors)
- mvebu: x530: Reduce SPL image size (Stefan)
- Rename "rx_training" to "mvebu_comphy_rx_training" (Stefan)
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At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.
This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.
To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
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Even if only USB gadget is defined, dwc3 generic driver enables
a definition and probe/remove functions for host driver.
This enables the definition if USB_HOST is enabled only.
Signed-off-by: Kunihiko Hayashi <[email protected]>
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All newer Allwinner SoCs (since about 2013) miss the CONFIGDATA register
in their MUSB implementation, so they need a quirk to hardcode this.
Currently this quirk depends on listing the SoCs affected in musb_reg.h,
which means that this list needs to grow with every new chip.
Move the quirk feature into Kconfig, next to PIO_ONLY, and change the
default to y (for Allwinner builds), while listing the early
implementations as exceptions.
This fixes USB peripheral operation on some newer SoCs, which were not
explicitly listed before.
Tested on H6, H616, R40 (which were broken before), and also on the H5
and A20, for regressions.
Signed-off-by: Andre Przywara <[email protected]>
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The pcie_dw_mvebu configure ATU regions for memory, configuration
and IO space types. However the latter is not obligatory
and when not specified in the device tree, causes wrong
ATU configuration. Fix that by adding a dependency on the
detected PCIE regions count.
Signed-off-by: Marcin Wojtas <[email protected]>
Reviewed-on: https://sj1git1.cavium.com/18136
Reviewed-by: Kostya Porotchkin <[email protected]>
Tested-by: Kostya Porotchkin <[email protected]>
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After commit 1fe929ed497bcc8975be8d37383ebafd22b99dd2
("spi: kirkwood: prevent configuring speed exceeding max controller freq")
the spi frequency could be set to 0 on platform where spi-max-frequency
is not defined (e.g. on armada-388-gp). Prevent limiting speed in
mentioned cases.
Signed-off-by: Grzegorz Jaszczyk <[email protected]>
Tested-by: Kostya Porotchkin <[email protected]>
Reviewed-by: Marcin Wojtas <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This patch adds a limitation in the kirkwood_spi driver
set_speed hook, which prevents setting too high transfer
speed.
Signed-off-by: Marcin Wojtas <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Tested-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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The Armada SoC family implementation of this SPI hardware module has
extended the configuration register to allow for a wider range of SPI
clock rates. Specifically the Serial Baud Rate Pre-selection bits in the
SPI Interface Configuration Register now also use bits 6 and 7 as well.
Modify the baud rate calculation to handle these differences for the
Armada case. Potentially a baud rate can be setup using a number of
different pre-scalar and scalar combinations. This code tries all
possible pre-scalar divisors (8 in total) to try and find the most
accurate set.
Signed-off-by: Ken Ma <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-amlogic
- dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro
- usb: dwc3-meson-g12a: skip phy on -ENODATA aswell
- net: dwmac_meson8b: do not set TX delay in TXID & RXID
- net: designware: meson8b: add g12a compatible
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Add support for the Meson G12A dwmac glue compatible needed after Linux 5.12 sync.
Signed-off-by: Neil Armstrong <[email protected]>
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When the PHY interface is set as TXID & RXID, the delays should be taken from DT,
but first they should not be hardcoded since the PHY driver will set them.
Fixes: 798424e857 ("net: designware: add Amlogic Meson8b & later glue driver")
Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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If the PHY isn't specified in the DT, -ENODATA means it should be skipped,
handle it like -ENOENT.
With that, devices without USB3 supported can have USB working (Odroid-HC4).
Fixes: adb049abf7 ("usb: dwc3: Add Meson G12A USB Glue")
Signed-off-by: Neil Armstrong <[email protected]>
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The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work
properly due to the wrong implementations. It will cause the u-boot
PWM command to not work as expected. The bugs will be resolved in this
patch.
Signed-off-by: Vincent Chen <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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Variables which had previously been stored in .bss are moved to .data. In
addition, probed needs to be reset when the clock driver is re-bound
post-relocation.
Signed-off-by: Sean Anderson <[email protected]>
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No other (real) clocks have the cpu clock as their parent; instead they are
children of aclk. Move the clint clock under aclk to match them.
Signed-off-by: Sean Anderson <[email protected]>
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This simplifies the PLL creation process, since we don't have to pass all
the parameters individually.
Signed-off-by: Sean Anderson <[email protected]>
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This conditional always evaluated as false, regardless of the value of reg.
Fix it so that it properly tests the bits in the PLL register. Also test
PLL_EN, now that we set it.
Reported-by: Damien Le Moal <[email protected]>
Signed-off-by: Sean Anderson <[email protected]>
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After starting or setting the rate of a PLL, the enable bit must be set.
This fixes a bug where the AI ram would not be accessible, because it
requires PLL1 to be running.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Damien Le Moal <[email protected]>
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If the user/dev explicitly requests a clock be assigned a certain rate,
then we should warn them if we can't do it. This makes it clear if the
clock is running at the default rate.
Signed-off-by: Sean Anderson <[email protected]>
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This patch changes the functioning of the detection of w1 devices.
The old way was a comparison between detected w1 and the ones described in
the device tree. Now it will just look for the driver matching the family
id of the w1 detected.
The patch is inspired from Maxime Ripard code.
Signed-off-by: Kory Maincent <[email protected]>
Reviewed-by: Maxime Ripard <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-ti
- Initial support for AM64 EVM and SK
- K3 DDR driver unification for J7 and AM64 platforms.
- Minor fixes for TI clock driver
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Add a new compatible to support AM64 SoC
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Currently driver may end up caching disabled port ID as active
interface. Fix this by bailing out earlier in case port is marked
disabled in the DT.
Signed-off-by: Vignesh Raghavendra <[email protected]>
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CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8)
Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port)
as preparation to allow any one of the 8 ports to be used as ethernet
interface in U-Boot.
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Sync BCDMA and PKTDMA support from Kernel for AM64 SoC
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Add AM64 SoC specific channel mapping and endpoint data.
Signed-off-by: Vignesh Raghavendra <[email protected]>
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Extend PSIL EP data to include AM64 DMA specific information
Signed-off-by: Vignesh Raghavendra <[email protected]>
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ICSSG Ethernet driver uses two src threads per port (one per slice).
Similarly CPSW uses one src thread.
Drop PSIL EP static data for other src threads in order to reduce
R5 SPL footprint. This makes AM65x board bootable again.
Signed-off-by: Vignesh Raghavendra <[email protected]>
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With AM64x supporting only K3_NAV_RINGACC_RING_MODE_RING or the exposed
ring mode, all other K3 SoCs have also been moved to this common
baseline. Therefore drop other modes such as
K3_NAV_RINGACC_RING_MODE_MESSAGE (and proxy) to save on SPL footprint.
There is a saving of ~800 bytes with this change for am65x_evm_r5_defconfig.
Signed-off-by: Vignesh Raghavendra <[email protected]>
Reviewed-by: Grygorii Strashko <[email protected]>
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