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Since the commit commit 6a895d039ba7 ("net: Update eQos driver and FEC
driver to use eth phy interfaces") the field phyaddr of driver private data
struct eqos_priv is no more used in eqos_start() for the phy_connect()
parameter.
Now this variable is only initialized in eqos_probe_resources_stm32()
it can be removed.
Reviewed-by: Ramon Fried <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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Bind any subnode with name beginning by mdio, mdio0 for example,
and not only the "mdio" as namei of subnode.
Reviewed-by: Ramon Fried <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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Replace debug trace and printf to log macros:
- debug() replaced by dev_dbg() when device is available, this macro
indicate the device name since commit ceb70bb870ac ("dm: Print device
name in dev_xxx like Linux")
- printf() replaced by log_notice() to allow dispatch to log backends.
Reviewed-by: Ramon Fried <[email protected]>
Signed-off-by: Patrick Delaunay <[email protected]>
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The gpio reset and the assert or deassert delay are defined in generic
binding of the ethernet phy in Linux:
Documentation/devicetree/bindings/net/ethernet-phy.yaml
reset-gpios:
maxItems: 1
description:
The GPIO phandle and specifier for the PHY reset signal.
reset-assert-us:
description:
Delay after the reset was asserted in microseconds. If this
property is missing the delay will be skipped.
reset-deassert-us:
description:
Delay after the reset was deasserted in microseconds. If
this property is missing the delay will be skipped.
See also U-Boot: doc/device-tree-bindings/net/phy.txt
This patch adds the parsing of this common DT properties in the
u-class "eth_phy_generic", used by default in the associated driver
"eth_phy_generic_drv"
This parsing function eth_phy_of_to_plat can be reused by other
ethernet phy drivers for this uclass UCLASS_ETH_PHY.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Use same type as eth_device->iobase and support addresses greater
than INT_MAX.
Signed-off-by: Peter Hoyes <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
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Fixed a defect of a null pointer being discovered by Coverity Scan:
CID 331544: Null pointer dereferences (REVERSE_INULL)
Null-checking "size" suggests that it may be null, but it has already been
dereferenced on all paths leading to the check.
Signed-off-by: Chen Guanqiao <[email protected]>
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It is useful to be able to iterate over block devices. Typically there
are fixed and removable devices. For security reasons it is sometimes
useful to ignore removable devices since they are under user control.
Add iterators which support selecting the block-device type.
Signed-off-by: Simon Glass <[email protected]>
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Add support for reading devicetree flags for MMC devices. With this we
can distinguish between fixed and removable drives. Note that this
information is only available when the device is probed, not when it is
bound, since it is read in the of_to_plat() method. This could be changed
if needed later.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Rather than calling directly into the sandbox SDL code, we can use the
normal U-Boot console handling for this feature. Update the code, to make
it more generic.
Signed-off-by: Simon Glass <[email protected]>
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The v2 format is 64-bytes in size. Support this and drop v1 since it is
not used anymore.
Signed-off-by: Simon Glass <[email protected]>
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This function is not needed anymore. Drop it.
Signed-off-by: Simon Glass <[email protected]>
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Add a function to read this information from the EC. It is useful for
determining whether the battery has enough charge to boot.
Signed-off-by: Simon Glass <[email protected]>
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Allow lzma compression as well as lz4.
Signed-off-by: Simon Glass <[email protected]>
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It is sometimes helpful to see which sequence is assigned to a device.
Add debugging info for that.
Signed-off-by: Simon Glass <[email protected]>
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The Renesas R-Car Gen3 development kits contain board ID EEPROM.
This driver parses out the board ID and revision out of that
EEPROM and exports it e.g. for the board-info print on boot.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Sean Anderson <[email protected]>
Cc: Simon Glass <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-ti
- Enabled distro boot for all TI platforms.
- Cleanup for AM335x Guardian Board
- PRUSS rproc on AM65 platform.
- Add PMIC support for J7200
- Misc fixes for Nokia RX-51
# Conflicts:
# arch/arm/mach-omap2/am33xx/Kconfig
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As the migration deadline has passed, require that DM_PCI be used.
Signed-off-by: Tom Rini <[email protected]>
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As the deadline for migration to DM_USB, when using a USB host
controller has now gone two years past the deadline, enforce migration.
This is done by:
- Ensuring that all host controller options (other than the very legacy
old MUSB ones) now select USB_HOST. USB_HOST now enforces DM_USB and
OF_CONTROL.
- Remove other parts of Kconfig logic that had platforms pick DM_USB.
- To keep Kconfig happy, have some select statements test for USB_HOST
as well.
- Re-order some Kconfig entries and menus so that we can cleanly pick
host or gadget roles. For the various HCD options that have platform
glue options, group them together and update dependencies in some
cases.
- As SPL_DM_USB is not required, on platforms that had not yet enabled
it, disable it.
Cc: Marek Vasut <[email protected]>
Cc: Icenowy Zheng <[email protected]>
Cc: Samuel Holland <[email protected]>
Cc: FUKAUMI Naoki <[email protected]>
Cc: Andre Przywara <[email protected]>
Cc: Jagan Teki <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it. As this is also the last in family remove the related
support as well.
Cc: Angelo Durgehello <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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This driver is currently only used on MIPS Malta boards.
Signed-off-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This driver is currently only used on MIPS Malta boards.
Signed-off-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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On MIPS the DRAM start address respectively CONFIG_SYS_SDRAM_BASE
is still used as a virtual, CPU-mapped address instead of being used
as physical address. Converting all MIPS boards and generic MIPS code
to fix that is not trivial. Due to the approaching deadline for
PCI DM conversion, this workaround is required for MIPS boards with
PCI support until the CONFIG_SYS_SDRAM_BASE issue could be solved.
Add a compile-time option to let the PCI uclass core optionally map
the DRAM address to a physical address when adding the PCI region
of type PCI_REGION_SYS_MEMORY.
Signed-off-by: Daniel Schwierzeck <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
i.MX
----
- mx7ulp : fix WDOG
- imx8 : Phytec
- USB3 support for i.MX8
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
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According to i.MX7ULP Reference Manual we should wait for WDOG unlock
and reconfiguration to complete.
Section "59.5.3 Configure Watchdog" provides the following example:
DisableInterrupts; //disable global interrupt
WDOG_CNT = 0xD928C520; //unlock watchdog
while(WDOG_CS[ULK]==0); //wait until registers are unlocked
WDOG_TOVAL = 256; //set timeout value
WDOG_CS = WDOG_CS_EN(1) | WDOG_CS_CLK(1) | WDOG_CS_INT(1) |
WDOG_CS_WIN(0) | WDOG_CS_UPDATE(1);
while(WDOG_CS[RCS]==0); //wait until new configuration takes effect
EnableInterrupts; //enable global interrupt
Update U-Boot WDOG driver to align with i.MX7ULP reference manual.
Use 32 bits accessing to CS register. According to RM, the bits in
this register only can write once after unlock. So using 8 bits access
will cause problem.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Breno Lima <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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According to i.MX7ULP Reference Manual the second word write for both
UNLOCK and REFRESH operations must occur in maximum 16 bus clock.
The current code is using writel() function which has a DMB barrier to
order the memory access. The DMB between two words write may introduce
some delay in certain circumstance, causing a WDOG timeout due to 16 bus
clock window requirement.
Replace writel() function by __raw_writel() to achieve a faster memory
access and avoid such issue.
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Breno Lima <[email protected]>
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Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Patrick Wildt <[email protected]>
Tested-by: Patrick Wildt <[email protected]>
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- Large number of Coverity reported issues addressed
- m41t62 bugfix
- Support more Android image compression formats
- FIT + DTO bugfix
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- designware_wdt: reset watchdog in designware_wdt_stop() function
(Meng)
- socfpga_stratix10: enable wdt command (Meng)
- wdt-uclass: Use IS_ENABLED for WATCHDOG_AUTOSTART (Teresa)
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There is no separate SPL/TPL config for WATCHDOG_AUTOSTART.
So use IS_ENABLED instead of CONFIG_IS_ENABLED to make watchdog
working in SPL again.
Fixes: 830d29ac3721 ("watchdog: Allow to use CONFIG_WDT without starting watchdog")
Signed-off-by: Teresa Remmet <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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In uboot command line environment, watchdog is not able to be
stopped with below commands:
SOCFPGA_STRATIX10 # wdt dev watchdog@ffd00200
SOCFPGA_STRATIX10 # wdt stop
Refer to watchdog driver in linux kernel, it is also need to reset
watchdog after disable it so that the disable action takes effect.
Signed-off-by: Meng Li <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
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Add the support of SYSCFG clock used by syscon driver
to prepare the clock management of STM32MP_SYSCON_SYSCFG.
This clock is already defined in kernel device tree,
stm32mp151.dtsi but not yet supported in the syscon driver:
syscfg: syscon@50020000 {
compatible = "st,stm32mp157-syscfg", "syscon";
reg = <0x50020000 0x400>;
clocks = <&rcc SYSCFG>;
};
It is safe to support this clock in U-Boot driver with
RCC_MC_APB3ENSETR, Bit 11 SYSCFGEN: SYSCFG peripheral clocks
enable.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Fix wrong register use when set/reset ST bit.
ST bit is in register M41T62_REG_SEC not in M41T62_REG_ALARM_HOUR.
I have not actually tested this. But this seemed buggy from inspection.
Fixes: 9bbe210512c4539 ("rtc: m41t62: add oscillator fail bit reset support")
Signed-off-by: Max Yang <[email protected]>
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When the default clocks cannot be set, the clock is silently probed and
the error is ignored. This is incorrect, since having the clocks at the
correct speed may be important for operation of the system.
Fix it by checking the return code.
Signed-off-by: Simon Glass <[email protected]>
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The width is set up in single_of_to_plat() and can only have three values,
all of which result in a non-zero divisor. Add a comment.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 331154)
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At present the return value of ofnode_get_property() is not checked, which
causes a coverity warning. While we are here, use logging for the errors.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 331157)
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Update dm_dump_drivers() to use the return value from uclass_get() to
check the validity of uc. This is equivalent and should be more attractive
to Coverity.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 316601)
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The devres_alloc() function is intended to avoid the need for freeing
memory, although in practice it may not be enabled, thus leading to a true
leak.
Nevertheless this is intended. Add a comment.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 312951)
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The devres_alloc() function is intended to avoid the need for freeing
memory, although in practice it may not be enabled, thus leading to a true
leak.
Nevertheless this is intended. Add a comment to explain this.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 312952)
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This cannot actually fail, but check the value anyway to keep coverity
happy.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 316351)
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At present if ifname is exactly IFNAMSIZ characters then it will result
in an unterminated string. Fix this by using strlcpy() instead.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 316358)
Acked-by: Ramon Fried <[email protected]>
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- x86: various improvements made in getting Chromium OS verified boot
running on top of coreboot, booting into U-Boot.
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TI J7200 EVM has lp876441 pmic that is similar to tps65941. Add support
for same with existing driver with new compatible.
Signed-off-by: Gowtham Tammana <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Acked-by: Jaehoon Chung <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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The K3 AM65x family of SoCs have the next generation of the PRU-ICSS
processor subsystem, commonly referred to as ICSSG. Each ICSSG processor
subsystem on AM65x SR1.0 contains two primary PRU cores and two new
auxiliary PRU cores called RTUs. The AM65x SR2.0 SoCs have a revised
ICSSG IP that is based off the subsequent IP revision used on J721E
SoCs. This IP instance has two new custom auxiliary PRU cores called
Transmit PRUs (Tx_PRUs) in addition to the existing PRUs and RTUs.
Each RTU and Tx_PRU cores have their own dedicated IRAM (smaller than
a PRU), Control and debug feature sets, but is different in terms of
sub-modules integrated around it and does not have the full capabilities
associated with a PRU core. The RTU core is typically used to aid a
PRU core in accelerating data transfers, while the Tx_PRU cores is
normally used to control the TX L2 FIFO if enabled in Ethernet
applications. Both can also be used to run independent applications.
The RTU and Tx_PRU cores though share the same Data RAMs as the PRU
cores, so the memories have to be partitioned carefully between different
applications. The new cores also support a new sub-module called Task
Manager to support two different context thread executions.
The driver currently supports the AM65xx SoC
Signed-off-by: Keerthy <[email protected]>
Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Murali Karicheri <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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The Programmable Real-Time Unit - Industrial Communication
Subsystem (PRU-ICSS) is present of various TI SoCs such as
AM335x or AM437x or the AM654x family. Each SoC can have
one or more PRUSS instances that may or may not be identical.
The PRUSS consists of dual 32-bit RISC cores called the
Programmable Real-Time Units (PRUs), some shared, data and
instruction memories, some internal peripheral modules, and
an interrupt controller. The programmable nature of the PRUs
provide flexibility to implement custom peripheral interfaces,
fast real-time responses, or specialized data handling.
Add support for pruss driver. Currently am654x family
is supported.
Signed-off-by: Keerthy <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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scracth register
RTC second scratch register[32-bit]:
-zero byte hold boot count value
-first byte hold update available state
-second byte hold version
-third byte hold magic number
Signed-off-by: Gireesh Hiremath <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Gbp-Pq: Topic apertis/guardian
Gbp-Pq: Name am335x-guardian-software-update-available-status-is-store.patch
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update panel driver hx8238
fix build bug
Signed-off-by: Gireesh Hiremath <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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These headers are not actually used. Drop them so that this driver can
be used by other boards, e.g. coreboot.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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When booting from coreboot we may not have a PCH driver available. The
SPI driver can operate without the PCH but currently complains in this
case. Update it to continue to work normally. The only missing feature
is memory-mapping of SPI-flash contents, which is not essential.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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At present only bridge devices are bound before relocation, to save space
in pre-relocation memory. In some cases we do actually want to bind a
device, e.g. because it provides the console UART. Add a devicetree
binding to support this.
Use the PCI_VENDEV() macro to encode the cell value. This is present in
U-Boot but not used, so move it to the binding header-file.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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These functions don't modify the device-ID struct that is passed in, so
mark the argument as const, so the data structure can be declared that
way. This allows it to be placed in the rodata section.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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