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This patch adds support for MTK SPI NOR controller, which you
can see on mt7622 & mt7629.
1. This controller is designed only for SPI NOR. We can't adjust
its bus clock dynamically. Set clock in dts instead.
2. This controller only supports 1-1-1 write mode.
3. Remove mtk_snor_match_read() since upper SPI-MEM layer already
handles command.
4. sf read/write/update commands are tested with this driver.
Signed-off-by: SkyLake.Huang <[email protected]>
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This is a basic driver for the ultra-low-power Abracon AB x80x series
of RTC chips. It supports in particular, the supersets AB0805 and AB1805.
It allows reading and writing the time, and enables the supercapacitor or
battery charger.
Signed-off-by: Ying-Chun Liu (PaulLiu) <[email protected]>
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Set this flag so that it is available to those looking at the device. For
non-removable devices there is no need to check for insertion/removable
since the media can never change.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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At present if an eMMC part is in the system, the ACPI table generated
will include information about that, as well as the SD card. We only need
to include the SD card, since it has a card-detect GPIO. Use a different
compatible string for each option, and add code only for the SD card.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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In some cases so much of the framebuffer is updated that it is not worth
copying the changes piece by piece to the copy framebuffer. Add a function
to copy the whole thing.
Signed-off-by: Simon Glass <[email protected]>
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This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as
it is not configured for any board (any more). With this removal, some
PCI related files get cleaned up a bit.
Additional, dm_pciauto_setup_device() is now static, as it's not
referenced from any code outside of this C file.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This commit add an option TPL_BOOTCOUNT_LIMIT to
use bootcount on TPL.
Signed-off-by: Philippe Reynes <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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- Espressobin: Disable slot when emmc is not present (Pali)
- DS414; config header cleanup (Phil)
- PCI: auto-config enhancement (Phil)
- pci_mvebu: Also map IO region (Phil)
- serial: a3720: Implement pending method for output direction (Pali)
- turris_mox: Enable a few commands (Marek)
- helios4 & ClearFog changes (Dennis)
- Plus some minor misc changes
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The phydev structure has a PHY OF node pointer in it, use that OF node
first when looking up PHY OF node properties, since that is likely the
correct PHY OF node pointer. If the pointer is not valid, which is the
case e.g. on legacy DTs, fall back to parsing MAC ethernet-phy subnode.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Ramon Fried <[email protected]>
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Add phy driver support for MACs embedded inside Cortina Access SoCs
Signed-off-by: Abbie Chang <[email protected]>
Signed-off-by: Alex Nemirovsky <[email protected]>
CC: Joe Hershberger <[email protected]>
CC: Tom Rini <[email protected]>
CC: Aaron Tseng <[email protected]>
Moved out PHY specific code out of Cortina NI Ethernet driver
and into a Cortina Access PHY interface driver
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Add Cortina Access Ethernet device driver for CAxxxx SoCs.
This driver supports both legacy and DM_ETH network models.
Signed-off-by: Aaron Tseng <[email protected]>
Signed-off-by: Alex Nemirovsky <[email protected]>
Signed-off-by: Abbie Chang <[email protected]>
CC: Joe Hershberger <[email protected]>
CC: Abbie Chang <[email protected]>
CC: Tom Rini <[email protected]>
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Add some missing address translations from virtual address in local DRAM
to physical address, which is needed for the DMA transactions to work
correctly.
This issue was detected while testing the e1000 driver on the MIPS
Octeon III platform, which needs address translation.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Aaron Williams <[email protected]>
Cc: Chandrakala Chavva <[email protected]>
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Using (dm_)pci_virt_to_mem() is incorrect to translate the virtual
address in local DRAM to a physical address. The correct macro here
is virt_to_phys() so switch to using this macro.
As virt_to_bus() is now not used any more, this patch also removes
both definitions (DM and non-DM).
This issue was detected while testing the e1000 driver on the MIPS
Octeon III platform, which needs address translation.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Aaron Williams <[email protected]>
Cc: Chandrakala Chavva <[email protected]>
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bus_to_phys() is defined but not referenced at all. This patch removes
it completely.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Joe Hershberger <[email protected]>
Cc: Aaron Williams <[email protected]>
Cc: Chandrakala Chavva <[email protected]>
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Value pcie->dev in function pcie_advk_probe() is not initialized yet
so use dev as argument for dev_dbg()/dev_warn().
Function pcie_advk_wait_pio() itself prints error message on failure
so do not print duplicate error message in caller.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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To check if some output characters are waiting either in Transmitter
Holding Register or Transmitter Shift Register we need to look at
TX_EMPTY bit of UART Status Register.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Configure an IO region and window for PNP identical to how MEM region is
set up. Linux does this only if the DT defines a pcie-io-aperture
property for the SOC, but since all supported boards do this should not
be needed.
Signed-off-by: Phil Sutter <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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On my DS414, some PCI devices return odd values when probing BAR sizes.
An obvious case is all-ones response, the Linux driver
(drivers/pci/probe.c) catches those explicitly and a comment explains
that either bit 0 or bit 1 must be clear (depending on MEM or IO type).
Other BARs return e.g. 0xfff0000f or 0xfff00004 and thus manage to break
size calculation due to the "middle" zeroes. Mitigate that copying more
or less what Linux does and do a "find least bit set".
Signed-off-by: Phil Sutter <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This change extends previous commit 061c6d1b238a ("arm: mvebu: Espressobin:
Detect presence of emmc at runtime") and when emmc is not present then emmc
is removed from U-Boot DM and corresponding slot is disabled. Therefore on
Espressobin board without soldered emmc, state of emmc hw should be same as
if emmc was disabled in DTS.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The Armada driver also works on Nedap's custom Kirkwood board with a
Marvell 88F6180 CPU. The original commit of that driver,
commit 704d9a645e17 ("gpio: Add DM GPIO driver for Marvell MVEBU"),
also mentions that this driver would be suitable for Kirkwood. This
does not completely replace the Kirkwood specific driver as there
are still boards depending on that driver.
Signed-off-by: Harm Berntsen <[email protected]>
CC: Stefan Roese <[email protected]>,
Reviewed-by: Stefan Roese <[email protected]>
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- New Allwinner H616 SoC support (sans Ethernet & USB)
- H6 DT update
- Tanix TX6 TV box support
- OrangePi 3 support
- OrangePi Zero2 (H616) support
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This commit introduces DM H616 clock driver.
Signed-off-by: Jernej Skrabec <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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H616 pinctrl is no different configuration wise than others, so just add
compatible for it.
Signed-off-by: Jernej Skrabec <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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H616 is very similar to H6 so most of the infrastructure can be reused.
However, two big differences are that it doesn't have functional SRAM A2
which is usually used for TF-A and it doesn't have ARISC co-processor.
It also needs bigger SPL size - 48 KiB.
Signed-off-by: Jernej Skrabec <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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So far the only difference between the various Allwinner MMC controller
we are concerned about is the mod clock register offset.
This is actually not directly related to the MMC controller IP, but an
integration choice, dependent on the SoC this appears in.
To avoid becoming trapped with some compatible fallback strings, let's
remove the whole struct sunxi_mmc_variant, and replace this with a SoC
based choice, which we can derive from the CONFIG_MACH_SUNx_y symbols.
This will later simplify H616 support.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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While currently none of the newer Allwinner SoCs currently has I2C
support implemented in U-Boot, this will change soon. mvtwsi driver is
good as it is for them except one macro. Update it to be ready once I2C
support lands for those SoCs.
Signed-off-by: Jernej Skrabec <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
Reviewed-by: Samuel Holland <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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It turns out that several SoCs share same mmc configuration as H6. In
order to lower ifdef clutter replace H6 specific macro with common one.
Signed-off-by: Jernej Skrabec <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This PMIC can be found on H616 boards and it's very similar to AXP805
and AXP806.
Signed-off-by: Jernej Skrabec <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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So far all GBit users of the sun8i-emac driver were using the "rgmii"
PHY mode, even though this turns out to be wrong. It just worked because
the PHY driver doesn't do the proper setup (yet).
In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the
correct ones.
To allow the DTs to describe the phy-mode correctly, and to stay
compatible with Linux, at least allow those other RGMII modes in the
driver.
This avoids breakage if mainline DTs will be synced with U-Boot.
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Heinrich Schuchardt <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-mips
- MIPS: add support for Mediatek MT7620 SoCs
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Changes for 2020.04
-------------------
- new board:
Phytec phyCORE-i.MX8MP
i.MX8MN Beacon EmbeddedWorks devkit
- Fixes:
several nanbcb fixes
fix for imx8mm_beacon
- further switch to distro boot commands
- DM:
DM Ether for MX6UL
CI:
https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6013
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https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
Second set of u-boot-atmel features for 2021.04 cycle
This feature set includes macb updates for all interfaces and new
sama7g5 variant support; micrel ksz9031 DLL support; a new board from
Giant based on Adafruit feather form factor which contains a SAMA5D27
SoC; several fixes regarding the NAND flash PMECC block; and pincontrol
drive strength support for pio4 controller.
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Add DM_FLAG_PRE_RELOC flag for reset-mtmips to make sure this driver can
be probed before relocation even if u-boot,dm-pre-reloc is not present
in the dts.
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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Currently this driver does not set the value of plat->cfg.f_max, which
results in that MMC framework will always run at the lowest frequency.
This patch sets plat->cfg.f_max to the maximum allowed frequency, which
equals to the source clock frequency.
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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The driver is missing pad control settings (pad delay and pad conf) for
the mt7620 and mt76x8. Although mt76x8 still works well, mt7620 will
encounter CRC error on data transfers.
This patch adds default pad control settings for mt7620_compat.
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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It turns out that the sclk cycles used by mt7620/mt7628 is the same as
other chips (20 bits, 1048576), not 65536.
This patch removes sclk_cycle_shift from dev_comp, and uses a macro with
a value 20 instead.
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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This patch adds ethernet driver for MediaTek MT7620 SoC.
The MT7620 SoC has a built-in ethernet (Frame Engine) and a built-in
7-port switch and two xMII interfaces (can be MII/RMII/RGMII).
The port 0-3 of the switch connects to intergrited FE PHYs. Port 4 can be
configured to connect to either the intergrited FE PHY, or the xMII.
Port 5 always connects to the xMII. Port 6 is the CPU port.
This driver supports MT7530 giga switch connects to port 5.
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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This patch adds USB PHY driver for MediaTek MT7620 SoC
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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This patch adds spi controller support for MediaTek MT7620 SoC.
The SPI controller supports two chip selects. These two chip selects are
implemented as two separate register groups, but they share the same bus
(DI/DO/CLK), only CS pins are dedicated for each register group.
Appearently these two register groups cannot operates simulataneously so
they are implemented as one controller.
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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This patch adds GPIO controller driver for MediaTek MT7620 SoC
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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This patch adds watchdog support for the Mediatek MT7620 SoC
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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This patch adds pinctrl support for MediaTek MT7620 SoC.
The MT7620 SoC supports only pinmux.
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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This patch adds a clock driver for MediaTek MT7620 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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This patch adds uart support for MediaTek MT7620 and earlier SoCs.
The UART used by MT7620 is incompatible with the ns16550a driver.
All registers of this UART have different addresses. A special 16-bit
register for Divisor Latch is used to set the baudrate instead of the
original two 8-bit registers (DLL and DLM).
The driver supports of-platdata which is useful for tiny SPL.
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
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In case the clock framework is enabled, enable the SPI controller clock
and obtain max frequency from the clock framework.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jagan Teki <[email protected]>
Cc: Stefano Babic <[email protected]>
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The CSPI/ECSPI register bits do not differ between newer SoCs, instead
of having multiple copies of the same thing for each iMX SoC, define
the bits in the driver.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Jagan Teki <[email protected]>
Cc: Stefano Babic <[email protected]>
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Add ECSPI clock entries to iMX8MN clock driver. Only make those entries
available in case SPI support in U-Boot is enabled at all to conserve
space, esp. in SPL.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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The i.MX8M Mini can use the FlexSPI driver. Add support
for it to the driver.
Signed-off-by: Adam Ford <[email protected]>
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prevent unsued variable compiler warning if
DM_REGULATOR is not set.
Signed-off-by: Heiko Schocher <[email protected]>
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Now that header files no longer include common.h it must be included
first.
Otherwise the build fails with errors like
include/asm/arch/clock.h:43:1: error: unknown type name 'u32'
u32 imx_get_uartclk(void);
Fixes: c3dc39a2f85b ("arm: Don't include common.h in header files")
Signed-off-by: Martin Fuzzey <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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