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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
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The Sige1 is a single board computer developed by ArmSoM, based on the
Rockchip RK3528A SoC.
Add initial device tree for the ArmSoM Sige1 board.
Signed-off-by: Jonas Karlman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 1c6b12ef9575bc18dad2393e50ca1ebf96f0a0c8 ]
(cherry picked from commit 3ba04aa78ba71faab4a339f5ab15bc81a3e0a51b)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The ROCK 2A and ROCK 2F is a high-performance single board computer
developed by Radxa, based on the Rockchip RK3528A SoC.
Add initial device tree for the Radxa ROCK 2A and ROCK 2F boards.
Signed-off-by: Jonas Karlman <[email protected]>
Tested-by: Yao Zi <[email protected]>
Reviewed-by: Nicolas Frattaroli <[email protected]>
Tested-by: Nicolas Frattaroli <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 5b71b3d9aa61626d6a93ed2f761a748aa2ecfa95 ]
(cherry picked from commit d272bc0c747a5af49cf98140ebd25a702f84ab52)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
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The bootloader for RK3588 Tiger currently forces the PMIC reset behavior
(stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X
which is incorrect for our devices.
It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.
Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.
Signed-off-by: Quentin Schulz <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: e82f642b9821384045915dc30e73df7de8424827 ]
(cherry picked from commit d9c568906be166834f4f977bc7f704176bac5b8a)
Reviewed-by: Kever Yang <[email protected]>
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The bootloader for RK3588 Jaguar currently forces the PMIC reset
behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC)
to 0b1X which is incorrect for our devices.
It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.
Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.
Signed-off-by: Quentin Schulz <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: ee907113430aa02a8202c91bb574c385ecc28aa2 ]
(cherry picked from commit 8bd14566b75f9409de703a0d2f9a0704b71a7ebe)
Reviewed-by: Kever Yang <[email protected]>
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To make it easier to read the device tree, let's add constants for the
rockchip,reset-mode property values that are currently only applicable
to RK806 PMIC.
Signed-off-by: Quentin Schulz <[email protected]>
[dt-maintainers did not consider this part of the binding, so we're
keeping the header in the devicetree directory]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 304be20e65ca08fc2e9cb58eb939a0054d8a8b81 ]
(cherry picked from commit 0e417bfcbc385c127c7f5ea01df6289aed8325c2)
Reviewed-by: Kever Yang <[email protected]>
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
Perform a few fixups in our dts* files to match upstream changes.
Signed-off-by: Tom Rini <[email protected]>
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Quentin Schulz <[email protected]> says:
Due to updates to the Device Tree (migrating to onboard USB hub nodes
instead of (badly) hacking things with a gpio regulator that doesn't
actually work properly), we now need to enable the onboard USB hub
driver in U-Boot.
This anticipates upcoming breakage when 6.16 DT will be merged into
U-Boot's dts/upstream.
The series can be applied as is before v6.16 DT is merged or only the
defconfig changes after 6.16 DT has been merged.
The last two patches are simply to avoid probing devices that aren't
actually routed on RK3399 Puma, which is nice to have but doesn't fix
anything.
Note that this depends on the following series:
https://lore.kernel.org/u-boot/20250722-usb_onboard_hub_cypress_hx3-v4-0-91c3ee958c0e@thaumatec.com/
Link: https://lore.kernel.org/r/[email protected]
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Puma with Haikou
The u2phy0_host port is the part of the USB PHY0 (namely the
HOST0_DP/DM lanes) which routes directly to the USB2.0 HOST
controller[1]. The other lanes of the PHY are routed to the USB3.0 OTG
controller (dwc3), which we do use.
The HOST0_DP/DM lanes aren't routed on RK3399 Puma so let's simply
disable the USB2.0 controllers.
USB3 OTG has been known to be unstable on RK3399 Puma Haikou for a
while, one of the recurring issues being that only USB2 is detected and
not USB3 in host mode. Reading the justification above and seeing that
we are keeping u2phy0_host in the Haikou carrierboard DTS probably may
have bothered you since it should be changed to u2phy0_otg. The issue is
that if it's switched to that, USB OTG on Haikou is entirely broken. I
have checked the routing in the Gerber file, the lanes are going to the
expected ball pins (that is, NOT HOST0_DP/DM).
u2phy0_host is for sure the wrong part of the PHY to use, but it's the
only one that works at the moment for that board so keep it until we
figure out what exactly is broken.
No intended functional change.
[1] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf
Chapter 2 USB2.0 PHY
Fixes: 2c66fc34e945 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM")
Signed-off-by: Quentin Schulz <[email protected]>
Signed-off-by: Lukasz Czechowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: febd8c6ab52c683b447fe22fc740918c86feae43 ]
(cherry picked from commit 0a0ebebfdd4558512675e1aff34bddb770086cb0)
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The u2phy1_host port is the part of the USB PHY1 (namely the
HOST1_DP/DM lanes) which routes directly to the USB2.0 HOST
controller[1]. The other lanes of the PHY are routed to the USB3.0 OTG
controller (dwc3), which we do use.
The HOST1_DP/DM lanes aren't routed on RK3399 Puma so let's simply
disable the USB2.0 controllers and associated part in USB2.0 PHY.
No intended functional change.
[1] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf
Chapter 2 USB2.0 PHY
Fixes: 2c66fc34e945 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM")
Signed-off-by: Quentin Schulz <[email protected]>
Signed-off-by: Lukasz Czechowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 3373af1d76bacd054b37f3e10266dd335ce425f8 ]
(cherry picked from commit 97640da1f41d022484c1a4725bed943a5ae56073)
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Currently, the onboard Cypress CYUSB3304 USB hub is not defined in
the device tree, and hub reset pin is provided as vcc5v0_host
regulator to usb phy. This causes instability issues, as a result
of improper reset duration.
The fixed regulator device requests the GPIO during probe in its
inactive state (except if regulator-boot-on property is set, in
which case it is requested in the active state). Considering gpio
is GPIO_ACTIVE_LOW for Puma, it means it’s driving it high. Then
the regulator gets enabled (because regulator-always-on property),
which drives it to its active state, meaning driving it low.
The Cypress CYUSB3304 USB hub actually requires the reset to be
asserted for at least 5 ms, which we cannot guarantee right now
since there's no delay in the current config, meaning the hub may
sometimes work or not. We could add delay as offered by
fixed-regulator but let's rather fix this by using the proper way
to model onboard USB hubs.
Define hub_2_0 and hub_3_0 nodes, as the onboard Cypress hub
consist of two 'logical' hubs, for USB2.0 and USB3.0.
Use the 'reset-gpios' property of hub to assign reset pin instead
of using regulator. Rename the vcc5v0_host regulator to
cy3304_reset to be more meaningful. Pin is configured to
output-high by default, which sets the hub in reset state
during pin controller initialization. This allows to avoid double
enumeration of devices in case the bootloader has setup the USB
hub before the kernel.
The vdd-supply and vdd2-supply properties in hub nodes are
added to provide correct dt-bindings, although power supplies are
always enabled based on HW design.
Fixes: 2c66fc34e945 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM")
Cc: [email protected] # 6.6
Cc: [email protected] # Backport of the patch in this series fixing product ID in onboard_dev_id_table in drivers/usb/misc/onboard_usb_dev.c driver
Signed-off-by: Lukasz Czechowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: d7cc532df95f7f159e40595440e4e4b99481457b ]
(cherry picked from commit 0fe42d171081426ab119ca5c0eb130e5f3a9a805)
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v6.16-rc1 DT"
Quentin Schulz <[email protected]> says:
v6.16-rc1 will bring an incompatible change to the Device Tree of PX30
Ringneck which will break Ethernet support.
Unfortunately, the designware net driver's logic doesn't seem to allow
having the old Device Tree (without MDIO bus and Ethernet PHY nodes)
with DM_MDIO and DM_ETH_PHY enabled so there cannot be a smooth
transition.
Since this is going to bite me in a few months time, let's just break
and fix it now in a couple of commits so I don't have to think about it
later :)
This can be cleanly applied on master or next, I have absolutely zero
preference on the branch this should be merged in (my opinion is that
it's too late in the 2024.07 cycle to bring this in :) ).
Link: https://lore.kernel.org/r/[email protected]
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Using snps,reset-* properties to handle the ethernet-phy resets is
deprecated and instead a real phy node should be used.
Move the Ringneck phy-reset properties to such a node
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Tested-by: Quentin Schulz <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: e463625af7f92c4a9f097f7fb87f6baaad6e762a ]
(cherry picked from commit 76d0d8e00c9ac845ca8d6cbe191cf015ca3a8c16)
Reviewed-by: Sumit Garg <[email protected]>
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Using snps,reset-* properties for handling the phy-reset is deprecated
and instead a real phy node should be defined that then contains the
reset-gpios handling.
To facilitate this, add the core mdio node under the px30's gmac, similar
to how the other Rockchip socs already do this.
Signed-off-by: Heiko Stuebner <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: ede4837a504ca7e5811217060aa8300b8d0cf7f2 ]
(cherry picked from commit cb54a264ecdb9e95b1529e4542e157cb9acded30)
Reviewed-by: Sumit Garg <[email protected]>
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
Signed-off-by: Tom Rini <[email protected]>
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As the name implies, it is built around the RK3576 SoC with 4x Cortex-A72
cores, four Cortex-A53 cores and Mali-G52 MC3 GPU.
Storage options are EMMC, SD-Card, a 2242 M.2 slot and the possibility to
use UFS 2.0 storage.
Video Output options are a HDMI port, a DSI connector as well as Display-
Port via the TypeC connector (all of them not yet supported).
Networking options are a Low-profile Gigabit Ethernet RJ45 port with
Motorcomm YT8531 PHY as well as WiFi via an AMPAK AP6256 module.
USB ports on the board are 1x USB 3.0 port, 1x USB 2.0 port, 1x USB Type-C
and it comes with 40-pin GPIO header
Signed-off-by: Heiko Stuebner <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[ upstream commit: 887ff17cdd8f088a52e2b61e71f2b6c9b9678de6 ]
(cherry picked from commit 388e7272d092bd20e414cd408bac39d8fd02d765)
Reviewed-by: Kever Yang <[email protected]>
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This adds the otp node to the rk3576 soc devicetree including the
individual fields we know about.
Tested-by: Nicolas Frattaroli <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[ upstream commit: 8715d2eeb062f6859c252bb6c87b363230b66e9f ]
(cherry picked from commit d67cf6de8aacb4abcdfb516eeb8a511a4a657bc1)
Reviewed-by: Kever Yang <[email protected]>
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The Radxa E20C may come with an onboard eMMC (8GB / 16GB / 32GB / 64GB).
Enable support for the onboard eMMC on Radxa E20C.
Signed-off-by: Jonas Karlman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 3a01b5f14a8ae2d45aea5aeed30001ac1655de86 ]
(cherry picked from commit bd4c8a1c08f92d863d89c0ddff59e5f5bc6a1e34)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user
button.
Add support for the maskrom button using a adc-keys node, also add the
regulators used by SARADC controller.
Signed-off-by: Jonas Karlman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 3a2819ee9c71d1c6388e456cc4eb042914d15d7e ]
(cherry picked from commit 460ef5b623e5fa69843305faf50f6b1a8e81e1cd)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user
button.
Add support for the user button using a gpio-keys node.
Signed-off-by: Jonas Karlman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: ad8afc8813567994164f2720189c819da8c22b99 ]
(cherry picked from commit 6793b56b79df26ab3323e5293b97577d0786ddb3)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Radxa E20C has three gpio controlled leds (sys, wan and lan).
Add led nodes and set default trigger to heartbeat for the sys led and
netdev for the lan and wan leds.
Signed-off-by: Jonas Karlman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 6a709e003492e9878d5f1357be0b2e1162e1e6a6 ]
(cherry picked from commit a3556ede6b48c7760ac3608ad77601fca26d2ce0)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Radxa E20C route UART0 M0 pins (GPIO4_C7 and GPIO4_D0) to the onboard
CH340B for debug console use.
Add pinctrl for UART0 M0 pins used for serial console.
Signed-off-by: Jonas Karlman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 0d2312f0d3e4ce74af0977c1519a07dfc71a82ac ]
(cherry picked from commit 9bcf6ccdd87c3be48fe7d75150c6e403c5c0a42d)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The SDHCI controller in Rockchip RK3528 is similar to the one included
in RK3588.
Add device tree node for the SDHCI controller in RK3528.
Signed-off-by: Jonas Karlman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: a98cc47f79ab5b8059b748bf0bd59335edfff7d9 ]
(cherry picked from commit db7a99c423dea0ead19d6a18053d898a762a3b48)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add a device tree node for the SARADC controller used by RK3528.
Signed-off-by: Jonas Karlman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 6e58302c84ce90aadbecd41efe1f69098a6f91e5 ]
(cherry picked from commit 8ba64ba5cb301bca777ba7f0d2a2a72f49af5ff2)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Same as RK3568, RK3528 uses SCMI clk instead of ARMCLK.
Add SCMI clk for CPU, GPU and RNG will also use it.
Signed-off-by: Chukun Pan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: fbcbc1fb93e14729bd87ab386b7f62694dcc8b51 ]
(cherry picked from commit 6e03c7e28e2d929a420809a24b0379305a9fb86a)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The Quality-of-Service (QsS) node stores/restores specific
register contents when the power domains is turned off/on.
Add QoS node so that they can connect to the power domain.
Signed-off-by: Chukun Pan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 61a05d8ca3030a544175671f5fab7a8f29c24085 ]
(cherry picked from commit 9ee90dfd6957fcc42ea94c43d195b01d1b286713)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi
from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node
removed due to missing label reference to pcfg_output_low_pull_down.
Signed-off-by: Jonas Karlman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: a31fad19ae39ea27b5068e3b02bcbf30a905339b ]
(cherry picked from commit 89a24fa2e923b68a42ccc8cc9cb2d5bdf291ac40)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add missing clocks in UART nodes for RK3528 SoC.
Signed-off-by: Yao Zi <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: b9454434d0349223418f74fbfa7b902104da9bc5 ]
(cherry picked from commit 12f69f638472dc9cf1b62816c7d4407de1846d12)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is
generated by internal Ethernet phy, a fixed clock node is added as a
placeholder to avoid orphans.
Signed-off-by: Yao Zi <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 858cdcdd11cf9913756297d3869e4de0f01329ea ]
(cherry picked from commit 60741472b42e92d2393327cb70669ab90e3b382f)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add the RK3588's standalone hardware random number generator node to its
device tree, and enable it.
Signed-off-by: Nicolas Frattaroli <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[changed reset-id to its numeric value while the constant makes its
way through the crypto tree]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 6ee0b9ad3995ee5fa229035c69013b7dd0d3634b ]
(cherry picked from commit 4800c4aaad00ffdc053850f130e8504a04dd110d)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
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BootROM leave GPIO4_D6 configured as SDMMC_PWREN function and DW MCI
driver set PRWEN high on MMC_POWER_UP and low on MMC_POWER_OFF.
Similarly U-Boot also set PRWEN high before accessing mmc.
However, HW revision prior to v1.2 must pull GPIO4_D6 low to access
sdmmc. For HW revision v1.2 the state of GPIO4_D6 has no impact.
Model an always-on active low fixed regulator using GPIO4_D6 to fix
use of sdmmc on older HW revisions of the board.
Fixes: adeb5d2a4ba4 ("arm64: dts: rockchip: Add Radxa ROCK S0")
Signed-off-by: Jonas Karlman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 26c100232b09ced0857306ac9831a4fa9c9aa231 ]
(cherry picked from commit ca8e0bedbc790b19b11efc223677d178b8eeb74e)
Signed-off-by: Jonas Karlman <[email protected]>
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
[rockchip fixes from Jonas Karlman via IRC]
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Radxa ROCK 5C is a 8K computer for everything[1] using the Rockchip
RK3588S2 chip:
- Rockchip RK3588S2
- Quad A76 and Quad A55 CPU
- 6 TOPS NPU
- up to 32GB LPDDR4x RAM
- eMMC / SPI flash connector
- Micro SD Card slot
- Gigabit ethernet port (supports PoE with add-on PoE HAT)
- WiFi6 / BT5.4
- 1x USB 3.0 Type-A HOST port
- 1x USB 3.0 Type-A OTG port
- 2x USB 2.0 Type-A HOST port
- 1x USB Type-C 5V power port
[1] https://radxa.com/products/rock5/5c
Signed-off-by: FUKAUMI Naoki <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 3ddf5cdb77e6efd6fe9b70f36dec935e324a3cd2 ]
(cherry picked from commit f80689fcef4b9b07a97b629b4075cc1a4c21a68e)
Reviewed-by: Kever Yang <[email protected]>
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Add support for the HDMI0 output port found on RK3588 SoC.
Signed-off-by: Cristian Ciocaltea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: d7bb71e69f58c1b3665a9f926bf8d3855111bf8e ]
(cherry picked from commit a839348380c2072e00a26bbdb80744982fe04c56)
Reviewed-by: Kever Yang <[email protected]>
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These pinctrls manage the low-speed PCIe signals:
- CLKREQ#: An output on the RK3588 (both RC or EP modes), used to
request that external clock-generation circuitry provide a clock.
- PERST#: An input on the RK3588 in EP mode, used to detect a reset
signal from the RC. In RC mode, the hardware does not use this signal:
Linux itself generates it by putting the pin in GPIO mode.
- WAKE#: In EP mode, this is an output; in RC mode, this is an input.
Each of these signals serves a distinct purpose, and more importantly,
PERST# should not be muxed when the RK3588 is in the RC role. Bundling
them together in pinctrl groups prevents proper use: indeed, almost none
of the current board-specific .dts files make any use of them.
(Exception: Rock 5A recently had a patch land that misuses _pins; this
patch corrects that.)
However, on some RK3588 boards, the PCIe 3 controller will indefinitely
stall the boot if CLKREQ# is not muxed (details in the next patch).
This patch unbundles the signals to allow them to be used.
Signed-off-by: Sam Edwards <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 4294e32111781b3de4d73b944cbd1bc1662a9a7a ]
(cherry picked from commit 8713425fa162b61bcf5f7a6dcd171fddfb12be36)
Reviewed-by: Kever Yang <[email protected]>
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Typically any non-removable storage (emmc) is listed before removable
storage (sd-card) options. Also U-Boot will try to override and use
mmc0=sdhci and mmc1=sdmmc0 for all rk356x boards.
Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <[email protected]>
Signed-off-by: Tianling Shen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: b7cd1115456d312f8c5e60c80fdc35fd35ea6eab ]
Signed-off-by: Tianling Shen <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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It is required to boot from eMMC without additional patch in u-boot.
Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <[email protected]>
Signed-off-by: Tianling Shen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 1b5365034410f1ca21adadadd492b99bdf4f2c55 ]
Signed-off-by: Tianling Shen <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The status prop is typically the last prop.
Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <[email protected]>
Signed-off-by: Tianling Shen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 17e150fdd983c7e59b9240e34a166285f3c3fb39 ]
Signed-off-by: Tianling Shen <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Replace deprecated snps,reset props and move them to the PHY node.
Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <[email protected]>
Signed-off-by: Tianling Shen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 82b2868937883b65732da498b26366d34db61510 ]
Signed-off-by: Tianling Shen <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Use the marketing name for model name, this matches the dt-binding.
Also update the website url in copyright.
Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
Suggested-by: Jonas Karlman <[email protected]>
Signed-off-by: Tianling Shen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: b5bf84206a5c77528f9dd4cbca4e72caa063c102 ]
Signed-off-by: Tianling Shen <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
Ethernet ports designed and developed by FriendlyElec for IoT
applications.
Specification:
- Rockchip RK3566
- 2GB LPDDR4X RAM
- optional 32GB eMMC module
- SD card slot
- 2x 1000 Base-T
- 3x LEDs (POWER, LAN, WAN)
- 2x Buttons (Reset, MaskROM)
- 1x USB 3.0 Port
- Type-C 5V 2A Power
Signed-off-by: Tianling Shen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 50decd493c8394c52d04561fe4ede34df27a46ba ]
Signed-off-by: Tianling Shen <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
Based on what "git diff" suggests, rename a device tree for
imx8mm_venice_defconfig and imx8mp_venice_defconfig
Signed-off-by: Tom Rini <[email protected]>
---
Cc: Tim Harvey <[email protected]>
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The R2S Plus is basically an R2S with additional eMMC.
The eMMC configuration for the DTS has been extracted and copied from
rk3328-nanopi-r2.dts, v2017.09 branch from the friendlyarm/uboot-rockchip
repository.
Signed-off-by: Sergey Bostandzhyan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: b8c02878292200ebb5b4a8cfc9dbf227327908bd ]
(cherry picked from commit c9bf98827964441f4dd16faa45bd4046f472e693)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Cool Pi CM5 GenBook works as a carrier board connect with CM5 [0].
Specification:
- Rockchip RK3588
- LPDDR5X 8/32 GB
- eMMC 64 GB
- HDMI Type A out x 1
- USB 3.0 Host x 1
- USB-C 3.0 with DisplayPort AltMode
- PCIE M.2 E Key for RTL8852BE Wireless connection
- PCIE M.2 M Key for NVME connection
- eDP panel with 1920x1080
This patch add basic support to bringup eMMC/USB HOST/WiFi/TouchPad/
Battery/PCIE NVME, and can also drive a HDMI output with out of tree
hdmi patches.
[0] https://www.crowdsupply.com/shenzhen-tianmao-technology-co-ltd/genbook-rk3588
Signed-off-by: Andy Yan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 4a8c1161b843c366776fc872a6fe45b743b2983e ]
(cherry picked from commit dc6316da23734d9321e09f8c8a7669f4b4cb9f75)
Reviewed-by: Kever Yang <[email protected]>
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The device contains two i2c-connected eeproms holding some product-
specific values. One sitting on the mainboard and one on the statically
connected backplane.
While the eeprom chips themself have a size of 512 byte, the eeprom data
only uses 256 byte each, probably to stay compatible with other models.
Signed-off-by: Heiko Stuebner <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[ upstream commit: da6f4130234448122fe3e66c8116f7d9eea8a5c7 ]
(cherry picked from commit 0b3109708caf5002ba188ae28eae9ce46b2c39b4)
Reviewed-by: Kever Yang <[email protected]>
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Contrary to the vendor-kernel the pmu-io-domains are not enabled by
default. This resulted in the value not being set according to the
regulator, which in turn made the gmac0 interface that is connected
to the vccio4 supply inoperable.
Fixes: 64b7f16fb394 ("arm64: dts: rockchip: add 2 pmu_io_domain supplies for Qnap-TS433")
Signed-off-by: Heiko Stuebner <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[ upstream commit: 40cc4257169712f0ae3835820a4c5afbdd1a16ff ]
(cherry picked from commit f509fcb1fb82117e551b489592ac5714a6c5cd8d)
Reviewed-by: Kever Yang <[email protected]>
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While it requires to have the right phy driver loaded (i.e. motorcomm)
to make the phy asserting the right delays, this is generally the
preferred way to define the MAC <-> PHY connection.
Signed-off-by: Uwe Kleine-König <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: e8d45544f806f3b55c30345de84262cbb9504902 ]
(cherry picked from commit e0bbe061fd537bd7b113c53eb046bbcbf0e6597d)
Reviewed-by: Kever Yang <[email protected]>
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