summaryrefslogtreecommitdiff
path: root/include/asm-ppc/config.h
AgeCommit message (Collapse)Author
2010-04-13Move architecture-specific includes to arch/$ARCH/include/asmPeter Tyser
This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <[email protected]>
2010-04-0785xx: Added various P1012/P1013/P1021/P1022 definesKumar Gala
There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list * Added number of LAWs for P1012/P1013/P1021/P1022 * Set CONFIG_MAX_CPUS to 2 for P1021/P1022 * PCI port config Signed-off-by: Haiying Wang <[email protected]> Signed-off-by: Srikanth Srinivasan <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2010-01-21lmb: only force on arches that use itMike Frysinger
Signed-off-by: Mike Frysinger <[email protected]>
2010-01-05ppc/85xx: Add tracking of TLB CAM usageKumar Gala
We need to track which TLB CAM entries are used to allow us to "dynamically" allocate entries later in the code. For example the SPD DDR code today hard codes which TLB entries it uses. We can now make that pick entries that are free. Signed-off-by: Kumar Gala <[email protected]>
2010-01-05NET: Base support for etsec2.0Kumar Gala
1. Modified the tsec_mdio structure to include the new regs 2. Modified the MDIO_BASE_ADDR so that it will handle both older version and new version of etsec. Signed-off-by: Sandeep Gopalpet <[email protected]> Acked-by: Kim Phillips <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2009-10-2785xx: MP Boot Page Translation updatePeter Tyser
This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2009-10-03ppc: Enable full relocation to RAMPeter Tyser
The following changes allow U-Boot to fully relocate from flash to RAM: - Remove linker scripts' .fixup sections from the .text section - Add -mrelocatable to PLATFORM_RELFLAGS for all boards - Define CONFIG_RELOC_FIXUP_WORKS for all boards Previously, U-Boot would partially relocate, but statically initialized pointers needed to be manually relocated. Signed-off-by: Peter Tyser <[email protected]>
2009-09-24ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala
There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala <[email protected]>
2009-08-2885xx: Added CONFIG_MAX_CPUS for P1020Poonam Aggrwal
Signed-off-by: Poonam Aggrwal <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2009-08-288xxx: Removed CONFIG_NUM_CPUS from 85xx/86xxPoonam Aggrwal
The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2009-07-17ppc: Fix compile error for boards with CONFIG_DDR_ECCPeter Tyser
A bug was introduced by commit e94e460c6e8741f42dab6d8dd4b596ba5d9d79ae which affected non-MPC83xx/85xx/86xx ppc boards which had CONFIG_DDR_ECC defined and resulted in errors such as: Configuring for canyonlands board... fsl_dma.c:50:2: error: #error "Freescale DMA engine not supported on your processor" make[1]: *** No rule to make target `.depend', needed by `libdma.a'. Stop. Signed-off-by: Peter Tyser <[email protected]>
2009-07-0283xx: Add support for fsl_dma driverPeter Tyser
Signed-off-by: Peter Tyser <[email protected]> Reviewed-by: Ira W. Snyder <[email protected]> Tested-by: Ira W. Snyder <[email protected]> Acked-by: Kim Phillips <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2009-07-018xxx: Break out DMA code to a common filePeter Tyser
DMA support is now enabled via the CONFIG_FSL_DMA define instead of the previous CONFIG_DDR_ECC Signed-off-by: Peter Tyser <[email protected]> Signed-off-by: Kumar Gala <[email protected]>
2009-02-23MPC86xx: set CONFIG_MAX_MEM_MAPPED to 2G by defaultBecky Bruce
Currently, we get 256MB as the default, but since all the 86xx board configs define a 2G BAT mapping for RAM, raise default to 2G. Signed-off-by: Becky Bruce <[email protected]> Acked-by: Jon Loeliger <[email protected]>
2009-02-1685xx: Fix how we map DDR memoryKumar Gala
Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: Kumar Gala <[email protected]>
2009-02-12ppc4xx: Fix problem with CONFIG_MAX_MEM_MAPPED in include/asm-ppc/config.hStefan Roese
CONFIG_SDRAM_PPC4xx_IBM_DDR2 is not set when include/asm-ppc/config.h is included. So for katmai, CONFIG_MAX_MEM_MAPPED will get set to 256MB. It makes perfect sense to set CONFIG_MAX_MEM_MAPPED to 2GB for all PPC4xx boards right now. Signed-off-by: Stefan Roese <[email protected]>
2009-02-10ppc: Move CONFIG_MAX_MEM_MAPPED to common config.hKumar Gala
Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent between the two current users (lib_ppc/board.c, 44x SPD DDR2). Signed-off-by: Kumar Gala <[email protected]> Acked-by: Stefan Roese <[email protected]>
2009-02-10Add an architecture specific config.h for common definesKumar Gala
We have common defines that we duplicate in various ways. Having an arch specific config.h gives us a common location for those defines. Eventually we should be able to replace this when we have proper Kconfig support. Signed-off-by: Kumar Gala <[email protected]>
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-15 04:21:32 +0000