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Signed-off-by: Michal Simek <[email protected]>
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Signed-off-by: Michal Simek <[email protected]>
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MPC837XEMDS boards can support PCI-E via "PCI-E riser card". The card
provides two PCI-E (x2) ports. Though, only one port can be used in x2
mode. Two ports can function simultaneously in x1 mode.
PCI-E x1/x2 modes can be switched via "pex_x2" environment variable.
Signed-off-by: Anton Vorontsov <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
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MPC8315ERDB boards features PCI-E x1 and Mini PCI-E x1 ports. Let's
support them.
Signed-off-by: Anton Vorontsov <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
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This patch adds esd's loadpci BSP command to CPCI4052 and
CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM.
Signed-off-by: Matthias Fuchs <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)
- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.
Signed-off-by: Haiying Wang <[email protected]>
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Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately. This makes the code easier to read
and understand, and facilitates mapping changes going forward.
Signed-off-by: Becky Bruce <[email protected]>
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Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately. This makes the code easier to read
and understand, and facilitates mapping changes going forward.
Signed-off-by: Becky Bruce <[email protected]>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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Signed-off-by: Peter Tyser <[email protected]>
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The values given for the PHY address were wrong, so the code
read no valid PHY ID, and fell through to the generic PHY
support, which would work on 1000M but would not auto negotiate
down to 100M or 10M.
Signed-off-by: Paul Gortmaker <[email protected]>
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Lets make things a bit more user friendly. It isn't 1985 anymore.
Signed-off-by: Paul Gortmaker <[email protected]>
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These interfaces don't have usable connectors on the board, so don't
bother enumerating or configuring them.
Signed-off-by: Paul Gortmaker <[email protected]>
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Initial support for Extreme Engineering Solutions XPedite5370 -
a MPC8572-based 3U VPX single board computer with a PMC/XMC
site.
Signed-off-by: Peter Tyser <[email protected]>
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Conflicts:
board/atmel/atngw100/atngw100.c
board/atmel/atstk1000/atstk1000.c
cpu/at32ap/at32ap700x/gpio.c
include/asm-avr32/arch-at32ap700x/clk.h
include/configs/atngw100.h
include/configs/atstk1002.h
include/configs/atstk1003.h
include/configs/atstk1004.h
include/configs/atstk1006.h
include/configs/favr-32-ezkit.h
include/configs/hammerhead.h
include/configs/mimc200.h
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Shinya Kuribayashi <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Peter Tyser <[email protected]>
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Also fix some minor typos.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
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This patch fixes building U-Boot for CPCI405 boards.
Signed-off-by: Matthias Fuchs <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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---
Microblaze platforms use generic settings and to have
many platforms is confusing that's why I decided to remove this
platform from U-BOOT. ml401 tree is sufficient for covering
all Microblaze platforms.
This change will go through microblaze custodian tree.
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Signed-off-by: Michal Simek <[email protected]>
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Signed-off-by: Niklaus Giger <[email protected]>
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Use the GNU 'date' command to auto-generate a new U-Boot
timestamp on every compile.
Signed-off-by: Peter Tyser <[email protected]>
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This patch adds the possiblity to choose the media where the environment will
be located. This allow to choose this fundamental configuration without editing
config files.
Documentation file added.
Signed-off-by: Nicolas Ferre <[email protected]>
Acked-by: Stelian Pop <[email protected]>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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The default DDR freq is 400MHz or 800M data rate,
the old settings is pure wrong for the default case.
Signed-off-by: Dave Liu <[email protected]>
Acked-by: Andy Fleming <[email protected]>
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The BR_PHYS_ADDR macro is useful on all machines that have local bus
which is pretty much all 83xx/85xx/86xx chips.
Additionally most 85xx & 86xx will need it if they want to support
36-bit physical addresses.
Signed-off-by: Kumar Gala <[email protected]>
Acked-by: Andy Fleming <[email protected]>
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Prevent further viral propogation of the unused
symbol CONFIG_L1_INIT_RAM by just removing it.
Signed-off-by: Jon Loeliger <[email protected]>
Acked-by: Andy Fleming <[email protected]>
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The DDR controller of 8548/8544/8568/8572/8536 processors
have the ECC data init feature, and the new DDR code is
using the feature, and we don't need the way with DMA to
init memory any more.
Signed-off-by: Dave Liu <[email protected]>
Acked-by: Andy Fleming <[email protected]>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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Prevent further viral propogation of the unused
symbol CONFIG_L1_INIT_RAM by just removing it.
Signed-off-by: Jon Loeliger <[email protected]>
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Introducing 64-bit (36-bit) support for the MPC8641HPCN
failed to accomodate the other two 86xx boards.
Introduce definitions for CONFIG_SYS_CCSRBAR_PHYS_{LOW,HIGH}
CONFIG_SYS_CCSR_DEFAULT_DBAT{U,L} and CONFIG_SYS_CCSR_DEFAULT_IBAT{U,L}
with nominal 32-bit values.
Signed-off-by: Jon Loeliger <[email protected]>
Acked-by: Becky Bruce <[email protected]>
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This patch disables some unused features from the PCI405 configuration
to keep U-Boot image size below 192k.
Signed-off-by: Matthias Fuchs <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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