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Signed-off-by: Roy Zang <[email protected]>
Acked-by: Jon Loeliger <[email protected]>
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Signed-off-by: Heiko Schocher <[email protected]>
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This patch makes the sequoia board use the generic usb-ohci driver
instead of cpu/ppc4xx/usb_ohci.c.
Signed-off-by: Matthias Fuchs <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Kyungmin Park <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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Add cfb console support to FSL 8610 DIU driver.
Inspect board version from PIXIS to obtain correct pixel format.
Use #define CONFIG_VIDEO in config file to enable fb console.
To switch monitor, set monitor variable to
0 - DVI, 1 - Single link LVDS, 2 - Double link LVDS
followed by "diufb init".
Preserve logo bitmap at the top of the fb console.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Jon Loeliger <[email protected]>
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1280x1024 and 1024x768 @ 32 bpp are supported now.
DVI, Single-link LVDS, Double-link LVDS are all supported.
Environmental variable "monitor" is used to specify monitor port.
A new command "diufb" is introduced to reinitialize monitor
and display a BMP file in the memory. So far, 1-bit, 4-bit,
8-bit and 24-bit BMP formats are supported.
diufb init
- initialize the diu driver
Enable the port specified in the environmental variable "monitor"
diufb addr
- display bmp file in memory.
The bmp image should be no bigger than the resolution, 1280x1024
for DVI and double-link LVDS, 1024x768 for single-link LVDS.
Note, this driver allocate memory but doesn't free it after use
It is written on purpose -- to avoid a failure of reallocation
due to memory fragement.
ECC of DDR is disabled for DIU performance. L2 data cache is also disabled.
Signed-off-by: York Sun <[email protected]>
Signed-off-by: Jon loeliger <[email protected]>
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One may #define ENV_DEBUG to get them back again.
Signed-off-by: York Sun <[email protected]>
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Signed-off-by: Jason Jin <[email protected]>
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The address in the BAT register is aligned with the BAT size.
The original definition actually did not define BAT for PCIE2 IO.
This patch fix this.
Signed-off-by: Jason Jin <[email protected]>
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Basically, refactor the CFG_PIXIS_VBOOT_MASK values
into the separate board config files.
Signed-off-by: Jason Jin <[email protected]>
Signed-off-by: Jon Loeliger <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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The configuration file has already enabled USB, but it
missed definition of CFG_OHCI_SWAP_REG_ACCESS, the USB
on MPC8641HPCN can not work because of the wrong USB
register endian.
And add the USB command to U-Boot commands list.
Signed-off-by: Zhang Wei <[email protected]>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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To get the IDS8247 board working following are done:
- FCC2 is deactivated
- FCC1 is activated
- I2C is activated
- CFI driver is activated
- Adapted for use with LIBFDT
Signed-off-by: Sergej Stepanov <[email protected]>
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This patch adds NAND booting support for the AMCC 405EX(r) eval boards.
Again, only one image supports both targets.
Signed-off-by: Stefan Roese <[email protected]>
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Wolfgang is right: It's not a good idea to set up default initial
ethernet addresses for a board, even though they belong to the local
range.
This will change the failure mode from "IT manager screams at you for
using duplicate ethernet addresses" to a nice error message explaining
that the ethernet address hasn't been set properly.
Signed-off-by: Haavard Skinnemoen <[email protected]>
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All 4xx board config files don't need the cache definitions anymore.
These are now defined in common headers.
Signed-off-by: Stefan Roese <[email protected]>
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The Haleakala is nearly identical with the Kilauea eval board. The only
difference is that the 405EXr only supports one EMAC and one PCIe
interface. This patch adds support for the Haleakala board by using
the identical image for Kilauea and Haleakala. The distinction is done
by comparing the PVR.
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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On Yucca & Katmai, the inbound memory map pointed to 0x4.0000.0000, which
is the internal SRAM. Since I now ported and tested this endpoint mode
on Kilauea successfully to map to 0 (SDRAM), I also changed this for
Katmai.
Yucca will stay at internal SRAM for now. Not sure if somebody relies on
this setup.
Signed-off-by: Stefan Roese <[email protected]>
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This patch adds support for dynamic configuration of PCIe ports for the
AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
boards Yucca & Katmai and the 405EX board Kilauea.
This dynamic configuration is done via the "pcie_mode" environement
variable. This variable can be set to "EP" or "RP" for endpoint or
rootpoint mode. Multiple values can be joined via the ":" delimiter.
Here an example:
pcie_mode=RP:EP:EP
This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
as endpoint.
Per default Yucca will be configured as:
pcie_mode=RP:EP:EP
Per default Katmai will be configured as:
pcie_mode=RP:RP:REP
Per default Kilauea will be configured as:
pcie_mode=RP:RP
Signed-off-by: Tirumala R Marri <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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This patch enables the fdt support on the AMCC Kilauea eval board.
Additionally now EBC ranges fdt fixup is included to support NOR
FLASH mapping via the Linux physmap_of driver.
This Kilauea port now support booting arch/ppc and arch/powerpc
Linux kernels. The default environment "net_nfs" is for arch/ppc
and "net_nfs_fdt" is for arch/powerpc. In the long run, arch/ppc
support will be removed.
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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128MB seems to be the smallest possible value for the memory size
for on PCIe port. With this change now the BAR's of the PCIe cards
are accessible under U-Boot.
One big note: This only works for PCIe port 0 & 1. For port 2 this
currently doesn't work, since the base address is now 0xc0000000
(0xb0000000 + 2 * 0x08000000), and this is already occupied by
CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean
to change the base addresses completely and this change would have
too much impact right now.
This patch adds debug output to the 4xx pcie driver too.
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: TsiChungLiew <[email protected]>
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Signed-off-by: TsiChungLiew <[email protected]>
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Signed-off-by: TsiChungLiew <[email protected]>
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Signed-off-by: TsiChungLiew <[email protected]>
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Signed-off-by: Bartlomiej Sieka <[email protected]>
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With this patch PSC3 is configured as UART. This is done, because if
the pins of PSC3 are not configured at all (-> all pins are GPI),
due to crosstalk, spurious characters may be send over the RX232_2_TXD
signal line.
Signed-off-by: Martin Krause <[email protected]>
Signed-off-by: Grant Likely <[email protected]>
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With this patch PSC3 is configured as UART. This is done, because if
the pins of PSC3 are not configured at all (-> all pins are GPI),
due to crosstalk, spurious characters may be send over the RX232_2_TXD
signal line.
Signed-off-by: Martin Krause <[email protected]>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
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