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Move PHYLIB from board config to defconfig
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The SR1500 board is a CycloneV based board, similar to the EBV
SoCrates, equipped with the following devices:
- SPI NOR
- eMMC
- Ethernet
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Acked-by: Pavel Machek <[email protected]>
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Enable USB XHCI support for ZynqMP
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
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Added USB XHCI driver support for zynqmp.
Signed-off-by: Siva Durga Prasad Paladugu <[email protected]>
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This symbol is no longer used anywhere, remove it.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Tom Rini <[email protected]>
Acked-by: Heiko Schocher <[email protected]>
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Signed-off-by: Vagrant Cascadian <[email protected]>
Reviewed-by: Joe Hershberger <[email protected]>
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Signed-off-by: Francois Retief <[email protected]>
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Reworked the LEON2 start.S code to call board_init_f function at startup.
Also implemented the relocate_code function in assembly to relocate the
monitor and setup the stack pointer before calling relocated board_init_r.
Add the CONFIG_SYS_GENERIC_BOARD variable to all the LEON2 boards.
Signed-off-by: Francois Retief <[email protected]>
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Reworked the LEON3 start.S code to call board_init_f function at startup.
Also implemented the relocate_code function in assembly to relocate the
monitor and setup the stack pointer before calling relocated board_init_r.
Add the CONFIG_SYS_GENERIC_BOARD variable to all the LEON3 boards.
Signed-off-by: Francois Retief <[email protected]>
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Signed-off-by: Francois Retief <[email protected]>
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In order to fit into image constraints again, remove this feature.
Signed-off-by: Tom Rini <[email protected]>
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Simple patch to enable support for extfs filesystem in SPL,
this is useful to those who want to avoid vfat like plague.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
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Commit 1eb0c03c2198a7ec9de456b83dacdc4831b96cbf added
SPL_SYS_MALLOC_SIMPLE Kconfig option and changed the way it is
evaluated.
Thus, the definitions of CONFIG_SYS_MALLOC_SIMPLE in rk3***_common.h
board configs are now incorrect because CONFIG_SPL_BUILD is enabled so
CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) will look for SPL_SYS_MALLOC_SIMPLE
instead of SYS_MALLOC_SIMPLE.
This commit fix this enabling SPL_SYS_MALLOC_SIMPLE with the new Kconfig
option by default in rockchip-mach.
Signed-off-by: Ariel D'Alessandro <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This add some basic files required to allow the board to dispaly
serial message and can run command(mmc info etc)
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
Moved board Kconfig fragment from previous patch into this one to fix
build error:
Signed-off-by: Simon Glass <[email protected]>
Series-changes: 8
- moved board Kconfig fragment from previous patch into this one
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rk3036 only 4K size SRAM for SPL, so only support
timer, uart, sdram driver in SPL stage, when finish
initial sdram, back to bootrom.And in rk3036 sdmmc and
debug uart use same iomux, so if you want to boot from
sdmmc, you must disable debug uart.
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
Fixed build error for chromebook_jerry, firefly-rk3288:
Signed-off-by: Simon Glass <[email protected]>
Series-changes: 8
- Fix build error for chromebook_jerry, firefly-rk3288
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some rockchips soc will not use uclass in SPL stage,
so define config to decide whether to build common.c
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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some rockchip soc will not include lib/timer.c in SPL stage,
so implement timer driver for some soc can use us delay function in SPL.
Signed-off-by: Lin Huang <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Save the environment on the SD card for Firefly in the empty space
between the SPL and the u-boot image.
Signed-off-by: Sjoerd Simons <[email protected]>
Acked-by: Simon Glass <[email protected]>
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Similar to load an fdt, when loading an initrd about the 512Mb mark
things seem to break. For now force loading below 512Mb until the reason
why this fails has been determined/solved.
Signed-off-by: Sjoerd Simons <[email protected]>
Acked-by: Simon Glass <[email protected]>
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This is not supported with driver model, so print a message instead of
generating a build error. Rescanning PCI is not yet implemented.
This function will be implemented later once some additional PCI driver
model improvements are merged. It was confirmed on the mailing list
that no one on the tegra side will miss this feature, so it is disabled
for tegra.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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Move this option to Kconfig and fix up all users.
Signed-off-by: Simon Glass <[email protected]>
Tested-by: Stephen Warren <[email protected]>
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To group all dm timer drivers together, move tsc timer to
drivers/timer directory.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>
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The board supports following features:
- Boot media support: SD card/e.MMC/SPI flash,
- Support LCD display (optional, disabled by default),
- Support ethernet,
- Support USB mass storage.
Signed-off-by: Wenyou Yang <[email protected]>
[fix checkpatch warnings]
Signed-off-by: Andreas Bießmann <[email protected]>
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As the environment variables "serial#" and "ethaddr" need to be
overwriten by the users, CONFIG_ENV_OVERWRITE is defined to disable
the write protection. Anybody can change or delete these parameters.
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel
fails to access the device tree blob on boot. The reason is that u-boot
relocates the device tree blob into high memory when booting the kernel
and the kernel is unable to access the blob.
To avoid this issue, fdt_high is set to the value of 0xffffffff. The
device tree blob will not get relocated and is still in low memory to
make it accessible to the kernel.
For the same reason, initrd_high is set to the value of 0xffffffff too.
This patch is to update fdt_high and initrd_high for LS1021AQDS board.
Signed-off-by: Alison Wang <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Add support for the third USB controller for LS1043A.
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Use the U-Boot Driver Model. Just enable Freescale DSPI driver
and set DSPI related parameters in dts file.
Signed-off-by: Gong Qianyu <[email protected]>
Reviewed-by: York Sun <[email protected]>
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LS1043AQDS Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 DIMM
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* Two RGMII ports
* XFI 10G port
* SGMII
* QSGMII with 4x 1G ports
PCIe: supports Gen 1 and Gen 2
SATA 3.0: one SATA 3.0 port
USB 3.0: two micro AB connector and one type A connector
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Mingkai Hu <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Gong Qianyu <[email protected]>
[York Sun: Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <[email protected]>
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Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.
Signed-off-by: Pratiyush Mohan Srivastava <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
[York Sun: Updated MAINTAINERS files
Dropped #ifdef in cpu.h
Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <[email protected]>
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LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava <[email protected]>
Signed-off-by: Prabhakar Kushwaha <[email protected]>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <[email protected]>
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Management complex Firmware, DPL and DPC are depolyed during u-boot boot
sequence.
Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop
and apply DPL from u-boot command prompt.
Signed-off-by: Prabhakar Kushwaha <[email protected]>
Reviewed-by: York Sun <[email protected]>
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Remove fsloadcmd / ext2load as we are using load command
which use the corresponding latest file system command.
Signed-off-by: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefan Roese <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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socfpga_dw_mmc driver will obtain the drvsel and
smplsel value from device tree instead of definition
in config header file.
Signed-off-by: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Pavel Machek <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Pantelis Antoniou <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Acked-by: Marek Vasut <[email protected]>
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This board was constantly parasiting on the CV SoCDK, so split it
into it's own separate directory. Moreover, the board config was
missing important bits, like simple-bus support in SPL, the DRAM
configuration was incorrect and the DTS was also missing the pre
reloc bits.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Jan Viktorin <[email protected]>
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When adding support for the Arria10 platform, we're going to name the file
base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h
to be base_addr_ac5.h for the Arria5 and Cyclone5 platform.
Suggested-by: Marek Vasut <[email protected]>
Signed-off-by: Dinh Nguyen <[email protected]>
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This patch add ZyXEL NSA310S 1-Bay Media Server
The ZyXEL NSA310S device is a Kirkwood based NAS:
- SoC: Marvell 88F6702 1000Mhz
- SDRAM memory: 256MB DDR2 400Mhz
- Gigabit ethernet: PHY Marvell 88E1318
- Flash memory: 128MB
- 1 Power button
- 1 Power LED (blue)
- 4 Status LED (green)
- 1 Copy/Sync button
- 1 Reset button
- 1 SATA II port
- 2 USB 2.0 ports (front and back)
- Smart fan
Signed-off-by: Gerald Kerma <[email protected]>
Signed-off-by: Tony Dinh <[email protected]>
Signed-off-by: Luka Perkov <[email protected]>
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There are already Kconfig options for SPI flash drivers, but we
have not moved them from config.h to defconfig files. This commit
does this in a batch.
Signed-off-by: Bin Meng <[email protected]>
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There are already Kconfig options for SPI drivers, but we
have not moved them from config.h to defconfig files. This
commit does this in a batch.
Signed-off-by: Bin Meng <[email protected]>
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Add MMC and SPI DFU support.
Signed-off-by: Otavio Salvador <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Congatec has several MX6 boards based on quad, dual, dual-lite and solo.
Add SPL support so that all the variants can be supported
Signed-off-by: Otavio Salvador <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Tested basic fastboot commands, such as:
On the U-boot prompt:
=> fastboot 0
On the host PC:
$ fastboot getvar bootloader-version -i 0x0525
bootloader-version: U-Boot 2015.10-rc2-09654-g8f41d27
finished. total time: 0.000s
$ fastboot reboot -i 0x0525 --> board reboots fine.
Signed-off-by: Otavio Salvador <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Congatec boards boot from SPI NOR, so it makes more sense to use
SPI NOR to store the environment variables.
Signed-off-by: Otavio Salvador <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Add SPI NOR support:
=> sf probe
SF: Detected SST25VF032B with page size 256 Bytes, erase size 4 KiB, total 4 MiB
Signed-off-by: Otavio Salvador <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Using 50 MiB malloc pool in SPL is nonsense. Since the caches are not
enabled in SPL, it takes 2 seconds to init the pool and has no obvious
benefit. Reduce the size to 1 MiB.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Stefano Babic <[email protected]>
Cc: Tim Harvey <[email protected]>
Tested-by: Stefano Babic <[email protected]>
Acked-by: Tim Harvey <[email protected]>
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