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This patch adds Cypress manufacturer ID (34h) definition.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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into next
- V3U Falcon board support
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into next
- xSPI Octal DTR support (Pratyush Yadav)
- MXIC SPI driver (Zhengxun)
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Prepare v2021.07-rc5
# gpg: Signature made Mon 28 Jun 2021 03:39:36 PM EDT
# gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C
# gpg: Good signature from "Thomas Rini <[email protected]>" [ultimate]
# Conflicts:
# configs/am64x_evm_r5_defconfig
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We currently define the EFI support of an SMBIOS table as the third bit of
"BIOS Characteristics Extension Byte 1". The latest DMTF spec defines it
on "BIOS Characteristics Extension Byte 2".
Signed-off-by: Ilias Apalodimas <[email protected]>
Remove superfluous assignment.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The Cypress Semper flash is an xSPI compliant octal DTR flash. Add
support for using it in octal DTR mode.
The flash by default boots in a hybrid sector mode. Switch to uniform
sector mode on boot. Use the default 20 dummy cycles for a read fast
command.
The SFDP programming on some older versions of the flash was incorrect.
Fixes for that are included in the fixup hooks.
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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On probe, the SPI NOR core will put a flash in 8D-8D-8D mode if it
supports it. But Linux as of now expects to get the flash in 1S-1S-1S
mode. Handing the flash to Linux in Octal DTR mode means the kernel will
fail to detect the flash.
So, we need to reset to Power-on-Reset (POR) state before handing off
the flash. A Software Reset command can be used to do this.
One limitation of the soft reset is that it will restore state from
non-volatile registers in some flashes. This means that if the flash was
set to 8D mode in a non-volatile configuration, a soft reset won't help.
This commit assumes that we don't set any non-volatile bits anywhere,
and the flash doesn't have any non-volatile Octal DTR mode
configuration.
Since spi-nor-tiny doesn't (and likely shouldn't) have
spi_nor_soft_reset(), add a dummy spi_nor_remove() for it that does
nothing.
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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A Soft Reset sequence will return the flash to Power-on-Reset (POR)
state. It consists of two commands: Soft Reset Enable and Soft Reset.
Find out if the sequence is supported from BFPT DWORD 16.
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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This table is indication that the flash is xSPI compliant and hence
supports octal DTR mode. Extract information like the fast read opcode,
the number of dummy cycles needed for a Read Status Register command,
and the number of address bytes needed for a Read Status Register
command.
The default dummy cycles for a fast octal DTR read are set to 20. Since
there is no simple way of determining the dummy cycles needed for the
fast read command, flashes that use a different value should update it
in their flash-specific hooks.
Signed-off-by: Pratyush Yadav <[email protected]>
Acked-by: Jagan Teki <[email protected]>
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Double Transfer Rate (DTR) is SPI protocol in which data is transferred
on each clock edge as opposed to on each clock cycle. Make
framework-level changes to allow supporting flashes in DTR mode.
Right now, mixed DTR modes are not supported. So, for example a mode
like 4S-4D-4D will not work. All phases need to be either DTR or STR.
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The spi-mem layer provides a spi_mem_supports_op() function to check
whether a specific operation is supported by the controller or not.
This is much more accurate than the hwcaps selection logic based on
SPI_{RX,TX}_ flags.
Rework the hwcaps selection logic to use spi_mem_supports_op().
To make sure the build doesn't break for boards not using CONFIG_DM_SPI,
add a simple SPI_{RX,TX}_ based hwcaps selection logic in spi-mem-nodm
similar to spi_mem_default_supports_op(). This change is only
compile-tested.
To avoid SPL size problems on the x530 board, the old hwcaps selection
is still kept around. Leaving the code in-place was getting difficult to
read and understand, so the code is restructured to have it all in one
isolated function. As a result of this, the parameter hwcaps to
spi_nor_setup() is no longer needed. Remove it.
Based on the Linux commit c76f5089796a (mtd: spi-nor: Rework hwcaps
selection for the spi-mem case, 2019-08-06)
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Sometimes the information in a flash's SFDP tables is wrong. Sometimes
some information just can't be expressed in the SFDP table. So,
introduce the fixup hooks to allow tailoring settings for a specific
flash.
Three hooks are added: default_init, post_sfdp, and post_bfpt. These
allow tweaking the flash settings at different point in the probe
sequence. Since the hooks reside in nor->info, set that value just
before the call to spi_nor_init_params().
The hooks and at what points they are executed mimics Linux's spi-nor
framework. One major difference is that Linux puts the struct
spi_nor_fixups in nor->info. This is not possible in U-Boot because the
spi-nor-ids list is shared between spi-nor-core.c and spi-nor-tiny.c.
Since spi-nor-tiny shouldn't have those fixup hooks populated, add a
separate function that lets flashes populate their fixup hooks.
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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nor->setup() can be used by flashes to configure settings in case they
have any peculiarities that can't be easily expressed by the generic
spi-nor framework. This includes things like different opcodes, dummy
cycles, page size, uniform/non-uniform sector sizes, etc.
Move related declarations to avoid forward declarations.
Inspired by the Linux kernel's setup() hook.
Signed-off-by: Pratyush Yadav <[email protected]>
Acked-by: Jagan Teki <[email protected]>
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spi_mem_default_supports_op() rejects DTR ops by default to ensure that
the controller drivers that haven't been updated with DTR support
continue to reject them. It also makes sure that controllers that don't
support DTR mode at all (which is most of them at the moment) also
reject them.
This means that controller drivers that want to support DTR mode can't
use spi_mem_default_supports_op(). Driver authors have to roll their own
supports_op() function and mimic the buswidth checks. Or even worse,
driver authors might skip it completely or get it wrong.
Add spi_mem_dtr_supports_op(). It provides a basic sanity check for DTR
ops and performs the buswidth requirement check. Move the logic for
checking buswidth in spi_mem_default_supports_op() to a separate
function so the logic is not repeated twice.
Signed-off-by: Pratyush Yadav <[email protected]>
Acked-by: Jagan Teki <[email protected]>
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Controllers can use this function to perform basic sanity checking on
the spi-mem op.
Reviewed-by: Sean Anderson <[email protected]>
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", the second byte is the
inverse of the opcode. When it is "hex" an additional opcode byte based
is sent with the command whose value can be anything.
So, make opcode a 16-bit value and add a 'nbytes', similar to how
multiple address widths are handled.
All usages of sizeof(op->cmd.opcode) also need to be changed to be
op->cmd.nbytes because that is the actual indicator of opcode size.
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Init GICv3 for V3U Falcon in early phase
Signed-off-by: Koji Matsuoka <[email protected]>
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Add board code for the R8A779A0 V3U Falcon board.
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
--
Marek: - various small rebase fixes and clean ups
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Import R8A779A0 V3U DTs and headers from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut <[email protected]>
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The device_probe() function does the same thing as mtd_probe() and
mtd_probe() is only used in mtd_probe_uclass_mtd_devs(), where the
probing can be made simpler by using uclass_foreach_dev_probe macro.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Pali Rohár <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Cc: Priyanka Jain <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Patrick Delaunay <[email protected]>
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Add support for parsing partitions defined in device-trees via the
`partitions` node with `fixed-partitions` compatible.
The `mtdparts`/`mtdids` mechanism takes precedence. If some partitions
are defined for a MTD device via this mechanism, the code won't register
partitions for that MTD device from OF, even if they are defined.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Patrick Delaunay <[email protected]>
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Add function for retrieving full node path of a given ofnode.
This uses np->full_name if OF is live, otherwise a call to
fdt_get_path() is made.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add functions ofnode_get_addr_size_index_notrans(), which is a
non-translating version of ofnode_get_addr_size_index().
Some addresses are not meant to be translated, for example those of MTD
fixed-partitions.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Tested-by: Patrice Chotard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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- Revert fsl_esdhc_imx using VENDORSPEC_FRC_SDCLK_ON
- Fix data read for dw_mmc
- Increase minimum bus freq for mtk-sd
- Minor cleanup
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Based on the comment in socfpga_soc64_common.h, the intention is for
CONFIG_SYS_MEM_RESERVE_SECURE to be unused. However, in the code we do:
...
and that will evaluate to true. This leads to unwanted code being
compiled. Further, as CONFIG_SYS_MEM_RESERVE_SECURE has not been
migrated to Kconfig, this leads to a mismatch in the size of gd
depending on if we have or have not also had <configs/BOARD.h> also
included yet.
Remove the define as it's not needed.
Cc: Siew Chin Lim <[email protected]>
Cc: Chee Hong Ang <[email protected]>
Cc: Dalon Westergreen <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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The original code is in the public domain. Licenses/README states that the
general license for U-Boot is GPL 2.0+. So we can mark the malloc code as
GPL 2.0+ too.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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On ARM64 secure OS can run as 64bit or 32bit that's why it is necessary to
record information about architecture that other code can read it and
properly pass it to TF-A and start in 64bit or 32bit mode.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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clock output"
This reverts commit 63756575b42b8b4fb3f59cbbf0cedf03331bc2d2.
Since this commit a imx6qdl-pico board boots extremely slowly
in both SPL as well as U-Boot proper.
Fix this regression by reverting the offending commit for now.
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Tested-by: Pierre-Jean Texier <[email protected]>
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Change to static about dm function.
They can be used with wrapper functions.
Signed-off-by: Jaehoon Chung <[email protected]>
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Use mmc_send_cmd instead of dm_mmc_send_cmd.
It doesn't need to distinguish this function.
Signed-off-by: Jaehoon Chung <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-rockchip into next
- New SoC platform support: rk3568;
- rockchip pcie Code compile issue fix;
- Board fix for rk3399 Khadas Edge;
- Add Rockchip NFC driver;
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Add error callback in dfu stack to manage some board specific
behavior on DFU targets.
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Problem: USB2.0 port can recognize any USB1.1 devices (like usb keyboard)
Add missed USB OHCI configuration
USB device tree:
1 Hub (480 Mb/s, 0mA)
u-boot EHCI Host Controller
1 Hub (12 Mb/s, 0mA)
| U-Boot Root Hub
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+-2 Human Interface (1.5 Mb/s, 100mA)
Dell KB216 Wired Keyboard
Signed-off-by: Artem Lapkin <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add support for rk3568 evaluation board.
Signed-off-by: Joseph Chen <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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RK3568 is a high-performance and low power quad-core application
processor designed for personal mobile internet device and AIoT
equipments.
Signed-off-by: Joseph Chen <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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fdtoverlay (pxe_utils) require define fdtoverlay_addr_r env variable
for example sunxi-common.h meson64.h already have it.
Signed-off-by: Artem Lapkin <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add dts binding header for rk3568, files origin from kernel.
Signed-off-by: Elaine Zhang <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-atmel into next
First set of u-boot-atmel features for the 2021.10 cycle:
This feature set converts the boards pm9261 and pm9263 Ethernet support
to DM; enables hash command for all SAM boards; fixes the NAND pmecc
bit-flips correction; adds Falcon boot for sama5d3_xplained board; and
other minor adjustments.
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- fsl-qoriq: Bug fixes related pfe, eth, thermal node, vid.c, cpu release,
mmc, usb, env, etc for Layerscape boards
- powerpc: Update Maintainers for some boards.
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The T2080RDB boards revisions D and up have updated 10G Aquantia PHYs
connected to MAC1 and MAC2. The second Aquantia PHY is located at a
different address on the MDIO bus compared to rev C (0x8 instead of 0x1).
Fix-up the Linux device tree to update the PHY address for the second
Aquantia PHY on boards revisions D and up. Also rename the PHY node to
reflect the changes.
Signed-off-by: Camelia Groza <[email protected]>
[Rebased]
Signed-off-by: Priyanka Jain <[email protected]>
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A system clock of 66MHz was chosen for the pg-wcom-ls102xa.
Compared to the Evalboard, this corresponds to a reduction of 1/3.
The system counter clock should have been reduced accordingly,
but that was not the case, so we had a system time that was
1/3 behind the real time.
This patch corrects the system counter clock to
8.333MHz = 66.667MHz / 8.
Signed-off-by: Rainer Boschung <[email protected]>
Signed-off-by: Aleksandar Gerasimovski <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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In order to improve power consumption ls102x allows to disable peripherals
that are not in use.
This patch follows SELI8 HW design description and disables peripherals
that are not in use in our designs, the same configuration is applicable
and for EXPU1.
This patch uses available hwconfig option for updating ls102x device
disable configuration.
Signed-off-by: Aleksandar Gerasimovski <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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The default behavior in the latest u-boot revisions is to rotate the
active net device to the next available if the requested link is not
established.
For our ls102x based devices this would mean that if active debug net
device is not available, u-boot will rotate and set the next net device
that is one of the estar adapters.
To return from this situation manual action to set correct ethact
adapter will be needed and this can be annoying when working in
debug mode.
Setting ethrotate=no will disable net adapter rotation and will make sure
that the primary adapter is always used.
Signed-off-by: Aleksandar Gerasimovski <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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In our designs we reserve PRAM area at the end of the RAM, and in order
this area to be visible and taken into account by the u-boot memory mgmt
CONFIG_PRAM has to be defined.
Signed-off-by: Aleksandar Gerasimovski <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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From production view this is standard test executed during production on
all linux based foxmc cards.
On CENT2 HW defined memory region is zero means that some DDR accesses are
done by memory_post_dataline and memory_post_addrline but pattern tests
are skipped that's why mem_regions is fast there.
On ls102x for the complete DDR region of 1GiB memory_regions_post_test
takes approx. 4min and this is too much for production, so this patch
defines only 1MiB region as compromise.
Signed-off-by: Aleksandar Gerasimovski <[email protected]>
Reviewed-by: Priyanka Jain <[email protected]>
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The EXPU1 design is a new 40G capable ethernet service unit card for
Hitachi-Powergrids wired-com product lines.
The base SoC is same as for already added SELI8 card, consequently the
already added u-boot support for SELI8 is reused.
Signed-off-by: Rainer Boschung <[email protected]>
Signed-off-by: Aleksandar Gerasimovski <[email protected]>
[Fixed new line error at EOF]
Signed-off-by: Priyanka Jain <[email protected]>
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Drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
is used instead.
Signed-off-by: Yangbo Lu <[email protected]>
Acked-by: Michael Walle <[email protected]> [for kontron-sl28]
Reviewed-by: Priyanka Jain <[email protected]>
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