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Fix errors in the LWMON5 Sysmon POST for negative temperatures.
Signed-off-by: Yuri Tikhonov <[email protected]>
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Add test for DPIC_SYS_ERROR_REG to be zero in the LWMON5 dsPIC POST.
Signed-off-by: Yuri Tikhonov <[email protected]> ---
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plus some coding style cleanup
Signed-off-by: Wolfgang Denk <[email protected]>
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Modify the RTC API to provide one a status for the time reported by
the rtc_get() function:
0 - a reliable time is guaranteed,
< 0 - a reliable time isn't guaranteed (power fault, clock issues,
and so on).
The RTC chip drivers are responsible for providing this info if the
corresponding chip supports such functionality. If not - always
report that the time is reliable.
The POST RTC test was modified to detect the RTC faults utilizing
this new rtc_get() feature.
Signed-off-by: Yuri Tikhonov <[email protected]>
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Signed-off-by: Dmitry Rakhchev <[email protected]>
Signed-off-by: Yuri Tikhonov <[email protected]>
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Backlight was switched on even when temperature was too low.
Signed-off-by: Dmitry Rakhchev <[email protected]>
Signed-off-by: Yuri Tikhonov <[email protected]>
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watch-dog for now.
Signed-off-by: Dmitry Rakhchev <[email protected]>
Signed-off-by: Yuri Tikhonov <[email protected]>
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as POST_CRITICAL fails then the alternative, post_critical, boot-command is used. If this command is not defined then U-Boot enters into interactive mode.
Signed-off-by: Dmitry Rakhchev <[email protected]>
Signed-off-by: Yuri Tikhonov <[email protected]>
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* External Watchdog test;
* dsPIC tests;
* FPGA test;
* GDC test;
* Sysmon tests.
Signed-off-by: Dmitry Rakhchev <[email protected]>
Signed-off-by: Yuri Tikhonov <[email protected]>
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Signed-off-by: Dmitry Rakhchev <[email protected]>
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This patch changes the physical addess parameter from 32bit to 64bit.
This is needed for 36bit 4xx platforms to access areas located
beyond the 4GB border, like SoC peripherals (EBC etc.).
Signed-off-by: Stefan Roese <[email protected]>
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Fix warnings while compilation with new gcc in eldk-4.2
Signed-off-by: Anatolij Gustschin <[email protected]>
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Currently (since commit b2e2142c) u-boot crashes on
sequoia board while SPR test if CONFIG_4xx_DCACHE is
enabled. This patch disables the cache while SPR test.
Signed-off-by: Anatolij Gustschin <[email protected]>
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The CPU POST test code (run from cpu_post_exec_31()) doesn't follow the
ABI carefully, at least the CR3, CR4, and CR5 fields of CR are clobbered
by it. The gcc-4.2 with its more aggressive optimization exposes this fact.
This patch just saves the CR value before running the test code, so allowing
it to do anything it wants with CR.
Signed-off-by: Dmitry Rakhchev <[email protected]>
Acked-by: Yuri Tikhonov <[email protected]>
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Signed-off-by: Larry Johnson <[email protected]>
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The ECC POST reported intermittent failures running after power-up on
the Korat PPC440EPx board. Even when the test passed, the debugging
output occasionally reported additional unexpected ECC errors.
This refactoring has three main objectives: (1) minimize the code
executed with ECC enabled during the tests, (2) add more checking of the
results so any unexpected ECC errors would cause the test to fail, and
(3) use synchronization (only) where required by the processor.
Signed-off-by: Larry Johnson <[email protected]>
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post/cpu/ppc4xx/spr.c contained a few checks for registers only present
for PPC440 and derivates processor.
Signed-off-by: Niklaus Giger <[email protected]>
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On LWMON5 we now use d-cache as init-ram and stack. The SPR POST test uses
self modifying code and this doesn't work with stack in d-cache, since
I can't move the code from d-cache to i-cache. We move the SPR test to
be executed a little later, after relocation. Then stack is located in
SDRAM and this self-modifying code is no problem anymore.
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Larry Johnson <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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As repoted by Larry Johnson, running "diag run cache" caused a crash
in U-Boot. This problem was introduced by a patch that removed the
TLB entry for the cache test after the test has completed. Since this
TLB was only setup once, a 2nd attempt to run this cache test
failed with a crash. Now this TLB entry is created every time the
routine is called.
Signed-off-by: Stefan Roese <[email protected]>
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Now that the 440EPx ECC test is not board specific anymore
remove this Makefile.
Signed-off-by: Stefan Roese <[email protected]>
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This patch allows the ECC POST to be used for different boards with the
PPC440 Denali SDRAM controller. Modifications include skipping the test
if ECC is not enabled (as for non-ECC DIMMs) and adding synchronization
to prevent timing errors.
Signed-off-by: Larry Johnson <[email protected]>
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Signed-off-by: Larry Johnson <[email protected]>
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Signed-off-by: Matthias Fuchs <[email protected]>
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Now with caches enabled (i- and d-cache) on 44x, we need a chance to
disable the cache for the CPU POST tests, since these tests consist
of self modifying code. This is done via the new change_tlb() function.
Signed-off-by: Stefan Roese <[email protected]>
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This patch enables the 4xx EMAC POST driver to work too, when dcache is
enabled.
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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The POST ethernet test needed to be changed to dynamically determine
the count of ethernet devices. This code is cloned from the 4xx
ethernet driver.
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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As experienced on lwmon5, on some boards the POST memory test can
corrupt the global data buffer (bd). This patch fixes this issue
by checking and limiting this area.
Signed-off-by: Yuri Tikhonov <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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When CFG_POST_ETHER_EXT_LOOPBACK is defined, the ethernet POST
is not done using an internal loopback connection, but by assuming
that an external loopback connector is plugged into the board.
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Roese <[email protected]>
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The patch adds support for UART POST on ppc44x-based boards with no
external serial clocks installed.
Signed-off-by: Yuri Tikhonov <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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- Clear ECC status regs after ECC POST test
- Set dcbz for ECC generation with caches enabled as default
- Code cleanup
Signed-off-by: Stefan Roese <[email protected]>
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This patch adds ECC Post test for the Lwmon5 board based
on PPC440EPx to U-Boot.
Signed-off-by: Pavel Kolesnikov <[email protected]>
Acked-by: Yuri Tikhonov <[email protected]>
Acked-by: Stefan Roese <[email protected]>
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Signed-off-by: Heiko Schocher <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Signed-off-by: Sergei Poselenov <[email protected]>
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Added memory, CPU, UART, I2C and SPR POST tests for PPC440.
Signed-off-by: Igor Lisitsin <[email protected]>
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Signed-off-by: Wolfgang Denk <[email protected]>
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Based on patch by Mike Frysinger, 20 Jun 2006
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Modifications are based on the linux kernel approach and
support two use cases:
1) Add O= to the make command line
'make O=/tmp/build all'
2) Set environement variable BUILD_DIR to point to the desired location
'export BUILD_DIR=/tmp/build'
'make'
The second approach can also be used with a MAKEALL script
'export BUILD_DIR=/tmp/build'
'./MAKEALL'
Command line 'O=' setting overrides BUILD_DIR environent variable.
When none of the above methods is used the local build is performed and
the object files are placed in the source directory.
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