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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023 Mathieu Othacehe <[email protected]>
*/
/ {
binman: binman {
multiple-images;
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
ddr-1d-imem-fw {
filename = "lpddr4_imem_1d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-1d-dmem-fw {
filename = "lpddr4_dmem_1d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-imem-fw {
filename = "lpddr4_imem_2d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-dmem-fw {
filename = "lpddr4_dmem_2d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl {
type = "nxp-imx9image";
cfg-path = "spl/u-boot-spl.cfgout";
args;
boot-from = "sd";
soc-type = "IMX9";
append = "mx93a1-ahab-container.img";
container;
image = "a55", "u-boot-spl-ddr.bin", "0x2049A000";
};
u-boot {
type = "nxp-imx9image";
cfg-path = "u-boot-container.cfgout";
args;
boot-from = "sd";
soc-type = "IMX9";
container;
image0 = "a55", "bl31.bin", "0x204E0000";
image1 = "a55", "u-boot.bin", "0x80200000";
};
};
};
};
&A55_0 {
clocks = <&clk IMX93_CLK_ARM_PLL>;
};
&A55_1 {
clocks = <&clk IMX93_CLK_ARM_PLL>;
};
&tmu {
compatible = "fsl,imx93-tmu";
reg = <0x44482000 0x1000>;
clocks = <&clk IMX93_CLK_TMC_GATE>;
little-endian;
fsl,tmu-calibration = <0x0000000e 0x800000da
0x00000029 0x800000e9
0x00000056 0x80000102
0x000000a2 0x8000012a
0x00000116 0x80000166
0x00000195 0x800001a7
0x000001b2 0x800001b6>;
#thermal-sensor-cells = <1>;
};
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