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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) ASPEED Technology Inc.
* Ryan Chen <[email protected]>
*
*/
#ifndef _ASM_ARCH_PLATFORM_H
#define _ASM_ARCH_PLATFORM_H
#if defined(CONFIG_ASPEED_AST2500)
#define ASPEED_MAC_COUNT 2
#define ASPEED_DRAM_BASE 0x80000000
#define ASPEED_SRAM_BASE 0x1e720000
#define ASPEED_SRAM_SIZE 0x9000
#elif defined(CONFIG_ASPEED_AST2600)
#define ASPEED_MAC_COUNT 4
#define ASPEED_DRAM_BASE 0x80000000
#define ASPEED_SRAM_BASE 0x10000000
#define ASPEED_SRAM_SIZE 0x16000
#elif defined(CONFIG_ASPEED_AST2700)
#define ASPEED_CPU_AHBC_BASE 0x12000000
#define ASPEED_CPU_REVISION_ID 0x12C02000
#define ASPEED_CPU_SCU_BASE 0x12C02000
#define ASPEED_CPU_HW_STRAP1 0x12C02010
#define ASPEED_CPU_RESET_LOG1 0x12C02050
#define ASPEED_CPU_RESET_LOG2 0x12C02060
#define ASPEED_CPU_RESET_LOG3 0x12C02070
#define ASPEED_MAC_COUNT 3
#define ASPEED_DRAM_BASE 0x400000000
#define ASPEED_SRAM_BASE 0x10000000
#define ASPEED_SRAM_SIZE 0x20000
#define ASPEED_FMC_REG_BASE 0x14000000
#define ASPEED_FMC_CS0_BASE 0x100000000
#define ASPEED_FMC_CS0_SIZE 0x80000000
#define ASPEED_IO_MAC0_BASE 0x14050000
#define ASPEED_IO_MAC1_BASE 0x14060000
#define ASPEED_IO_AHBC_BASE 0x140b0000
#define ASPEED_IO_REVISION_ID 0x14C02000
#define CHIP_AST2700A1_ID_MASK BIT(16)
#define ASPEED_IO_SCU_BASE 0x14C02000
#define ASPEED_IO_HW_STRAP1 0x14C02010
#define ASPEED_IO_RESET_LOG1 0x14C02050
#define ASPEED_IO_RESET_LOG2 0x14C02060
#define ASPEED_IO_RESET_LOG3 0x14C02070
#define ASPEED_IO_RESET_LOG4 0x14C02080
#define ASPEED_IO_GPIO_BASE 0x14C0B000
#define ASPEED_WDTA_BASE 0x14C37400
#else
#error "Unrecognized Aspeed platform."
#endif
#endif
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