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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (c) 2026, Arm Limited. All rights reserved.
*
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "corstone1000.dtsi"
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
cpus: cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a320";
reg = <0 0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a320";
reg = <0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a320";
reg = <0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a320";
reg = <0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
sram: sram@2400000 {
compatible = "mmio-sram";
reg = <0x02400000 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
gic: interrupt-controller@1c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
reg = <0x1c000000 0x10000>,
<0x1c040000 0x80000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
soc {
npu@1a050000 {
compatible = "arm,corstone1000-ethos-u85", "arm,ethos-u85";
reg = <0x1a050000 0x1400>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&refclk100mhz>, <&refclk100mhz>;
clock-names = "core", "apb";
sram = <&sram>;
};
};
};
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