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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 NXP
*/
#include "imx91-pinfunc.h"
#include "imx91_93_common.dtsi"
/{
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tmu 0>;
trips {
cpu_alert: cpu-alert {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert>;
cooling-device =
<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
};
&aips1 {
tmu: thermal-sensor@44482000 {
compatible = "fsl,imx91-tmu";
reg = <0x44482000 0x1000>;
#thermal-sensor-cells = <0>;
clocks = <&clk IMX93_CLK_TMC_GATE>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "thr1", "thr2", "ready";
nvmem-cells = <&tmu_trim1>, <&tmu_trim2>;
nvmem-cell-names = "trim1", "trim2";
};
};
&clk {
compatible = "fsl,imx91-ccm";
};
&ddr_pmu {
compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu";
};
&eqos {
clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
<&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET1_QOS_TSN>,
<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;
assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET1_QOS_TSN>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
};
&fec {
clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
<&clk IMX91_CLK_ENET2_REGULAR_GATE>,
<&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET2_REGULAR>,
<&clk IMX93_CLK_DUMMY>;
assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET2_REGULAR>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
};
&i3c1 {
clocks = <&clk IMX93_CLK_BUS_AON>,
<&clk IMX93_CLK_I3C1_GATE>,
<&clk IMX93_CLK_DUMMY>;
};
&i3c2 {
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
<&clk IMX93_CLK_I3C2_GATE>,
<&clk IMX93_CLK_DUMMY>;
};
&iomuxc {
compatible = "fsl,imx91-iomuxc";
};
&media_blk_ctrl {
compatible = "fsl,imx91-media-blk-ctrl", "syscon";
clocks = <&clk IMX93_CLK_MEDIA_APB>,
<&clk IMX93_CLK_MEDIA_AXI>,
<&clk IMX93_CLK_NIC_MEDIA_GATE>,
<&clk IMX93_CLK_MEDIA_DISP_PIX>,
<&clk IMX93_CLK_CAM_PIX>,
<&clk IMX93_CLK_LCDIF_GATE>,
<&clk IMX93_CLK_ISI_GATE>,
<&clk IMX93_CLK_MIPI_CSI_GATE>;
clock-names = "apb", "axi", "nic", "disp", "cam",
"lcdif", "isi", "csi";
};
&ocotp {
tmu_trim1: tmu-trim@a0 {
reg = <0xa0 0x4>;
};
tmu_trim2: tmu-trim@a4 {
reg = <0xa4 0x4>;
};
};
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