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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2026 NXP
*/
#include "imx93.dtsi"
/ {
aliases {
mmc2 = &usdhc3;
};
reg_usdhc3_vmmc: regulator-usdhc3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc3_vmmc>;
regulator-name = "WLAN_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usdhc3_pwrseq: usdhc3_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_pwrseq>;
reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
};
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
pinctrl-3 = <&pinctrl_usdhc3_sleep>;
mmc-pwrseq = <&usdhc3_pwrseq>;
vmmc-supply = <®_usdhc3_vmmc>;
bus-width = <4>;
keep-power-in-suspend;
non-removable;
wakeup-source;
status = "okay";
};
&iomuxc {
pinctrl_reg_usdhc3_vmmc: regusdhc3vmmcgrp {
fsl,pins = <
/*
* Enable open drain and internal pull-up to allow the IW610 JTAG
* connector to control the PDn status.
*/
MX93_PAD_GPIO_IO29__GPIO2_IO29 0xb9e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582
MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e
MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe
MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe
>;
};
pinctrl_usdhc3_sleep: usdhc3grpsleepgrp {
fsl,pins = <
MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e
MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e
MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e
MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e
MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e
MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e
>;
};
pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp {
fsl,pins = <
MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x39e
>;
};
};
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