blob: 1feccd61258effb96654f0428f40b995ed718b80 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
|
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2026 NXP
*
* NXP S32N79 Reference Design Board (S32N79-RDB)
*/
/dts-v1/;
#include "s32n79.dtsi"
/ {
compatible = "nxp,s32n79-rdb", "nxp,s32n79";
model = "NXP S32N79-RDB";
aliases {
serial0 = &uart0;
serial1 = &uart5;
serial2 = &uart6;
serial3 = &uart7;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
scmi_shbuf: memory@93000000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x93000000 0x0 0x80>;
no-map;
};
};
memory@80000000 {
reg = <0x00 0x80000000 0x00 0x80000000>,
<0x88 0x00000000 0x03 0x40000000>,
<0xc0 0x00000000 0x03 0x40000000>;
device_type = "memory";
};
};
&irqsteer_coss {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart5 {
status = "okay";
};
&uart6 {
status = "okay";
};
&uart7 {
status = "okay";
};
&usdhc0 {
disable-wp;
no-sdio;
status = "okay";
};
|
