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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2026 MediaTek Inc.
*/
#ifndef __MT6358_H_
#define __MT6358_H_
#define MT6358_REGULATOR_DRIVER "mt6358_regulator"
enum {
MT6366_ID_VDRAM1 = 0,
MT6366_ID_VCORE,
MT6366_ID_VPA,
MT6366_ID_VPROC11,
MT6366_ID_VPROC12,
MT6366_ID_VGPU,
MT6366_ID_VS2,
MT6366_ID_VMODEM,
MT6366_ID_VS1,
MT6366_ID_VDRAM2,
MT6366_ID_VSIM1,
MT6366_ID_VIBR,
MT6366_ID_VRF12,
MT6366_ID_VIO18,
MT6366_ID_VUSB,
MT6366_ID_VCN18,
MT6366_ID_VFE28,
MT6366_ID_VSRAM_PROC11,
MT6366_ID_VCN28,
MT6366_ID_VSRAM_OTHERS,
MT6366_ID_VSRAM_GPU,
MT6366_ID_VXO22,
MT6366_ID_VEFUSE,
MT6366_ID_VAUX18,
MT6366_ID_VMCH,
MT6366_ID_VBIF28,
MT6366_ID_VSRAM_PROC12,
MT6366_ID_VEMC,
MT6366_ID_VIO28,
MT6366_ID_VA12,
MT6366_ID_VRF18,
MT6366_ID_VCN33,
MT6366_ID_VMC,
MT6366_ID_VAUD28,
MT6366_ID_VSIM2,
MT6366_ID_RG_MAX,
};
#define MT6358_BUCK_VPROC11_CON0 0x1388
#define MT6358_BUCK_VPROC11_DBG0 0x139e
#define MT6358_BUCK_VPROC11_ELR0 0x13a6
#define MT6358_BUCK_VPROC12_CON0 0x1408
#define MT6358_BUCK_VPROC12_DBG0 0x141e
#define MT6358_BUCK_VPROC12_ELR0 0x1426
#define MT6358_BUCK_VCORE_CON0 0x1488
#define MT6358_BUCK_VCORE_DBG0 0x149e
#define MT6358_BUCK_VCORE_ELR0 0x14aa
#define MT6358_BUCK_VGPU_CON0 0x1508
#define MT6358_BUCK_VGPU_ELR0 0x1526
#define MT6358_BUCK_VMODEM_CON0 0x1588
#define MT6358_BUCK_VMODEM_DBG0 0x159e
#define MT6358_BUCK_VMODEM_ELR0 0x15a6
#define MT6358_BUCK_VDRAM1_CON0 0x1608
#define MT6358_BUCK_VDRAM1_DBG0 0x161e
#define MT6358_BUCK_VDRAM1_ELR0 0x1626
#define MT6358_BUCK_VS1_CON0 0x1688
#define MT6358_BUCK_VS1_DBG0 0x169e
#define MT6358_BUCK_VS1_ELR0 0x16ae
#define MT6358_BUCK_VS2_CON0 0x1708
#define MT6358_BUCK_VS2_DBG0 0x171e
#define MT6358_BUCK_VS2_ELR0 0x172e
#define MT6358_BUCK_VPA_CON0 0x1788
#define MT6358_BUCK_VPA_CON1 0x178a
#define MT6358_BUCK_VPA_DBG0 0x1792
#define MT6358_LDO_VXO22_CON0 0x1a88
#define MT6358_LDO_VA12_CON0 0x1a9c
#define MT6358_LDO_VAUX18_CON0 0x1ab0
#define MT6358_LDO_VAUD28_CON0 0x1ac4
#define MT6358_LDO_VIO28_CON0 0x1ad8
#define MT6358_LDO_VIO18_CON0 0x1aec
#define MT6358_LDO_VDRAM2_CON0 0x1b08
#define MT6358_LDO_VDRAM2_ELR0 0x1b78
#define MT6358_LDO_VEMC_CON0 0x1b1c
#define MT6358_LDO_VUSB_CON0_0 0x1b30
#define MT6358_LDO_VSRAM_PROC11_CON0 0x1b46
#define MT6358_LDO_VSRAM_PROC11_DBG0 0x1b60
#define MT6358_LDO_VSRAM_PROC12_CON0 0x1b88
#define MT6358_LDO_VSRAM_PROC12_DBG0 0x1ba2
#define MT6358_LDO_VSRAM_OTHERS_CON0 0x1ba6
#define MT6358_LDO_VSRAM_OTHERS_DBG0 0x1bc0
#define MT6358_LDO_VSRAM_GPU_CON0 0x1bc8
#define MT6358_LDO_VSRAM_GPU_DBG0 0x1be2
#define MT6358_LDO_VSRAM_CON0 0x1bee
#define MT6358_LDO_VSRAM_CON1 0x1bf0
#define MT6358_LDO_VSRAM_CON2 0x1bf2
#define MT6358_LDO_VSRAM_CON3 0x1bf4
#define MT6358_LDO_VFE28_CON0 0x1c08
#define MT6358_LDO_VRF18_CON0 0x1c1c
#define MT6358_LDO_VRF12_CON0 0x1c30
#define MT6358_LDO_VEFUSE_CON0 0x1c44
#define MT6358_LDO_VCN18_CON0 0x1c58
#define MT6358_LDO_VMC_CON0 0x1cc4
#define MT6358_LDO_VMCH_CON0 0x1cd8
#define MT6358_LDO_VIBR_CON0 0x1d08
#define MT6358_LDO_VCN33_CON0_0 0x1d1c
#define MT6358_LDO_VSIM1_CON0 0x1d48
#define MT6358_LDO_VSIM2_CON0 0x1d5c
#define MT6358_LDO_VCN28_CON0 0x1d88
#define MT6358_LDO_VBIF28_CON0 0x1d9e
#define MT6358_VSIM1_ANA_CON0 0x1e2c
#define MT6358_VSIM2_ANA_CON0 0x1e30
#define MT6358_VUSB_ANA_CON0 0x1e34
#define MT6358_VEMC_ANA_CON0 0x1e38
#define MT6358_VIO28_ANA_CON0 0x1e40
#define MT6358_VIBR_ANA_CON0 0x1e44
#define MT6358_VMCH_ANA_CON0 0x1e48
#define MT6358_VMC_ANA_CON0 0x1e4c
#define MT6358_VRF18_ANA_CON0 0x1e88
#define MT6358_VCN18_ANA_CON0 0x1e8c
#define MT6358_VIO18_ANA_CON0 0x1e94
#define MT6358_VEFUSE_ANA_CON0 0x1e98
#define MT6358_VRF12_ANA_CON0 0x1e9c
#define MT6358_VDRAM2_ANA_CON0 0x1eaa
#define MT6358_VA12_ANA_CON0 0x1eb2
#define MT6358_VCN33_ANA_CON0 0x1e28
#endif
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