fix codeql ComparisonWithWiderType (#711)

2 files changed, 23 insertions, 23 deletions

diff --git a/storage/miniports/storahci/src/ahci.h b/storage/miniports/storahci/src/ahci.h
index b11c24fe..46ceca16 100644
--- a/storage/miniports/storahci/src/ahci.h
+++ b/storage/miniports/storahci/src/ahci.h
@@ -756,27 +756,27 @@ typedef union _AHCI_HBA_CAPABILITIES  {
 
     struct {
         //LSB
-        ULONG NP :5; //Number of Ports: 0 s based value indicating the maximum number of ports supported by the HBA silicon. A maximum of 32 ports can be supported. A value of ?0h?, indicating one port, is the minimum requirement. Note that the number of ports indicated in this field may be more than the number of ports indicated in the GHC.PI register.
-        ULONG SXS :1; //AHCI 1.1 Supports External SATA: When set to '1', indicates that the HBA has one or more Serial ATA ports that has a signal only connector that is externally accessible. If this bit is set, software may refer to the PxCMD.ESP bit to determine whether a specific port has its signal connector externally accessible as a signal only connector (i.e. power is not part of that connector).  When the bit is cleared to '0', indicates that the HBA has no Serial ATA ports that have a signal only connector externally accessible.
-        ULONG EMS :1; //AHCI 1.1 Enclosure Management Supported: When set to '1', indicates that the HBA supports enclosure management as defined in section 12.  When enclosure management is supported, the HBA has implemented the EM_LOC and EM_CTL global HBA registers.  When cleared to '0', indicates that the HBA does not support enclosure management and the EM_LOC and EM_CTL global HBA registers are not implemented.
-        ULONG CCCS :1; //AHCI 1.1 Command Completion Coalescing Supported: When set to '1', indicates that the HBA supports command completion coalescing as defined in section 11.  When command completion coalescing is supported, the HBA has implemented the CCC_CTL and the CCC_PORTS global HBA registers.  When cleared to '0', indicates that the HBA does not support command completion coalescing and the CCC_CTL and CCC_PORTS global HBA registers are not implemented.
-        ULONG NCS :5; //Number of Command Slots: 0 s based value indicating the number of command slots supported by this HBA. A minimum of 1 and maximum of 32 slots can be supported.
-        ULONG PSC :1; //Partial State Capable: Indicates whether the HBA can support transitions to the Partial state. When cleared to ?0 , software must not allow the HBA to initiate transitions to the Partial state via aggressive link power management nor the PxCMD.ICC field in each port, and the PxSCTL.IPM field in each port must be programmed to disallow device initiated Partial requests. When set to ?1 , HBA and device initiated Partial requests can be supported.
-        ULONG SSC :1; //Slumber State Capable: Indicates whether the HBA can support transitions to the Slumber state. When cleared to ?0 , software must not allow the HBA to initiate transitions to the Slumber state via aggressive link power management nor the PxCMD.ICC field in each port, and the PxSCTL.IPM field in each port must be programmed to disallow device initiated Slumber requests. When set to ?1 , HBA and device initiated Slumber requests can be supported.
-        ULONG PMD :1; //PIO Multiple DRQ Block: If set to '1 , the HBA supports multiple DRQ block data transfers for the PIO command protocol. If cleared to ?0 the HBA only supports single DRQ block data transfers for the PIO command protocol.
-        ULONG FBSS :1; //AHCI 1.1  FIS-based Switching Supported: When set to '1', indicates that the HBA supports Port Multiplier FIS-based switching. When cleared to '0', indicates that the HBA does not support FIS-based switching.  AHCI 1.0 and 1.1 HBAs shall have this bit cleared to '0'.
-        ULONG SPM :1; //Supports Port Multiplier: Indicates whether the HBA can support a Port Multiplier. When set, a Port Multiplier using command-based switching is supported. When cleared to ?0 , a Port Multiplier is not supported, and a Port Multiplier may not be attached to this HBA.
-        ULONG SAM :1; //Supports AHCI mode only: The SATA controller may optionally support AHCI access mechanisms only. A value of '0' indicates that in addition to the native AHCI mechanism (via ABAR), the SATA controller implements a legacy, task-file based register interface such as SFF-8038i. A value of '1' indicates that the SATA controller does not implement a legacy, task-file based register interface.
-        ULONG SNZO :1; //Supports Non-Zero DMA Offsets: When set to '1 , indicates that the HBA can support non-zero DMA offsets for DMA Setup FISes. This bit is reserved for future AHCI enhancements. AHCI 1.0 HBAs must have this bit cleared to ?0 .
-        ULONG ISS :4; //Interface Speed Support: Indicates the maximum speed the HBA can support on its ports. These encodings match the PxSCTL.DET.SPD field, which is programmable by system software. Values are:
-        ULONG SCLO :1; //Supports Command List Override: When set to '1 , indicates that the HBA supports the PxCMD.CLO bit and its associated function. When cleared to ?0 , the HBA is not capable of clearing the BSY and DRQ bits in the Status register in order to issue a software reset if these bits are still set from a previous operation.
-        ULONG SAL :1; //Supports Activity LED: When set to '1 , indicates that the HBA supports a single output pin which indicates activity. This pin can be connected to an LED on the platform to indicate device activity on any drive. See section 10.10 for more information.
-        ULONG SALP :1; //Supports Aggressive Link Power Management: When set to ?1 , indicates that the HBA can support auto-generating link requests to the Partial or Slumber states when there are no commands to process. Refer to section 8.3.1.3.
-        ULONG SSS :1; //Supports Staggered Spin-up: When set to '1 , indicates that the HBA supports staggered spin-up on its ports, for use in balancing power spikes. This value is loaded by the BIOS prior to OS initialization.
-        ULONG SMPS :1; //Supports Mechanical Presence Switch: ): When set to '1', the HBA supports mechanical presence switches on its ports for use in hot plug operations.  When cleared to '0', this function is not supported.  This value is loaded by the BIOS prior to OS initialization.
-        ULONG SSNTF :1; //AHCI 1.1 Supports SNotification Register: When set to '1', indicates that the HBA supports the PxSNTF (SNotification) register and its associated functionality.  When cleared to '0', the HBA does not support the PxSNTF (SNotification) register and its associated functionality.  Refer to section 10.10.1.
-        ULONG SNCQ :1; //Supports Native Command Queuing: Indicates whether the HBA supports Serial ATA native command queuing. If set to ?1 , an HBA shall handle DMA Setup FISes natively, and shall handle the auto-activate optimization through that FIS. If cleared to ?0 , native command queuing is not supported and software should not issue any native command queuing commands.
-        ULONG S64A :1; //Supports 64-bit Addressing: Indicates whether the HBA can access 64-bit data structures. If true, the HBA shall make the 32-bit upper bits of the port DMA Descriptor, the PRD Base, and each PRD entry read/write. If cleared, these are read- only and treated as ?0 by the HBA.
+        UCHAR NP :5; //Number of Ports: 0 s based value indicating the maximum number of ports supported by the HBA silicon. A maximum of 32 ports can be supported. A value of ?0h?, indicating one port, is the minimum requirement. Note that the number of ports indicated in this field may be more than the number of ports indicated in the GHC.PI register.
+        UCHAR SXS :1; //AHCI 1.1 Supports External SATA: When set to '1', indicates that the HBA has one or more Serial ATA ports that has a signal only connector that is externally accessible. If this bit is set, software may refer to the PxCMD.ESP bit to determine whether a specific port has its signal connector externally accessible as a signal only connector (i.e. power is not part of that connector).  When the bit is cleared to '0', indicates that the HBA has no Serial ATA ports that have a signal only connector externally accessible.
+        UCHAR EMS :1; //AHCI 1.1 Enclosure Management Supported: When set to '1', indicates that the HBA supports enclosure management as defined in section 12.  When enclosure management is supported, the HBA has implemented the EM_LOC and EM_CTL global HBA registers.  When cleared to '0', indicates that the HBA does not support enclosure management and the EM_LOC and EM_CTL global HBA registers are not implemented.
+        UCHAR CCCS :1; //AHCI 1.1 Command Completion Coalescing Supported: When set to '1', indicates that the HBA supports command completion coalescing as defined in section 11.  When command completion coalescing is supported, the HBA has implemented the CCC_CTL and the CCC_PORTS global HBA registers.  When cleared to '0', indicates that the HBA does not support command completion coalescing and the CCC_CTL and CCC_PORTS global HBA registers are not implemented.
+        UCHAR NCS :5; //Number of Command Slots: 0 s based value indicating the number of command slots supported by this HBA. A minimum of 1 and maximum of 32 slots can be supported.
+        UCHAR PSC :1; //Partial State Capable: Indicates whether the HBA can support transitions to the Partial state. When cleared to ?0 , software must not allow the HBA to initiate transitions to the Partial state via aggressive link power management nor the PxCMD.ICC field in each port, and the PxSCTL.IPM field in each port must be programmed to disallow device initiated Partial requests. When set to ?1 , HBA and device initiated Partial requests can be supported.
+        UCHAR SSC :1; //Slumber State Capable: Indicates whether the HBA can support transitions to the Slumber state. When cleared to ?0 , software must not allow the HBA to initiate transitions to the Slumber state via aggressive link power management nor the PxCMD.ICC field in each port, and the PxSCTL.IPM field in each port must be programmed to disallow device initiated Slumber requests. When set to ?1 , HBA and device initiated Slumber requests can be supported.
+        UCHAR PMD :1; //PIO Multiple DRQ Block: If set to '1 , the HBA supports multiple DRQ block data transfers for the PIO command protocol. If cleared to ?0 the HBA only supports single DRQ block data transfers for the PIO command protocol.
+        UCHAR FBSS :1; //AHCI 1.1  FIS-based Switching Supported: When set to '1', indicates that the HBA supports Port Multiplier FIS-based switching. When cleared to '0', indicates that the HBA does not support FIS-based switching.  AHCI 1.0 and 1.1 HBAs shall have this bit cleared to '0'.
+        UCHAR SPM :1; //Supports Port Multiplier: Indicates whether the HBA can support a Port Multiplier. When set, a Port Multiplier using command-based switching is supported. When cleared to ?0 , a Port Multiplier is not supported, and a Port Multiplier may not be attached to this HBA.
+        UCHAR SAM :1; //Supports AHCI mode only: The SATA controller may optionally support AHCI access mechanisms only. A value of '0' indicates that in addition to the native AHCI mechanism (via ABAR), the SATA controller implements a legacy, task-file based register interface such as SFF-8038i. A value of '1' indicates that the SATA controller does not implement a legacy, task-file based register interface.
+        UCHAR SNZO :1; //Supports Non-Zero DMA Offsets: When set to '1 , indicates that the HBA can support non-zero DMA offsets for DMA Setup FISes. This bit is reserved for future AHCI enhancements. AHCI 1.0 HBAs must have this bit cleared to ?0 .
+        UCHAR ISS :4; //Interface Speed Support: Indicates the maximum speed the HBA can support on its ports. These encodings match the PxSCTL.DET.SPD field, which is programmable by system software. Values are:
+        UCHAR SCLO :1; //Supports Command List Override: When set to '1 , indicates that the HBA supports the PxCMD.CLO bit and its associated function. When cleared to ?0 , the HBA is not capable of clearing the BSY and DRQ bits in the Status register in order to issue a software reset if these bits are still set from a previous operation.
+        UCHAR SAL :1; //Supports Activity LED: When set to '1 , indicates that the HBA supports a single output pin which indicates activity. This pin can be connected to an LED on the platform to indicate device activity on any drive. See section 10.10 for more information.
+        UCHAR SALP :1; //Supports Aggressive Link Power Management: When set to ?1 , indicates that the HBA can support auto-generating link requests to the Partial or Slumber states when there are no commands to process. Refer to section 8.3.1.3.
+        UCHAR SSS :1; //Supports Staggered Spin-up: When set to '1 , indicates that the HBA supports staggered spin-up on its ports, for use in balancing power spikes. This value is loaded by the BIOS prior to OS initialization.
+        UCHAR SMPS :1; //Supports Mechanical Presence Switch: ): When set to '1', the HBA supports mechanical presence switches on its ports for use in hot plug operations.  When cleared to '0', this function is not supported.  This value is loaded by the BIOS prior to OS initialization.
+        UCHAR SSNTF :1; //AHCI 1.1 Supports SNotification Register: When set to '1', indicates that the HBA supports the PxSNTF (SNotification) register and its associated functionality.  When cleared to '0', the HBA does not support the PxSNTF (SNotification) register and its associated functionality.  Refer to section 10.10.1.
+        UCHAR SNCQ :1; //Supports Native Command Queuing: Indicates whether the HBA supports Serial ATA native command queuing. If set to ?1 , an HBA shall handle DMA Setup FISes natively, and shall handle the auto-activate optimization through that FIS. If cleared to ?0 , native command queuing is not supported and software should not issue any native command queuing commands.
+        UCHAR S64A :1; //Supports 64-bit Addressing: Indicates whether the HBA can access 64-bit data structures. If true, the HBA shall make the 32-bit upper bits of the port DMA Descriptor, the PRD Base, and each PRD entry read/write. If cleared, these are read- only and treated as ?0 by the HBA.
         //MSB
     };
 
diff --git a/storage/miniports/storahci/src/entrypts.c b/storage/miniports/storahci/src/entrypts.c
index 71469e02..16078c49 100644
--- a/storage/miniports/storahci/src/entrypts.c
+++ b/storage/miniports/storahci/src/entrypts.c
@@ -614,7 +614,7 @@ Note:
     // Currently StorAHCI does not utilize CAP.NP. It remains useful to identify platform BIOSes
     // which may violate the specification.
     //
-    NT_ASSERT(portCount > 0 && portCount <= (adapterExtension->CAP.NP + 1));
+    NT_ASSERT(portCount > 0 && portCount <= (ULONG)(adapterExtension->CAP.NP + 1));
 
     //3.4 Initializing the rest of PORT_CONFIGURATION_INFORMATION
     ConfigInfo->MaximumTransferLength = AHCI_MAX_TRANSFER_LENGTH_DEFAULT;
@@ -890,7 +890,7 @@ AhciHwPassiveInitialize (
     _In_ PVOID AdapterExtension
     )
 {
-    UCHAR i;
+    ULONG i;
     ULONG status = STOR_STATUS_SUCCESS;
     BOOLEAN enableD3Cold = FALSE;
     BOOLEAN d3ColdSupported = FALSE;