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authorJianpeng Peng <[email protected]>2022-10-19 11:15:47 +0800
committerJianpeng Peng <[email protected]>2022-10-19 11:15:47 +0800
commitf6a1811657d2a2abc5ca6026bb340cb68942db0a (patch)
tree90e26f24189863a289d26ac2679a71a0f84c2501 /tests/projects/embed/gnu-rm/hello/src/startup_ARMCM3.S
parentd9595826e8f81ec19673adcce87e44931cf75c0f (diff)
Add rule and test project for gnu-rm.
Diffstat (limited to 'tests/projects/embed/gnu-rm/hello/src/startup_ARMCM3.S')
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diff --git a/tests/projects/embed/gnu-rm/hello/src/startup_ARMCM3.S b/tests/projects/embed/gnu-rm/hello/src/startup_ARMCM3.S
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+/**************************************************************************//**
+ * @file startup_ARMCM3.S
+ * @brief CMSIS-Core(M) Device Startup File for Cortex-M3 Device
+ * @version V2.2.0
+ * @date 26. May 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+ .globl __Vectors_End
+ .globl __Vectors_Size
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* -14 NMI Handler */
+ .long HardFault_Handler /* -13 Hard Fault Handler */
+ .long MemManage_Handler /* -12 MPU Fault Handler */
+ .long BusFault_Handler /* -11 Bus Fault Handler */
+ .long UsageFault_Handler /* -10 Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* -5 SVC Handler */
+ .long DebugMon_Handler /* -4 Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* -2 PendSV Handler */
+ .long SysTick_Handler /* -1 SysTick Handler */
+
+ /* Interrupts */
+ .long Interrupt0_Handler /* 0 Interrupt 0 */
+ .long Interrupt1_Handler /* 1 Interrupt 1 */
+ .long Interrupt2_Handler /* 2 Interrupt 2 */
+ .long Interrupt3_Handler /* 3 Interrupt 3 */
+ .long Interrupt4_Handler /* 4 Interrupt 4 */
+ .long Interrupt5_Handler /* 5 Interrupt 5 */
+ .long Interrupt6_Handler /* 6 Interrupt 6 */
+ .long Interrupt7_Handler /* 7 Interrupt 7 */
+ .long Interrupt8_Handler /* 8 Interrupt 8 */
+ .long Interrupt9_Handler /* 9 Interrupt 9 */
+
+ .space (214 * 4) /* Interrupts 10 .. 224 are left out */
+__Vectors_End:
+ .equ __Vectors_Size, __Vectors_End - __Vectors
+ .size __Vectors, . - __Vectors
+
+
+ .thumb
+ .section .text
+ .align 2
+
+ .thumb_func
+ .type Reset_Handler, %function
+ .globl Reset_Handler
+ .fnstart
+Reset_Handler:
+ bl SystemInit
+
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4] /* source address */
+ ldr r2, [r4, #4] /* destination address */
+ ldr r3, [r4, #8] /* word count */
+ lsls r3, r3, #2 /* byte count */
+
+.L_loop0_0:
+ subs r3, #4 /* decrement byte count */
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+.L_loop0_done:
+
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3] /* destination address */
+ ldr r2, [r3, #4] /* word count */
+ lsls r2, r2, #2 /* byte count */
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4 /* decrement byte count */
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+
+ bl _start
+
+ .fnend
+ .size Reset_Handler, . - Reset_Handler
+
+/* The default macro is not used for HardFault_Handler
+ * because this results in a poor debug illusion.
+ */
+ .thumb_func
+ .type HardFault_Handler, %function
+ .weak HardFault_Handler
+ .fnstart
+HardFault_Handler:
+ b .
+ .fnend
+ .size HardFault_Handler, . - HardFault_Handler
+
+ .thumb_func
+ .type Default_Handler, %function
+ .weak Default_Handler
+ .fnstart
+Default_Handler:
+ b .
+ .fnend
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default exception/interrupt handlers.
+ * Default handler are weak symbols with an endless loop.
+ * They can be overwritten by real handlers.
+ */
+ .macro Set_Default_Handler Handler_Name
+ .weak \Handler_Name
+ .set \Handler_Name, Default_Handler
+ .endm
+
+
+/* Default exception/interrupt handler */
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+
+ .end