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Age	Commit message (Collapse)	Author
2026-02-11	lib: utils/cache: add Andes last level cache controller	Ben Zong-You Xie
	Introduce a FDT-based driver for the Andes Last Level Cache (LLC) controller to support cache maintenance operations. Signed-off-by: Ben Zong-You Xie <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Anup Patel <[email protected]>
2025-12-08	lib: utils/cache: Add SiFive Extensible Cache (EC) driver	Nick Hu
	Add support for SiFive Extensible Cache (EC) controller with multi-slice architecture. The driver implements cache maintenance operations through MMIO register interface. Co-developed-by: Vincent Chen <[email protected]> Signed-off-by: Vincent Chen <[email protected]> Co-developed-by: Samuel Holland <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Co-developed-by: Yong-Xuan Wang <[email protected]> Signed-off-by: Yong-Xuan Wang <[email protected]> Signed-off-by: Nick Hu <[email protected]> Reviewed-by: Anup Patel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Anup Patel <[email protected]>
2025-12-08	lib: utils/cache: Add SiFive PL2 controller	Nick Hu
	SiFive Private L2(PL2) cache is a private cache owned by each hart. Add this driver to support private cache flush operations via the MMIO registers. Co-developed-by: Eric Lin <[email protected]> Signed-off-by: Eric Lin <[email protected]> Co-developed-by: Zong Li <[email protected]> Signed-off-by: Zong Li <[email protected]> Co-developed-by: Vincent Chen <[email protected]> Signed-off-by: Vincent Chen <[email protected]> Co-developed-by: Samuel Holland <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Signed-off-by: Nick Hu <[email protected]> Reviewed-by: Anup Patel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Anup Patel <[email protected]>
2025-10-28	lib: utils/cache: Add fdt cmo helpers	Nick Hu
	Add the helpers to build up the cache hierarchy via FDT and provide some cmo functions for the user who want to flush the entire cache. Signed-off-by: Nick Hu <[email protected]> Reviewed-by: Samuel Holland <[email protected]> Reviewed-by: Anup Patel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Anup Patel <[email protected]>
2025-10-28	utils: cache: Add SiFive ccache controller	Vincent Chen
	SiFive Composable cache is a L3 share cache of the core complex. Add this driver to support the share cache maintenance operations via the MMIO registers. Co-developed-by: Samuel Holland <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Signed-off-by: Vincent Chen <[email protected]> Co-developed-by: Nick Hu <[email protected]> Signed-off-by: Nick Hu <[email protected]> Reviewed-by: Samuel Holland <[email protected]> Reviewed-by: Anup Patel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Anup Patel <[email protected]>
2025-10-28	lib: utils: Add FDT cache library	Nick Hu
	Add the FDT cache library so we can build up the cache topology via the 'next-level-cache' DT property. Co-developed-by: Vincent Chen <[email protected]> Signed-off-by: Vincent Chen <[email protected]> Co-developed-by: Andy Chiu <[email protected]> Signed-off-by: Andy Chiu <[email protected]> Signed-off-by: Nick Hu <[email protected]> Reviewed-by: Samuel Holland <[email protected]> Reviewed-by: Anup Patel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Anup Patel <[email protected]>
2025-10-28	lib: utils: Add cache flush library	Nick Hu
	The current RISC-V CMO only defines how to flush a cache block. However, certain use cases, such as power management, may require flushing the entire cache. Therefore, a framework is being introduced to allow vendors to flush the entire cache using their own methods. Signed-off-by: Nick Hu <[email protected]> Reviewed-by: Samuel Holland <[email protected]> Reviewed-by: Anup Patel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Anup Patel <[email protected]>