feat: improve startup flow

1. remove gpio&uart INIT_BOARD_EXPORT
2. init gpio&uart in rt_hw_board_init
3. add clock driver

9 files changed, 299 insertions, 3 deletions

diff --git a/bsp/n32g452xx/Libraries/rt_drivers/SConscript b/bsp/n32g452xx/Libraries/rt_drivers/SConscript
index 1298ec7063..4976568157 100755
--- a/bsp/n32g452xx/Libraries/rt_drivers/SConscript
+++ b/bsp/n32g452xx/Libraries/rt_drivers/SConscript
@@ -10,6 +10,7 @@ src = Split("""
 """)
 
 src += ['drv_common.c']
+src += ['drv_clk.c']
 
 if GetDepend(['RT_USING_PIN']):
     src += ['drv_gpio.c']
diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_clk.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_clk.c
new file mode 100755
index 0000000000..9af2d83e60
--- /dev/null
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_clk.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-20     breo.com     first version
+ */
+
+#include "drv_clk.h"
+#include "board.h"
+
+void DumpClock(const char *msg)
+{
+    RCC_ClocksType RCC_ClockFreq;
+    rt_kprintf("--------------------------------\n");
+    rt_kprintf("%s:\n", msg);
+    RCC_GetClocksFreqValue(&RCC_ClockFreq);
+    rt_kprintf("SYSCLK: %d\n", RCC_ClockFreq.SysclkFreq);
+    rt_kprintf("HCLK: %d\n", RCC_ClockFreq.HclkFreq);
+    rt_kprintf("PCLK1: %d\n", RCC_ClockFreq.Pclk1Freq);
+    rt_kprintf("PCLK2: %d\n", RCC_ClockFreq.Pclk2Freq);
+}
+
+void SetSysClockToHSI(void)
+{
+    RCC_DeInit();
+
+    RCC_EnableHsi(ENABLE);
+
+    /* Enable Prefetch Buffer */
+    FLASH_PrefetchBufSet(FLASH_PrefetchBuf_EN);
+
+    /* Flash 0 wait state */
+    FLASH_SetLatency(FLASH_LATENCY_0);
+
+    /* HCLK = SYSCLK */
+    RCC_ConfigHclk(RCC_SYSCLK_DIV1);
+
+    /* PCLK2 = HCLK */
+    RCC_ConfigPclk2(RCC_HCLK_DIV1);
+
+    /* PCLK1 = HCLK */
+    RCC_ConfigPclk1(RCC_HCLK_DIV1);
+
+    /* Select HSE as system clock source */
+    RCC_ConfigSysclk(RCC_SYSCLK_SRC_HSI);
+
+    /* Wait till PLL is used as system clock source */
+    while (RCC_GetSysclkSrc() != 0x00)
+    {
+    }
+}
+
+/**
+ * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+ *         and PCLK1 prescalers.
+ */
+void SetSysClockToHSE(void)
+{
+    ErrorStatus HSEStartUpStatus;
+
+    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration
+     * -----------------------------*/
+    /* RCC system reset(for debug purpose) */
+    RCC_DeInit();
+
+    /* Enable HSE */
+    RCC_ConfigHse(RCC_HSE_ENABLE);
+
+    /* Wait till HSE is ready */
+    HSEStartUpStatus = RCC_WaitHseStable();
+
+    if (HSEStartUpStatus == SUCCESS)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH_PrefetchBufSet(FLASH_PrefetchBuf_EN);
+
+        if (HSE_Value <= 32000000)
+        {
+            /* Flash 0 wait state */
+            FLASH_SetLatency(FLASH_LATENCY_0);
+        }
+        else
+        {
+            /* Flash 1 wait state */
+            FLASH_SetLatency(FLASH_LATENCY_1);
+        }
+
+        /* HCLK = SYSCLK */
+        RCC_ConfigHclk(RCC_SYSCLK_DIV1);
+
+        /* PCLK2 = HCLK */
+        RCC_ConfigPclk2(RCC_HCLK_DIV1);
+
+        /* PCLK1 = HCLK */
+        RCC_ConfigPclk1(RCC_HCLK_DIV1);
+
+        /* Select HSE as system clock source */
+        RCC_ConfigSysclk(RCC_SYSCLK_SRC_HSE);
+
+        /* Wait till HSE is used as system clock source */
+        while (RCC_GetSysclkSrc() != 0x04)
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+           configuration. User can add here some code to deal with this error */
+
+        /* Go to infinite loop */
+        while (1)
+        {
+        }
+    }
+}
+
+void SetSysClockToPLL(uint32_t freq, uint8_t src)
+{
+    uint32_t pllsrc = (src == SYSCLK_PLLSRC_HSI ? RCC_PLL_SRC_HSI_DIV2 : RCC_PLL_SRC_HSE_DIV2);
+    uint32_t pllmul;
+    uint32_t latency;
+    uint32_t pclk1div, pclk2div;
+    ErrorStatus HSEStartUpStatus;
+
+    if (HSE_VALUE != 8000000)
+    {
+        /* HSE_VALUE == 8000000 is needed in this project! */
+        while (1)
+            ;
+    }
+
+    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration
+     * -----------------------------*/
+    /* RCC system reset(for debug purpose) */
+    RCC_DeInit();
+
+    if (src == SYSCLK_PLLSRC_HSE)
+    {
+        /* Enable HSE */
+        RCC_ConfigHse(RCC_HSE_ENABLE);
+
+        /* Wait till HSE is ready */
+        HSEStartUpStatus = RCC_WaitHseStable();
+
+        if (HSEStartUpStatus != SUCCESS)
+        {
+            /* If HSE fails to start-up, the application will have wrong clock
+               configuration. User can add here some code to deal with this
+               error */
+
+            /* Go to infinite loop */
+            while (1)
+                ;
+        }
+    }
+
+    switch (freq)
+    {
+    case 24000000:
+        latency  = FLASH_LATENCY_0;
+        pllmul   = RCC_PLL_MUL_6;
+        pclk1div = RCC_HCLK_DIV1;
+        pclk2div = RCC_HCLK_DIV1;
+        break;
+    case 36000000:
+        latency  = FLASH_LATENCY_1;
+        pllmul   = RCC_PLL_MUL_9;
+        pclk1div = RCC_HCLK_DIV1;
+        pclk2div = RCC_HCLK_DIV1;
+        break;
+    case 48000000:
+        latency  = FLASH_LATENCY_1;
+        pllmul   = RCC_PLL_MUL_12;
+        pclk1div = RCC_HCLK_DIV2;
+        pclk2div = RCC_HCLK_DIV1;
+        break;
+    case 56000000:
+        latency  = FLASH_LATENCY_1;
+        pllmul   = RCC_PLL_MUL_14;
+        pclk1div = RCC_HCLK_DIV2;
+        pclk2div = RCC_HCLK_DIV1;
+        break;
+    case 72000000:
+        latency  = FLASH_LATENCY_2;
+        pllmul   = RCC_PLL_MUL_18;
+        pclk1div = RCC_HCLK_DIV2;
+        pclk2div = RCC_HCLK_DIV1;
+        break;
+    case 96000000:
+        latency  = FLASH_LATENCY_2;
+        pllmul   = RCC_PLL_MUL_24;
+        pclk1div = RCC_HCLK_DIV4;
+        pclk2div = RCC_HCLK_DIV2;
+        break;
+    case 128000000:
+        latency  = FLASH_LATENCY_3;
+        pllmul   = RCC_PLL_MUL_32;
+        pclk1div = RCC_HCLK_DIV4;
+        pclk2div = RCC_HCLK_DIV2;
+        break;
+    case 144000000:
+        /* must use HSE as PLL source */
+        latency  = FLASH_LATENCY_4;
+        pllsrc   = RCC_PLL_SRC_HSE_DIV1;
+        pllmul   = RCC_PLL_MUL_18;
+        pclk1div = RCC_HCLK_DIV4;
+        pclk2div = RCC_HCLK_DIV2;
+        break;
+    default:
+        while (1)
+            ;
+    }
+
+    FLASH_SetLatency(latency);
+
+    /* HCLK = SYSCLK */
+    RCC_ConfigHclk(RCC_SYSCLK_DIV1);
+
+    /* PCLK2 = HCLK */
+    RCC_ConfigPclk2(pclk2div);
+
+    /* PCLK1 = HCLK */
+    RCC_ConfigPclk1(pclk1div);
+
+    RCC_ConfigPll(pllsrc, pllmul);
+
+    /* Enable PLL */
+    RCC_EnablePll(ENABLE);
+
+    /* Wait till PLL is ready */
+    while (RCC_GetFlagStatus(RCC_FLAG_PLLRD) == RESET)
+        ;
+
+    /* Select PLL as system clock source */
+    RCC_ConfigSysclk(RCC_SYSCLK_SRC_PLLCLK);
+
+    /* Wait till PLL is used as system clock source */
+    while (RCC_GetSysclkSrc() != 0x08)
+        ;
+}
+
diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_clk.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_clk.h
new file mode 100755
index 0000000000..d61d64fc8c
--- /dev/null
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_clk.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-20     breo.com     first version
+ */
+
+#ifndef __DRV_CLK_H__
+#define __DRV_CLK_H__
+
+#include <stdint.h>
+#include <rtthread.h>
+#include <rthw.h>
+#ifdef RT_USING_DEVICE
+    #include <rtdevice.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void DumpClock(const char *msg);
+void SetSysClockToHSI(void);
+void SetSysClockToHSE(void);
+
+enum
+{
+    SYSCLK_PLLSRC_HSI,
+    SYSCLK_PLLSRC_HSE,
+};
+void SetSysClockToPLL(uint32_t freq, uint8_t src);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c
index 690253959f..0552232473 100644
--- a/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c
@@ -763,7 +763,6 @@ int n32_hw_pin_init(void)
     result = rt_device_pin_register("pin", &_n32_pin_ops, RT_NULL);
     return result;
 }
-INIT_BOARD_EXPORT(n32_hw_pin_init);
 
 rt_inline void pin_irq_hdr(int irqno)
 {
diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.h
index ae9bda7dce..f991436bb4 100644
--- a/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.h
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.h
@@ -10,5 +10,6 @@
 #ifndef GPIO_H__
 #define GPIO_H__
 
+int n32_hw_pin_init(void);
 
 #endif
diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c
index 3f5ebf450c..1feb0ac7e2 100644
--- a/bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c
@@ -214,7 +214,6 @@ int rt_hw_i2c_init(void)
 
     return RT_EOK;
 }
-
 INIT_BOARD_EXPORT(rt_hw_i2c_init);
 
 #endif /* RT_USING_I2C */
diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c b/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c
index fae6668671..e7238c925c 100644
--- a/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c
@@ -554,5 +554,4 @@ int rt_hw_usart_init(void)
 
     return RT_EOK;
 }
-INIT_BOARD_EXPORT(rt_hw_usart_init);
 
diff --git a/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.h b/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.h
index 4059092706..c8ca6a78cd 100644
--- a/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.h
+++ b/bsp/n32g452xx/Libraries/rt_drivers/drv_usart.h
@@ -11,5 +11,6 @@
 #ifndef __USART_H__
 #define __USART_H__
 
+int rt_hw_usart_init(void);
 
 #endif
diff --git a/bsp/n32g452xx/n32g452xx-mini-system/board/board.c b/bsp/n32g452xx/n32g452xx-mini-system/board/board.c
index f5fd86b932..533cb15d35 100644
--- a/bsp/n32g452xx/n32g452xx-mini-system/board/board.c
+++ b/bsp/n32g452xx/n32g452xx-mini-system/board/board.c
@@ -13,6 +13,7 @@
 #include <rtthread.h>
 
 #include <board.h>
+#include <drv_clk.h>
 
 #ifdef BSP_USING_SRAM
     #include "drv_sram.h"
@@ -72,6 +73,16 @@ void rt_hw_board_init()
 
     SystemClock_Config();
 
+#ifdef RT_USING_PIN
+    int n32_hw_pin_init(void);
+    n32_hw_pin_init();
+#endif
+
+#ifdef RT_USING_SERIAL
+    int rt_hw_usart_init(void);
+    rt_hw_usart_init();
+#endif
+
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif