Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5

[lts 3.1.x] format codes

12 files changed, 1791 insertions, 1791 deletions

diff --git a/bsp/dm365/platform/dm365.c b/bsp/dm365/platform/dm365.c
index 376bbeb115..0fe2d0a94a 100644
--- a/bsp/dm365/platform/dm365.c
+++ b/bsp/dm365/platform/dm365.c
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 #include <edma.h>
@@ -26,285 +26,285 @@ static rt_uint32_t vpssrate, vencrate_sd, vencrate_hd;
 /* Four Transfer Controllers on DM365 */
 static const rt_int8_t
 dm365_queue_tc_mapping[][2] = {
-	/* {event queue no, TC no} */
-	{0, 0},
-	{1, 1},
-	{2, 2},
-	{3, 3},
-	{-1, -1},
+    /* {event queue no, TC no} */
+    {0, 0},
+    {1, 1},
+    {2, 2},
+    {3, 3},
+    {-1, -1},
 };
 
 static const rt_int8_t
 dm365_queue_priority_mapping[][2] = {
-	/* {event queue no, Priority} */
-	{0, 7},
-	{1, 7},
-	{2, 7},
-	{3, 0},
-	{-1, -1},
+    /* {event queue no, Priority} */
+    {0, 7},
+    {1, 7},
+    {2, 7},
+    {3, 0},
+    {-1, -1},
 };
 
 static struct edma_soc_info edma_cc0_info = {
-	.n_channel		= 64,
-	.n_region		= 4,
-	.n_slot			= 256,
-	.n_tc			= 4,
-	.n_cc			= 1,
-	.queue_tc_mapping	= dm365_queue_tc_mapping,
-	.queue_priority_mapping	= dm365_queue_priority_mapping,
-	.default_queue		= EVENTQ_3,
+    .n_channel      = 64,
+    .n_region       = 4,
+    .n_slot         = 256,
+    .n_tc           = 4,
+    .n_cc           = 1,
+    .queue_tc_mapping   = dm365_queue_tc_mapping,
+    .queue_priority_mapping = dm365_queue_priority_mapping,
+    .default_queue      = EVENTQ_3,
 };
 
 static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = {
-	&edma_cc0_info,
+    &edma_cc0_info,
 };
 
 static rt_list_t clocks;
 
 struct clk {
-	char name[32];
-	rt_uint32_t *rate_hz;
-	struct clk *parent;
-	rt_list_t  node;
+    char name[32];
+    rt_uint32_t *rate_hz;
+    struct clk *parent;
+    rt_list_t  node;
 };
 
 static struct clk davinci_dm365_clks[] = {
-	{
-		.name = "ARMCLK",
-		.rate_hz = &armrate,
-	},
-	{
-		.name = "UART0",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "UART1",
-		.rate_hz = &commonrate,
-	},
-	{
-		.name = "HPI",
-		.rate_hz = &commonrate,
-	},
-	{
-		.name = "EMACCLK",
-		.rate_hz = &commonrate,
-	},
-	{
-		.name = "I2CCLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "McBSPCLK",
-		.rate_hz = &commonrate,
-	},
-	{
-		.name = "MMCSDCLK0",
-		.rate_hz = &mmcsdrate,
-	},
-	{
-		.name = "MMCSDCLK1",
-		.rate_hz = &mmcsdrate,
-	},
-	{
-		.name = "SPICLK",
-		.rate_hz = &commonrate,
-	},
-	{
-		.name = "gpio",
-		.rate_hz = &commonrate,
-	},
-	{
-		.name = "AEMIFCLK",
-		.rate_hz = &commonrate,
-	},
-	{
-		.name = "PWM0_CLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "PWM1_CLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "PWM2_CLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "PWM3_CLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "USBCLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "VOICECODEC_CLK",
-		.rate_hz = &voicerate,
-	},
-	{
-		.name = "RTC_CLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "KEYSCAN_CLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "ADCIF_CLK",
-		.rate_hz = &fixedrate,
-	},
+    {
+        .name = "ARMCLK",
+        .rate_hz = &armrate,
+    },
+    {
+        .name = "UART0",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "UART1",
+        .rate_hz = &commonrate,
+    },
+    {
+        .name = "HPI",
+        .rate_hz = &commonrate,
+    },
+    {
+        .name = "EMACCLK",
+        .rate_hz = &commonrate,
+    },
+    {
+        .name = "I2CCLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "McBSPCLK",
+        .rate_hz = &commonrate,
+    },
+    {
+        .name = "MMCSDCLK0",
+        .rate_hz = &mmcsdrate,
+    },
+    {
+        .name = "MMCSDCLK1",
+        .rate_hz = &mmcsdrate,
+    },
+    {
+        .name = "SPICLK",
+        .rate_hz = &commonrate,
+    },
+    {
+        .name = "gpio",
+        .rate_hz = &commonrate,
+    },
+    {
+        .name = "AEMIFCLK",
+        .rate_hz = &commonrate,
+    },
+    {
+        .name = "PWM0_CLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "PWM1_CLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "PWM2_CLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "PWM3_CLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "USBCLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "VOICECODEC_CLK",
+        .rate_hz = &voicerate,
+    },
+    {
+        .name = "RTC_CLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "KEYSCAN_CLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "ADCIF_CLK",
+        .rate_hz = &fixedrate,
+    },
 };
 
 /* clocks cannot be de-registered no refcounting necessary */
 struct clk *clk_get(const char *id)
 {
-	struct clk *clk;
-	rt_list_t *list;
-	
-	for (list = (&clocks)->next; list != &clocks; list = list->next)
-	{
-		clk = (struct clk *)rt_list_entry(list, struct clk, node);
-		if (rt_strcmp(id, clk->name) == 0)
-			return clk;
-	}
+    struct clk *clk;
+    rt_list_t *list;
 
-	return RT_NULL;
+    for (list = (&clocks)->next; list != &clocks; list = list->next)
+    {
+        clk = (struct clk *)rt_list_entry(list, struct clk, node);
+        if (rt_strcmp(id, clk->name) == 0)
+            return clk;
+    }
+
+    return RT_NULL;
 }
 
 rt_uint32_t clk_get_rate(struct clk *clk)
 {
-	rt_uint32_t	flags;
-	rt_uint32_t	*rate;
+    rt_uint32_t flags;
+    rt_uint32_t *rate;
 
-	for (;;) {
-		rate = clk->rate_hz;
-		if (rate || !clk->parent)
-			break;
-		clk = clk->parent;
-	}
-	return *rate;
+    for (;;) {
+        rate = clk->rate_hz;
+        if (rate || !clk->parent)
+            break;
+        clk = clk->parent;
+    }
+    return *rate;
 }
 
 void clk_register(struct clk *clk)
 {
-	rt_list_insert_after(&clocks, &clk->node);
+    rt_list_insert_after(&clocks, &clk->node);
 }
 
 int davinci_register_clks(struct clk *clk_list, int num_clks)
 {
-	struct clk *clkp;
-	int i;
+    struct clk *clkp;
+    int i;
 
-	for (i = 0, clkp = clk_list; i < num_clks; i++, clkp++)
-	{
-		//rt_kprintf("1:%s\n", clkp->name);
-		clk_register(clkp);
-		//rt_kprintf("2:%s\n", clkp->name);
-	}
+    for (i = 0, clkp = clk_list; i < num_clks; i++, clkp++)
+    {
+        //rt_kprintf("1:%s\n", clkp->name);
+        clk_register(clkp);
+        //rt_kprintf("2:%s\n", clkp->name);
+    }
 
-	return 0;
+    return 0;
 }
 
 /* PLL/Reset register offsets */
-#define PLLM		0x110
-#define PREDIV		0x114
-#define PLLDIV2		0x11C
-#define POSTDIV		0x128
-#define PLLDIV4		0x160
-#define PLLDIV5		0x164
-#define PLLDIV6		0x168
-#define PLLDIV7		0x16C
-#define PLLDIV8		0x170
+#define PLLM        0x110
+#define PREDIV      0x114
+#define PLLDIV2     0x11C
+#define POSTDIV     0x128
+#define PLLDIV4     0x160
+#define PLLDIV5     0x164
+#define PLLDIV6     0x168
+#define PLLDIV7     0x16C
+#define PLLDIV8     0x170
 
 
 int davinci_clk_init(void)
 {
-	struct clk *clk_list;
-	int num_clks;
-	rt_uint32_t pll0_mult, pll1_mult;
+    struct clk *clk_list;
+    int num_clks;
+    rt_uint32_t pll0_mult, pll1_mult;
 
-	unsigned long prediv, postdiv;
-	unsigned long pll_rate;
-	unsigned long pll_div2, pll_div4, pll_div5,
-		pll_div6, pll_div7, pll_div8;
+    unsigned long prediv, postdiv;
+    unsigned long pll_rate;
+    unsigned long pll_div2, pll_div4, pll_div5,
+        pll_div6, pll_div7, pll_div8;
 
-	rt_list_init(&clocks);
+    rt_list_init(&clocks);
 
-	//davinci_psc_register(davinci_psc_base, 1);
+    //davinci_psc_register(davinci_psc_base, 1);
 
-	pll0_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM);
-	pll1_mult = davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLM);
+    pll0_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM);
+    pll1_mult = davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLM);
 
-	commonrate = ((pll0_mult + 1) * 27000000) / 6;
-	armrate = ((pll0_mult + 1) * 27000000) / 2;
+    commonrate = ((pll0_mult + 1) * 27000000) / 6;
+    armrate = ((pll0_mult + 1) * 27000000) / 2;
 
-	fixedrate = 24000000;
+    fixedrate = 24000000;
 
-	/* Read PLL0 configuration */
-	prediv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PREDIV) &
-			0x1f) + 1;
-	postdiv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + POSTDIV) &
-			0x1f) + 1;
+    /* Read PLL0 configuration */
+    prediv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PREDIV) &
+            0x1f) + 1;
+    postdiv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + POSTDIV) &
+            0x1f) + 1;
 
-	/* PLL0 dividers */
-	pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV4) &
-			0x1f) + 1; /* EDMA, EMAC, config, common */
-	pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV5) &
-			0x1f) + 1; /* VPSS */
-	pll_div6 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV6) &
-			0x1f) + 1; /* VENC */
-	pll_div7 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV7) &
-			0x1f) + 1; /* DDR */
-	pll_div8 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV8) &
-			0x1f) + 1; /* MMC/SD */
+    /* PLL0 dividers */
+    pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV4) &
+            0x1f) + 1; /* EDMA, EMAC, config, common */
+    pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV5) &
+            0x1f) + 1; /* VPSS */
+    pll_div6 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV6) &
+            0x1f) + 1; /* VENC */
+    pll_div7 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV7) &
+            0x1f) + 1; /* DDR */
+    pll_div8 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV8) &
+            0x1f) + 1; /* MMC/SD */
 
-	pll_rate = ((fixedrate / prediv) * (2 * pll0_mult)) / postdiv;
+    pll_rate = ((fixedrate / prediv) * (2 * pll0_mult)) / postdiv;
 
-	commonrate = pll_rate / pll_div4; /* 486/4 = 121.5MHz */
-	vpssrate = pll_rate / pll_div5; /* 486/2 = 243MHz */
-	vencrate_sd = pll_rate / pll_div6; /* 486/18 =  27MHz */
-	ddrrate = pll_rate / pll_div7; /* 486/2 = 243MHz */
-	mmcsdrate = pll_rate / pll_div8; /* 486/4 =  121.5MHz */
+    commonrate = pll_rate / pll_div4; /* 486/4 = 121.5MHz */
+    vpssrate = pll_rate / pll_div5; /* 486/2 = 243MHz */
+    vencrate_sd = pll_rate / pll_div6; /* 486/18 =  27MHz */
+    ddrrate = pll_rate / pll_div7; /* 486/2 = 243MHz */
+    mmcsdrate = pll_rate / pll_div8; /* 486/4 =  121.5MHz */
 
-	rt_kprintf(
-		"PLL0: fixedrate: %d, commonrate: %d, vpssrate: %d\n",
-		fixedrate, commonrate, vpssrate);
-	rt_kprintf(
-		"PLL0: vencrate_sd: %d, ddrrate: %d mmcsdrate: %d\n",
-		vencrate_sd, (ddrrate/2), mmcsdrate);
+    rt_kprintf(
+        "PLL0: fixedrate: %d, commonrate: %d, vpssrate: %d\n",
+        fixedrate, commonrate, vpssrate);
+    rt_kprintf(
+        "PLL0: vencrate_sd: %d, ddrrate: %d mmcsdrate: %d\n",
+        vencrate_sd, (ddrrate/2), mmcsdrate);
 
-	/* Read PLL1 configuration */
-	prediv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PREDIV) &
-			0x1f) + 1;
-	postdiv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + POSTDIV) &
-			0x1f) + 1;
-	pll_rate = ((fixedrate / prediv) * (2 * pll1_mult)) / postdiv;
+    /* Read PLL1 configuration */
+    prediv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PREDIV) &
+            0x1f) + 1;
+    postdiv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + POSTDIV) &
+            0x1f) + 1;
+    pll_rate = ((fixedrate / prediv) * (2 * pll1_mult)) / postdiv;
 
-	/* PLL1 dividers */
-	pll_div2 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV2) &
-			0x1f) + 1; /* ARM */
-	pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV4) &
-			0x1f) + 1; /* VOICE */
-	pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV5) &
-			0x1f) + 1; /* VENC */
+    /* PLL1 dividers */
+    pll_div2 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV2) &
+            0x1f) + 1; /* ARM */
+    pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV4) &
+            0x1f) + 1; /* VOICE */
+    pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV5) &
+            0x1f) + 1; /* VENC */
 
-	armrate = pll_rate / pll_div2; /* 594/2 = 297MHz */
-	voicerate = pll_rate / pll_div4; /* 594/6 = 99MHz */
-	vencrate_hd = pll_rate / pll_div5; /* 594/8 = 74.25MHz */
+    armrate = pll_rate / pll_div2; /* 594/2 = 297MHz */
+    voicerate = pll_rate / pll_div4; /* 594/6 = 99MHz */
+    vencrate_hd = pll_rate / pll_div5; /* 594/8 = 74.25MHz */
 
-	rt_kprintf(
-		"PLL1: armrate: %d, voicerate: %d, vencrate_hd: %d\n",
-		armrate, voicerate, vencrate_hd);
+    rt_kprintf(
+        "PLL1: armrate: %d, voicerate: %d, vencrate_hd: %d\n",
+        armrate, voicerate, vencrate_hd);
 
-	clk_list = davinci_dm365_clks;
-	num_clks = ARRAY_SIZE(davinci_dm365_clks); 
+    clk_list = davinci_dm365_clks;
+    num_clks = ARRAY_SIZE(davinci_dm365_clks);
 
-	return davinci_register_clks(clk_list, num_clks);
+    return davinci_register_clks(clk_list, num_clks);
 }
 
 int platform_init(void)
 {
-	edma_init(dm365_edma_info);
+    edma_init(dm365_edma_info);
 }
 
 INIT_BOARD_EXPORT(platform_init);
@@ -312,44 +312,44 @@ INIT_BOARD_EXPORT(platform_init);
 /* Reset board using the watchdog timer */
 void reset_system(void)
 {
-	rt_uint32_t tgcr, wdtcr;
-	rt_uint32_t base = DAVINCI_WDOG_BASE;
+    rt_uint32_t tgcr, wdtcr;
+    rt_uint32_t base = DAVINCI_WDOG_BASE;
 
-	/* Disable, internal clock source */
-	davinci_writel(0, base + TCR);
+    /* Disable, internal clock source */
+    davinci_writel(0, base + TCR);
 
-	/* Reset timer, set mode to 64-bit watchdog, and unreset */
-	davinci_writel(0, base + TGCR);
-	tgcr =	(TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT) |
-		(TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
-		(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
-	davinci_writel(tgcr, base + TGCR);
+    /* Reset timer, set mode to 64-bit watchdog, and unreset */
+    davinci_writel(0, base + TGCR);
+    tgcr =  (TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT) |
+        (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
+        (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
+    davinci_writel(tgcr, base + TGCR);
 
-	/* Clear counter and period regs */
-	davinci_writel(0, base + TIM12);
-	davinci_writel(0, base + TIM34);
-	davinci_writel(0, base + PRD12);
-	davinci_writel(0, base + PRD34);
+    /* Clear counter and period regs */
+    davinci_writel(0, base + TIM12);
+    davinci_writel(0, base + TIM34);
+    davinci_writel(0, base + PRD12);
+    davinci_writel(0, base + PRD34);
 
-	/* Enable periodic mode */
-	davinci_writel(TCR_ENAMODE_PERIODIC << ENAMODE12_SHIFT, base + TCR);
+    /* Enable periodic mode */
+    davinci_writel(TCR_ENAMODE_PERIODIC << ENAMODE12_SHIFT, base + TCR);
 
-	/* Put watchdog in pre-active state */
-	wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
-		(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
-	davinci_writel(wdtcr, base + WDTCR);
+    /* Put watchdog in pre-active state */
+    wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
+        (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
+    davinci_writel(wdtcr, base + WDTCR);
 
-	/* Put watchdog in active state */
-	wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
-		(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
-	davinci_writel(wdtcr, base + WDTCR);
+    /* Put watchdog in active state */
+    wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
+        (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
+    davinci_writel(wdtcr, base + WDTCR);
 
-	/*
-	 * Write an invalid value to the WDKEY field to trigger
-	 * a watchdog reset.
-	 */
-	wdtcr = 0xDEADBEEF;
-	davinci_writel(wdtcr, base + WDTCR);
+    /*
+     * Write an invalid value to the WDKEY field to trigger
+     * a watchdog reset.
+     */
+    wdtcr = 0xDEADBEEF;
+    davinci_writel(wdtcr, base + WDTCR);
 }
 
 
diff --git a/bsp/dm365/platform/dm365_timer.h b/bsp/dm365/platform/dm365_timer.h
index 3bb1d761ed..93a0e3ef6b 100644
--- a/bsp/dm365/platform/dm365_timer.h
+++ b/bsp/dm365/platform/dm365_timer.h
@@ -4,57 +4,57 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 #ifndef __ASM_ARCH_TIME_H
 #define __ASM_ARCH_TIME_H
 
 /* Timer register offsets */
-#define PID12				0x0
-#define TIM12				0x10
-#define TIM34				0x14
-#define PRD12				0x18
-#define PRD34				0x1c
-#define TCR				0x20
-#define TGCR				0x24
-#define WDTCR				0x28
-#define CMP12(n)			(0x60 + ((n) << 2))
+#define PID12               0x0
+#define TIM12               0x10
+#define TIM34               0x14
+#define PRD12               0x18
+#define PRD34               0x1c
+#define TCR             0x20
+#define TGCR                0x24
+#define WDTCR               0x28
+#define CMP12(n)            (0x60 + ((n) << 2))
 
 /* Timer register bitfields */
-#define ENAMODE12_SHIFT 		6
-#define ENAMODE34_SHIFT 		22
-#define TCR_ENAMODE_DISABLE		0x0
-#define TCR_ENAMODE_ONESHOT		0x1
-#define TCR_ENAMODE_PERIODIC		0x2
-#define TCR_ENAMODE_MASK		0x3
+#define ENAMODE12_SHIFT         6
+#define ENAMODE34_SHIFT         22
+#define TCR_ENAMODE_DISABLE     0x0
+#define TCR_ENAMODE_ONESHOT     0x1
+#define TCR_ENAMODE_PERIODIC        0x2
+#define TCR_ENAMODE_MASK        0x3
 
-#define TGCR_TIMMODE_SHIFT		2
-#define TGCR_TIMMODE_64BIT_GP		0x0
-#define TGCR_TIMMODE_32BIT_UNCHAINED	0x1
-#define TGCR_TIMMODE_64BIT_WDOG 	0x2
-#define TGCR_TIMMODE_32BIT_CHAINED	0x3
+#define TGCR_TIMMODE_SHIFT      2
+#define TGCR_TIMMODE_64BIT_GP       0x0
+#define TGCR_TIMMODE_32BIT_UNCHAINED    0x1
+#define TGCR_TIMMODE_64BIT_WDOG     0x2
+#define TGCR_TIMMODE_32BIT_CHAINED  0x3
 
-#define TGCR_TIM12RS_SHIFT		0
-#define TGCR_TIM34RS_SHIFT		1
-#define TGCR_RESET			0x0
-#define TGCR_UNRESET			0x1
-#define TGCR_RESET_MASK 		0x3
+#define TGCR_TIM12RS_SHIFT      0
+#define TGCR_TIM34RS_SHIFT      1
+#define TGCR_RESET          0x0
+#define TGCR_UNRESET            0x1
+#define TGCR_RESET_MASK         0x3
 
-#define WDTCR_WDEN_SHIFT		14
-#define WDTCR_WDEN_DISABLE		0x0
-#define WDTCR_WDEN_ENABLE		0x1
-#define WDTCR_WDKEY_SHIFT		16
-#define WDTCR_WDKEY_SEQ0		0xA5C6
-#define WDTCR_WDKEY_SEQ1		0xDA7E
+#define WDTCR_WDEN_SHIFT        14
+#define WDTCR_WDEN_DISABLE      0x0
+#define WDTCR_WDEN_ENABLE       0x1
+#define WDTCR_WDKEY_SHIFT       16
+#define WDTCR_WDKEY_SEQ0        0xA5C6
+#define WDTCR_WDKEY_SEQ1        0xDA7E
 
 enum {
-	T0_BOT,
-	T0_TOP,
-	T1_BOT,
-	T1_TOP,
-	NUM_TIMERS
+    T0_BOT,
+    T0_TOP,
+    T1_BOT,
+    T1_TOP,
+    NUM_TIMERS
 };
 
 #endif /* __ASM_ARCH_TIME_H__ */
diff --git a/bsp/dm365/platform/dm36x.h b/bsp/dm365/platform/dm36x.h
index 1e7b4102be..2aa72a23ce 100644
--- a/bsp/dm365/platform/dm36x.h
+++ b/bsp/dm365/platform/dm36x.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 #ifndef __DM36X_H__
@@ -29,43 +29,43 @@ extern "C" {
 /*
  * Base register addresses
  */
-#define DAVINCI_DMA_3PCC_BASE			(0x01C00000)
-#define DAVINCI_DMA_3PTC0_BASE			(0x01C10000)
-#define DAVINCI_DMA_3PTC1_BASE			(0x01C10400)
-#define DAVINCI_I2C_BASE			(0x01C21000)
-#define DAVINCI_TIMER0_BASE			(0x01C21400)
-#define DAVINCI_TIMER1_BASE			(0x01C21800)
-#define DAVINCI_WDOG_BASE			(0x01C21C00)
-#define DAVINCI_PWM0_BASE			(0x01C22000)
-#define DAVINCI_PWM1_BASE			(0x01C22400)
-#define DAVINCI_PWM2_BASE			(0x01C22800)
-#define DAVINCI_SYSTEM_MODULE_BASE		(0x01C40000)
-#define DAVINCI_PLL_CNTRL0_BASE			(0x01C40800)
-#define DAVINCI_PLL_CNTRL1_BASE			(0x01C40C00)
-#define DAVINCI_PWR_SLEEP_CNTRL_BASE		(0x01C41000)
-#define DAVINCI_SYSTEM_DFT_BASE			(0x01C42000)
-#define DAVINCI_IEEE1394_BASE			(0x01C60000)
-#define DAVINCI_USB_OTG_BASE			(0x01C64000)
-#define DAVINCI_CFC_ATA_BASE			(0x01C66000)
-#define DAVINCI_SPI_BASE			(0x01C66800)
-#define DAVINCI_GPIO_BASE			(0x01C67000)
-#define DAVINCI_UHPI_BASE			(0x01C67800)
-#define DAVINCI_VPSS_REGS_BASE			(0x01C70000)
-#define DAVINCI_EMAC_CNTRL_REGS_BASE		(0x01C80000)
-#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	(0x01C81000)
-#define DAVINCI_EMAC_WRAPPER_RAM_BASE		(0x01C82000)
-#define DAVINCI_MDIO_CNTRL_REGS_BASE		(0x01C84000)
-#define DAVINCI_IMCOP_BASE			(0x01CC0000)
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		(0x01E00000)
-#define DAVINCI_VLYNQ_BASE			(0x01E01000)
-#define DAVINCI_MCBSP_BASE			(0x01E02000)
-#define DAVINCI_MMC_SD_BASE			(0x01E10000)
-#define DAVINCI_MS_BASE				(0x01E20000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	(0x02000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	(0x04000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	(0x06000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	(0x08000000)
-#define DAVINCI_VLYNQ_REMOTE_BASE		(0x0C000000)
+#define DAVINCI_DMA_3PCC_BASE           (0x01C00000)
+#define DAVINCI_DMA_3PTC0_BASE          (0x01C10000)
+#define DAVINCI_DMA_3PTC1_BASE          (0x01C10400)
+#define DAVINCI_I2C_BASE            (0x01C21000)
+#define DAVINCI_TIMER0_BASE         (0x01C21400)
+#define DAVINCI_TIMER1_BASE         (0x01C21800)
+#define DAVINCI_WDOG_BASE           (0x01C21C00)
+#define DAVINCI_PWM0_BASE           (0x01C22000)
+#define DAVINCI_PWM1_BASE           (0x01C22400)
+#define DAVINCI_PWM2_BASE           (0x01C22800)
+#define DAVINCI_SYSTEM_MODULE_BASE      (0x01C40000)
+#define DAVINCI_PLL_CNTRL0_BASE         (0x01C40800)
+#define DAVINCI_PLL_CNTRL1_BASE         (0x01C40C00)
+#define DAVINCI_PWR_SLEEP_CNTRL_BASE        (0x01C41000)
+#define DAVINCI_SYSTEM_DFT_BASE         (0x01C42000)
+#define DAVINCI_IEEE1394_BASE           (0x01C60000)
+#define DAVINCI_USB_OTG_BASE            (0x01C64000)
+#define DAVINCI_CFC_ATA_BASE            (0x01C66000)
+#define DAVINCI_SPI_BASE            (0x01C66800)
+#define DAVINCI_GPIO_BASE           (0x01C67000)
+#define DAVINCI_UHPI_BASE           (0x01C67800)
+#define DAVINCI_VPSS_REGS_BASE          (0x01C70000)
+#define DAVINCI_EMAC_CNTRL_REGS_BASE        (0x01C80000)
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE    (0x01C81000)
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE       (0x01C82000)
+#define DAVINCI_MDIO_CNTRL_REGS_BASE        (0x01C84000)
+#define DAVINCI_IMCOP_BASE          (0x01CC0000)
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE       (0x01E00000)
+#define DAVINCI_VLYNQ_BASE          (0x01E01000)
+#define DAVINCI_MCBSP_BASE          (0x01E02000)
+#define DAVINCI_MMC_SD_BASE         (0x01E10000)
+#define DAVINCI_MS_BASE             (0x01E20000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE    (0x02000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE    (0x04000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE    (0x06000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE    (0x08000000)
+#define DAVINCI_VLYNQ_REMOTE_BASE       (0x0C000000)
 
 
 /*
@@ -77,14 +77,14 @@ extern "C" {
  * In case of only one VLYNQ IP, define only the
  * 'LOW_VLYNQ_CONTROL_BASE'.
  */
-#define LOW_VLYNQ_CONTROL_BASE			DAVINCI_VLYNQ_BASE
+#define LOW_VLYNQ_CONTROL_BASE          DAVINCI_VLYNQ_BASE
 
-#define DM365_EMAC_BASE			(0x01D07000)
-#define DM365_EMAC_CNTRL_OFFSET		(0x0000)
-#define DM365_EMAC_CNTRL_MOD_OFFSET	(0x3000)
-#define DM365_EMAC_CNTRL_RAM_OFFSET	(0x1000)
-#define DM365_EMAC_MDIO_OFFSET		(0x4000)
-#define DM365_EMAC_CNTRL_RAM_SIZE	(0x2000)
+#define DM365_EMAC_BASE         (0x01D07000)
+#define DM365_EMAC_CNTRL_OFFSET     (0x0000)
+#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000)
+#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000)
+#define DM365_EMAC_MDIO_OFFSET      (0x4000)
+#define DM365_EMAC_CNTRL_RAM_SIZE   (0x2000)
 
 
 /*
@@ -96,117 +96,117 @@ extern "C" {
 /*
  * System module registers
  */
-#define PINMUX0		(DAVINCI_SYSTEM_MODULE_BASE + 0x00)
-#define PINMUX1		(DAVINCI_SYSTEM_MODULE_BASE + 0x04)
-#define PINMUX2		(DAVINCI_SYSTEM_MODULE_BASE + 0x08)
-#define PINMUX3		(DAVINCI_SYSTEM_MODULE_BASE + 0x0c)
-#define PINMUX4		(DAVINCI_SYSTEM_MODULE_BASE + 0x10)
+#define PINMUX0     (DAVINCI_SYSTEM_MODULE_BASE + 0x00)
+#define PINMUX1     (DAVINCI_SYSTEM_MODULE_BASE + 0x04)
+#define PINMUX2     (DAVINCI_SYSTEM_MODULE_BASE + 0x08)
+#define PINMUX3     (DAVINCI_SYSTEM_MODULE_BASE + 0x0c)
+#define PINMUX4     (DAVINCI_SYSTEM_MODULE_BASE + 0x10)
 
-#define DM365_ARM_INTMUX	(DAVINCI_SYSTEM_MODULE_BASE + 0x18)
-#define DM365_EDMA_EVTMUX	(DAVINCI_SYSTEM_MODULE_BASE + 0x1C)
-#define DAVINCI_PUPDCTL1	(DAVINCI_SYSTEM_MODULE_BASE + 0x7C)
+#define DM365_ARM_INTMUX    (DAVINCI_SYSTEM_MODULE_BASE + 0x18)
+#define DM365_EDMA_EVTMUX   (DAVINCI_SYSTEM_MODULE_BASE + 0x1C)
+#define DAVINCI_PUPDCTL1    (DAVINCI_SYSTEM_MODULE_BASE + 0x7C)
 
 
 
-#define ASYNC_EMIF_REVID	0x00
-#define ASYNC_EMIF_AWCCR	0x04
-#define ASYNC_EMIF_A1CR 	0x10
-#define ASYNC_EMIF_A2CR 	0x14
-#define ASYNC_EMIF_A3CR 	0x18
+#define ASYNC_EMIF_REVID    0x00
+#define ASYNC_EMIF_AWCCR    0x04
+#define ASYNC_EMIF_A1CR     0x10
+#define ASYNC_EMIF_A2CR     0x14
+#define ASYNC_EMIF_A3CR     0x18
 
 /*
  * Base register addresses common across DM355 and DM365
  */
-#define DM3XX_TIMER2_BASE		(0x01C20800)
-#define DM3XX_REALTIME_BASE		(0x01C20C00)
-#define DM3XX_PWM3_BASE			(0x01C22C00)
-#define DM3XX_SPI_BASE			(0x01C66000)
-#define DM3XX_SPI0_BASE			DM3XX_SPI_BASE
-#define DM3XX_SPI1_BASE			(0x01C66800)
-#define DM3XX_SPI2_BASE			(0x01C67800)
+#define DM3XX_TIMER2_BASE       (0x01C20800)
+#define DM3XX_REALTIME_BASE     (0x01C20C00)
+#define DM3XX_PWM3_BASE         (0x01C22C00)
+#define DM3XX_SPI_BASE          (0x01C66000)
+#define DM3XX_SPI0_BASE         DM3XX_SPI_BASE
+#define DM3XX_SPI1_BASE         (0x01C66800)
+#define DM3XX_SPI2_BASE         (0x01C67800)
 
 
 
 /*
  * DM365 base register address
  */
-#define DM365_DMA_3PTC2_BASE		(0x01C10800)
-#define DM365_DMA_3PTC3_BASE		(0x01C10C00)
-#define DM365_TIMER3_BASE		(0x01C23800)
-#define DM365_ADCIF_BASE		(0x01C23C00)
-#define DM365_SPI3_BASE			(0x01C68000)
-#define DM365_SPI4_BASE			(0x01C23000)
-#define DM365_RTC_BASE			(0x01C69000)
-#define DM365_KEYSCAN_BASE		(0x01C69400)
-#define DM365_UHPI_BASE			(0x01C69800)
-#define DM365_IMCOP_BASE		(0x01CA0000)
-#define DM365_MMC_SD1_BASE		(0x01D00000)
-#define DM365_MCBSP_BASE		(0x01D02000)
-#define DM365_UART1_BASE		(0x01D06000)
-#define DM365_EMAC_CNTRL_BASE		(0x01D07000)
-#define DM365_EMAC_WRAP_RAM_BASE	(0x01D08000)
-#define DM365_EMAC_WRAP_CNTRL_BASE	(0x01D0A000)
-#define DM365_EMAC_MDIO_BASE		(0x01D0B000)
-#define DM365_VOICE_CODEC_BASE		(0x01D0C000)
-#define DM365_ASYNC_EMIF_CNTRL_BASE	(0x01D10000)
-#define DM365_MMC_SD0_BASE		(0x01D11000)
-#define DM365_MS_BASE			(0x01D20000)
-#define DM365_KALEIDO_BASE		(0x01E00000)
+#define DM365_DMA_3PTC2_BASE        (0x01C10800)
+#define DM365_DMA_3PTC3_BASE        (0x01C10C00)
+#define DM365_TIMER3_BASE       (0x01C23800)
+#define DM365_ADCIF_BASE        (0x01C23C00)
+#define DM365_SPI3_BASE         (0x01C68000)
+#define DM365_SPI4_BASE         (0x01C23000)
+#define DM365_RTC_BASE          (0x01C69000)
+#define DM365_KEYSCAN_BASE      (0x01C69400)
+#define DM365_UHPI_BASE         (0x01C69800)
+#define DM365_IMCOP_BASE        (0x01CA0000)
+#define DM365_MMC_SD1_BASE      (0x01D00000)
+#define DM365_MCBSP_BASE        (0x01D02000)
+#define DM365_UART1_BASE        (0x01D06000)
+#define DM365_EMAC_CNTRL_BASE       (0x01D07000)
+#define DM365_EMAC_WRAP_RAM_BASE    (0x01D08000)
+#define DM365_EMAC_WRAP_CNTRL_BASE  (0x01D0A000)
+#define DM365_EMAC_MDIO_BASE        (0x01D0B000)
+#define DM365_VOICE_CODEC_BASE      (0x01D0C000)
+#define DM365_ASYNC_EMIF_CNTRL_BASE (0x01D10000)
+#define DM365_MMC_SD0_BASE      (0x01D11000)
+#define DM365_MS_BASE           (0x01D20000)
+#define DM365_KALEIDO_BASE      (0x01E00000)
 
-#define DAVINCI_UART0_BASE		(0x01C20000)
+#define DAVINCI_UART0_BASE      (0x01C20000)
 
-#define PSC_MDCTL_BASE			(0x01c41a00)
-#define PSC_MDSTAT_BASE			(0x01c41800)
-#define PSC_PTCMD			(0x01c41120)
-#define PSC_PTSTAT			(0x01c41128)
+#define PSC_MDCTL_BASE          (0x01c41a00)
+#define PSC_MDSTAT_BASE         (0x01c41800)
+#define PSC_PTCMD           (0x01c41120)
+#define PSC_PTSTAT          (0x01c41128)
 
-#define DM365_EINT_ENABLE0		0x01c48018
-#define DM365_EINT_ENABLE1		0x01c4801c
+#define DM365_EINT_ENABLE0      0x01c48018
+#define DM365_EINT_ENABLE1      0x01c4801c
 
-#define davinci_readb(a)	(*(volatile unsigned char  *)(a))
-#define davinci_readw(a)	(*(volatile unsigned short *)(a))
-#define davinci_readl(a)	(*(volatile unsigned int   *)(a))
+#define davinci_readb(a)    (*(volatile unsigned char  *)(a))
+#define davinci_readw(a)    (*(volatile unsigned short *)(a))
+#define davinci_readl(a)    (*(volatile unsigned int   *)(a))
 
-#define davinci_writeb(v,a)	(*(volatile unsigned char  *)(a) = (v))
-#define davinci_writew(v,a)	(*(volatile unsigned short *)(a) = (v))
-#define davinci_writel(v,a)	(*(volatile unsigned int   *)(a) = (v))
+#define davinci_writeb(v,a) (*(volatile unsigned char  *)(a) = (v))
+#define davinci_writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define davinci_writel(v,a) (*(volatile unsigned int   *)(a) = (v))
 
-#define readb(a)	davinci_readb(a)
-#define readw(a)	davinci_readw(a)
-#define readl(a)	davinci_readl(a)
+#define readb(a)    davinci_readb(a)
+#define readw(a)    davinci_readw(a)
+#define readl(a)    davinci_readl(a)
 
-#define write(v,a)	davinci_writeb(v,a)
-#define writew(v,a)	davinci_writew(v,a)
-#define writel(v,a)	davinci_writel(v,a)
+#define write(v,a)  davinci_writeb(v,a)
+#define writew(v,a) davinci_writew(v,a)
+#define writel(v,a) davinci_writel(v,a)
 
 /* define timer register struct*/
 typedef struct timer_regs_s {
-	rt_uint32_t pid12;            /* 0x0 */
-	rt_uint32_t emumgt_clksped;   /* 0x4 */
-	rt_uint32_t gpint_en;         /* 0x8 */
-	rt_uint32_t gpdir_dat;        /* 0xC */
-	rt_uint32_t tim12;            /* 0x10 */
-	rt_uint32_t tim34;            /* 0x14 */
-	rt_uint32_t prd12;            /* 0x18 */
-	rt_uint32_t prd34;            /* 0x1C */
-	rt_uint32_t tcr;              /* 0x20 */
-	rt_uint32_t tgcr;             /* 0x24 */
-	rt_uint32_t wdtcr;            /* 0x28 */
-	rt_uint32_t tlgc;             /* 0x2C */
-	rt_uint32_t tlmr;             /* 0x30 */
+    rt_uint32_t pid12;            /* 0x0 */
+    rt_uint32_t emumgt_clksped;   /* 0x4 */
+    rt_uint32_t gpint_en;         /* 0x8 */
+    rt_uint32_t gpdir_dat;        /* 0xC */
+    rt_uint32_t tim12;            /* 0x10 */
+    rt_uint32_t tim34;            /* 0x14 */
+    rt_uint32_t prd12;            /* 0x18 */
+    rt_uint32_t prd34;            /* 0x1C */
+    rt_uint32_t tcr;              /* 0x20 */
+    rt_uint32_t tgcr;             /* 0x24 */
+    rt_uint32_t wdtcr;            /* 0x28 */
+    rt_uint32_t tlgc;             /* 0x2C */
+    rt_uint32_t tlmr;             /* 0x30 */
 } timer_regs_t;
 
 /*****************************/
 /* CPU Mode                  */
 /*****************************/
-#define USERMODE		0x10
-#define FIQMODE			0x11
-#define IRQMODE			0x12
-#define SVCMODE			0x13
-#define ABORTMODE		0x17
-#define UNDEFMODE		0x1b
-#define MODEMASK		0x1f
-#define NOINT			0xc0
+#define USERMODE        0x10
+#define FIQMODE         0x11
+#define IRQMODE         0x12
+#define SVCMODE         0x13
+#define ABORTMODE       0x17
+#define UNDEFMODE       0x1b
+#define MODEMASK        0x1f
+#define NOINT           0xc0
 
 struct rt_hw_register
 {
diff --git a/bsp/dm365/platform/dma.c b/bsp/dm365/platform/dma.c
index 4316d9739e..baaedf650a 100644
--- a/bsp/dm365/platform/dma.c
+++ b/bsp/dm365/platform/dma.c
@@ -4,96 +4,96 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 
 #include <edma.h>
 
 /* Offsets matching "struct edmacc_param" */
-#define PARM_OPT		0x00
-#define PARM_SRC		0x04
-#define PARM_A_B_CNT		0x08
-#define PARM_DST		0x0c
-#define PARM_SRC_DST_BIDX	0x10
-#define PARM_LINK_BCNTRLD	0x14
-#define PARM_SRC_DST_CIDX	0x18
-#define PARM_CCNT		0x1c
+#define PARM_OPT        0x00
+#define PARM_SRC        0x04
+#define PARM_A_B_CNT        0x08
+#define PARM_DST        0x0c
+#define PARM_SRC_DST_BIDX   0x10
+#define PARM_LINK_BCNTRLD   0x14
+#define PARM_SRC_DST_CIDX   0x18
+#define PARM_CCNT       0x1c
 
-#define PARM_SIZE		0x20
+#define PARM_SIZE       0x20
 
 /* Offsets for EDMA CC global channel registers and their shadows */
-#define SH_ER		0x00	/* 64 bits */
-#define SH_ECR		0x08	/* 64 bits */
-#define SH_ESR		0x10	/* 64 bits */
-#define SH_CER		0x18	/* 64 bits */
-#define SH_EER		0x20	/* 64 bits */
-#define SH_EECR		0x28	/* 64 bits */
-#define SH_EESR		0x30	/* 64 bits */
-#define SH_SER		0x38	/* 64 bits */
-#define SH_SECR		0x40	/* 64 bits */
-#define SH_IER		0x50	/* 64 bits */
-#define SH_IECR		0x58	/* 64 bits */
-#define SH_IESR		0x60	/* 64 bits */
-#define SH_IPR		0x68	/* 64 bits */
-#define SH_ICR		0x70	/* 64 bits */
-#define SH_IEVAL	0x78
-#define SH_QER		0x80
-#define SH_QEER		0x84
-#define SH_QEECR	0x88
-#define SH_QEESR	0x8c
-#define SH_QSER		0x90
-#define SH_QSECR	0x94
-#define SH_SIZE		0x200
+#define SH_ER       0x00    /* 64 bits */
+#define SH_ECR      0x08    /* 64 bits */
+#define SH_ESR      0x10    /* 64 bits */
+#define SH_CER      0x18    /* 64 bits */
+#define SH_EER      0x20    /* 64 bits */
+#define SH_EECR     0x28    /* 64 bits */
+#define SH_EESR     0x30    /* 64 bits */
+#define SH_SER      0x38    /* 64 bits */
+#define SH_SECR     0x40    /* 64 bits */
+#define SH_IER      0x50    /* 64 bits */
+#define SH_IECR     0x58    /* 64 bits */
+#define SH_IESR     0x60    /* 64 bits */
+#define SH_IPR      0x68    /* 64 bits */
+#define SH_ICR      0x70    /* 64 bits */
+#define SH_IEVAL    0x78
+#define SH_QER      0x80
+#define SH_QEER     0x84
+#define SH_QEECR    0x88
+#define SH_QEESR    0x8c
+#define SH_QSER     0x90
+#define SH_QSECR    0x94
+#define SH_SIZE     0x200
 
 /* Offsets for EDMA CC global registers */
-#define EDMA_REV	0x0000
-#define EDMA_CCCFG	0x0004
-#define EDMA_QCHMAP	0x0200	/* 8 registers */
-#define EDMA_DMAQNUM	0x0240	/* 8 registers (4 on OMAP-L1xx) */
-#define EDMA_QDMAQNUM	0x0260
-#define EDMA_QUETCMAP	0x0280
-#define EDMA_QUEPRI	0x0284
-#define EDMA_EMR	0x0300	/* 64 bits */
-#define EDMA_EMCR	0x0308	/* 64 bits */
-#define EDMA_QEMR	0x0310
-#define EDMA_QEMCR	0x0314
-#define EDMA_CCERR	0x0318
-#define EDMA_CCERRCLR	0x031c
-#define EDMA_EEVAL	0x0320
-#define EDMA_DRAE	0x0340	/* 4 x 64 bits*/
-#define EDMA_QRAE	0x0380	/* 4 registers */
-#define EDMA_QUEEVTENTRY	0x0400	/* 2 x 16 registers */
-#define EDMA_QSTAT	0x0600	/* 2 registers */
-#define EDMA_QWMTHRA	0x0620
-#define EDMA_QWMTHRB	0x0624
-#define EDMA_CCSTAT	0x0640
+#define EDMA_REV    0x0000
+#define EDMA_CCCFG  0x0004
+#define EDMA_QCHMAP 0x0200  /* 8 registers */
+#define EDMA_DMAQNUM    0x0240  /* 8 registers (4 on OMAP-L1xx) */
+#define EDMA_QDMAQNUM   0x0260
+#define EDMA_QUETCMAP   0x0280
+#define EDMA_QUEPRI 0x0284
+#define EDMA_EMR    0x0300  /* 64 bits */
+#define EDMA_EMCR   0x0308  /* 64 bits */
+#define EDMA_QEMR   0x0310
+#define EDMA_QEMCR  0x0314
+#define EDMA_CCERR  0x0318
+#define EDMA_CCERRCLR   0x031c
+#define EDMA_EEVAL  0x0320
+#define EDMA_DRAE   0x0340  /* 4 x 64 bits*/
+#define EDMA_QRAE   0x0380  /* 4 registers */
+#define EDMA_QUEEVTENTRY    0x0400  /* 2 x 16 registers */
+#define EDMA_QSTAT  0x0600  /* 2 registers */
+#define EDMA_QWMTHRA    0x0620
+#define EDMA_QWMTHRB    0x0624
+#define EDMA_CCSTAT 0x0640
 
-#define EDMA_M		0x1000	/* global channel registers */
-#define EDMA_ECR	0x1008
-#define EDMA_ECRH	0x100C
-#define EDMA_SHADOW0	0x2000	/* 4 regions shadowing global channels */
-#define EDMA_PARM	0x4000	/* 128 param entries */
+#define EDMA_M      0x1000  /* global channel registers */
+#define EDMA_ECR    0x1008
+#define EDMA_ECRH   0x100C
+#define EDMA_SHADOW0    0x2000  /* 4 regions shadowing global channels */
+#define EDMA_PARM   0x4000  /* 128 param entries */
 
-#define PARM_OFFSET(param_no)	(EDMA_PARM + ((param_no) << 5))
+#define PARM_OFFSET(param_no)   (EDMA_PARM + ((param_no) << 5))
 
-#define EDMA_DCHMAP	0x0100  /* 64 registers */
-#define CHMAP_EXIST	BIT(24)
+#define EDMA_DCHMAP 0x0100  /* 64 registers */
+#define CHMAP_EXIST BIT(24)
 
 #define EDMA_MAX_DMACH           64
 #define EDMA_MAX_PARAMENTRY     512
 
-#define EDMA_CC0_BASE_REG	0x01c00000
-#define EDMA_TC0_BASE_REG	0x01c10000
-#define EDMA_TC1_BASE_REG	0x01c10400
-#define EDMA_TC2_BASE_REG	0x01c10800
-#define EDMA_TC3_BASE_REG	0x01c10c00
+#define EDMA_CC0_BASE_REG   0x01c00000
+#define EDMA_TC0_BASE_REG   0x01c10000
+#define EDMA_TC1_BASE_REG   0x01c10400
+#define EDMA_TC2_BASE_REG   0x01c10800
+#define EDMA_TC3_BASE_REG   0x01c10c00
 
-#define min_t(type, x, y) ({			\
-	type __min1 = (x);			\
-	type __min2 = (y);			\
-	__min1 < __min2 ? __min1: __min2; })
+#define min_t(type, x, y) ({            \
+    type __min1 = (x);          \
+    type __min2 = (y);          \
+    __min1 < __min2 ? __min1: __min2; })
 
 
 
@@ -103,130 +103,130 @@ static void volatile *edmacc_regs_base[EDMA_MAX_CC];
 
 static inline unsigned int edma_read(unsigned ctlr, int offset)
 {
-	return (unsigned int)davinci_readl(edmacc_regs_base[ctlr] + offset);
+    return (unsigned int)davinci_readl(edmacc_regs_base[ctlr] + offset);
 }
 
 static inline void edma_write(unsigned ctlr, int offset, int val)
 {
-	davinci_writel(val, edmacc_regs_base[ctlr] + offset);
+    davinci_writel(val, edmacc_regs_base[ctlr] + offset);
 }
 static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
-		unsigned or)
+        unsigned or)
 {
-	unsigned val = edma_read(ctlr, offset);
-	val &= and;
-	val |= or;
-	edma_write(ctlr, offset, val);
+    unsigned val = edma_read(ctlr, offset);
+    val &= and;
+    val |= or;
+    edma_write(ctlr, offset, val);
 }
 static inline void edma_and(unsigned ctlr, int offset, unsigned and)
 {
-	unsigned val = edma_read(ctlr, offset);
-	val &= and;
-	edma_write(ctlr, offset, val);
+    unsigned val = edma_read(ctlr, offset);
+    val &= and;
+    edma_write(ctlr, offset, val);
 }
 static inline void edma_or(unsigned ctlr, int offset, unsigned or)
 {
-	unsigned val = edma_read(ctlr, offset);
-	val |= or;
-	edma_write(ctlr, offset, val);
+    unsigned val = edma_read(ctlr, offset);
+    val |= or;
+    edma_write(ctlr, offset, val);
 }
 static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
 {
-	return edma_read(ctlr, offset + (i << 2));
+    return edma_read(ctlr, offset + (i << 2));
 }
 static inline void edma_write_array(unsigned ctlr, int offset, int i,
-		unsigned val)
+        unsigned val)
 {
-	edma_write(ctlr, offset + (i << 2), val);
+    edma_write(ctlr, offset + (i << 2), val);
 }
 static inline void edma_modify_array(unsigned ctlr, int offset, int i,
-		unsigned and, unsigned or)
+        unsigned and, unsigned or)
 {
-	edma_modify(ctlr, offset + (i << 2), and, or);
+    edma_modify(ctlr, offset + (i << 2), and, or);
 }
 static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
 {
-	edma_or(ctlr, offset + (i << 2), or);
+    edma_or(ctlr, offset + (i << 2), or);
 }
 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
-		unsigned or)
+        unsigned or)
 {
-	edma_or(ctlr, offset + ((i*2 + j) << 2), or);
+    edma_or(ctlr, offset + ((i*2 + j) << 2), or);
 }
 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
-		unsigned val)
+        unsigned val)
 {
-	edma_write(ctlr, offset + ((i*2 + j) << 2), val);
+    edma_write(ctlr, offset + ((i*2 + j) << 2), val);
 }
 static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
 {
-	return edma_read(ctlr, EDMA_SHADOW0 + offset);
+    return edma_read(ctlr, EDMA_SHADOW0 + offset);
 }
 static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
-		int i)
+        int i)
 {
-	return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
+    return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
 }
 static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
 {
-	edma_write(ctlr, EDMA_SHADOW0 + offset, val);
+    edma_write(ctlr, EDMA_SHADOW0 + offset, val);
 }
 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
-		unsigned val)
+        unsigned val)
 {
-	edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
+    edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
 }
 static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
-		int param_no)
+        int param_no)
 {
-	return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
+    return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
 }
 static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
-		unsigned val)
+        unsigned val)
 {
-	edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
+    edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
 }
 static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
-		unsigned and, unsigned or)
+        unsigned and, unsigned or)
 {
-	edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
+    edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
 }
 static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
-		unsigned and)
+        unsigned and)
 {
-	edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
+    edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
 }
 static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
-		unsigned or)
+        unsigned or)
 {
-	edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
+    edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
 }
 #if 0
 static inline void set_bits(int offset, int len, unsigned long *p)
 {
-	for (; len > 0; len--)
-		set_bit(offset + (len - 1), p);
+    for (; len > 0; len--)
+        set_bit(offset + (len - 1), p);
 }
 
 static inline void clear_bits(int offset, int len, unsigned long *p)
 {
-	for (; len > 0; len--)
-		clear_bit(offset + (len - 1), p);
+    for (; len > 0; len--)
+        clear_bit(offset + (len - 1), p);
 }
 #endif
 /*****************************************************************************/
 
-#define BIT(nr)			(1UL << (nr))
+#define BIT(nr)         (1UL << (nr))
 #define BITS_PER_LONG 32
-#define BIT_MASK(nr)		(1UL << ((nr) % BITS_PER_LONG))
-#define BIT_WORD(nr)		((nr) / BITS_PER_LONG)
-#define BITS_PER_BYTE		8
+#define BIT_MASK(nr)        (1UL << ((nr) % BITS_PER_LONG))
+#define BIT_WORD(nr)        ((nr) / BITS_PER_LONG)
+#define BITS_PER_BYTE       8
 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
 
-#define BITS_TO_LONGS(nr)	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+#define BITS_TO_LONGS(nr)   DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
 
 #define DECLARE_BITMAP(name,bits) \
-	unsigned long name[BITS_TO_LONGS(bits)]
+    unsigned long name[BITS_TO_LONGS(bits)]
 
 /**
  * test_bit - Determine whether a bit is set
@@ -235,44 +235,44 @@ static inline void clear_bits(int offset, int len, unsigned long *p)
  */
 static inline int test_bit(int nr, const volatile unsigned long *addr)
 {
-	return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
+    return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
 }
 
 static inline void clear_bit(int nr, volatile unsigned long *addr)
 {
-	unsigned long mask = BIT_MASK(nr);
-	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
-	rt_base_t level;
+    unsigned long mask = BIT_MASK(nr);
+    unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+    rt_base_t level;
 
-	level = rt_hw_interrupt_disable();
-	*p &= ~mask;
-	rt_hw_interrupt_enable(level);
+    level = rt_hw_interrupt_disable();
+    *p &= ~mask;
+    rt_hw_interrupt_enable(level);
 }
 
 static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
 {
-	unsigned long mask = BIT_MASK(nr);
-	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
-	unsigned long old;
-	rt_base_t level;
+    unsigned long mask = BIT_MASK(nr);
+    unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+    unsigned long old;
+    rt_base_t level;
 
-	level = rt_hw_interrupt_disable();
-	old = *p;
-	*p = old | mask;
-	rt_hw_interrupt_enable(level);
+    level = rt_hw_interrupt_disable();
+    old = *p;
+    *p = old | mask;
+    rt_hw_interrupt_enable(level);
 
-	return (old & mask) != 0;
+    return (old & mask) != 0;
 }
 
 static inline void set_bit(int nr, volatile unsigned long *addr)
 {
-	unsigned long mask = BIT_MASK(nr);
-	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
-	rt_base_t level;
+    unsigned long mask = BIT_MASK(nr);
+    unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+    rt_base_t level;
 
-	level = rt_hw_interrupt_disable();
-	*p  |= mask;
-	rt_hw_interrupt_enable(level);
+    level = rt_hw_interrupt_disable();
+    *p  |= mask;
+    rt_hw_interrupt_enable(level);
 }
 
 /*
@@ -286,45 +286,45 @@ extern int _find_next_bit_le(const unsigned long *p, int size, int offset);
 /*
  * These are the little endian, atomic definitions.
  */
-#define find_first_zero_bit(p,sz)	_find_first_zero_bit_le(p,sz)
-#define find_next_zero_bit(p,sz,off)	_find_next_zero_bit_le(p,sz,off)
-#define find_first_bit(p,sz)		_find_first_bit_le(p,sz)
-#define find_next_bit(p,sz,off)		_find_next_bit_le(p,sz,off)
+#define find_first_zero_bit(p,sz)   _find_first_zero_bit_le(p,sz)
+#define find_next_zero_bit(p,sz,off)    _find_next_zero_bit_le(p,sz,off)
+#define find_first_bit(p,sz)        _find_first_bit_le(p,sz)
+#define find_next_bit(p,sz,off)     _find_next_bit_le(p,sz,off)
 
 
 
 /* actual number of DMA channels and slots on this silicon */
 struct edma {
-	/* how many dma resources of each type */
-	unsigned	num_channels;
-	unsigned	num_region;
-	unsigned	num_slots;
-	unsigned	num_tc;
-	unsigned	num_cc;
-	enum dma_event_q 	default_queue;
+    /* how many dma resources of each type */
+    unsigned    num_channels;
+    unsigned    num_region;
+    unsigned    num_slots;
+    unsigned    num_tc;
+    unsigned    num_cc;
+    enum dma_event_q    default_queue;
 
-	/* list of channels with no even trigger; terminated by "-1" */
-	const rt_int8_t	*noevent;
+    /* list of channels with no even trigger; terminated by "-1" */
+    const rt_int8_t *noevent;
 
-	/* The edma_inuse bit for each PaRAM slot is clear unless the
-	 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
-	 */
-	DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
+    /* The edma_inuse bit for each PaRAM slot is clear unless the
+     * channel is in use ... by ARM or DSP, for QDMA, or whatever.
+     */
+    DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
 
-	/* The edma_unused bit for each channel is clear unless
-	 * it is not being used on this platform. It uses a bit
-	 * of SOC-specific initialization code.
-	 */
-	DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
+    /* The edma_unused bit for each channel is clear unless
+     * it is not being used on this platform. It uses a bit
+     * of SOC-specific initialization code.
+     */
+    DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
 
-	unsigned	irq_res_start;
-	unsigned	irq_res_end;
+    unsigned    irq_res_start;
+    unsigned    irq_res_end;
 
-	struct dma_interrupt_data {
-		void (*callback)(unsigned channel, unsigned short ch_status,
-				void *data);
-		void *data;
-	} intr_data[EDMA_MAX_DMACH];
+    struct dma_interrupt_data {
+        void (*callback)(unsigned channel, unsigned short ch_status,
+                void *data);
+        void *data;
+    } intr_data[EDMA_MAX_DMACH];
 };
 
 static struct edma *edma_cc[EDMA_MAX_CC];
@@ -332,38 +332,38 @@ static int arch_num_cc;
 
 /* dummy param set used to (re)initialize parameter RAM slots */
 static const struct edmacc_param dummy_paramset = {
-	.link_bcntrld = 0xffff,
-	.ccnt = 1,
+    .link_bcntrld = 0xffff,
+    .ccnt = 1,
 };
 
 /*****************************************************************************/
 
 static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
-		enum dma_event_q queue_no)
+        enum dma_event_q queue_no)
 {
-	int bit = (ch_no & 0x7) * 4;
+    int bit = (ch_no & 0x7) * 4;
 
-	/* default to low priority queue */
-	if (queue_no == EVENTQ_DEFAULT)
-		queue_no = edma_cc[ctlr]->default_queue;
+    /* default to low priority queue */
+    if (queue_no == EVENTQ_DEFAULT)
+        queue_no = edma_cc[ctlr]->default_queue;
 
-	queue_no &= 7;
-	edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
-			~(0x7 << bit), queue_no << bit);
+    queue_no &= 7;
+    edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
+            ~(0x7 << bit), queue_no << bit);
 }
 
 static void map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
 {
-	int bit = queue_no * 4;
-	edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
+    int bit = queue_no * 4;
+    edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
 }
 
 static void assign_priority_to_queue(unsigned ctlr, int queue_no,
-		int priority)
+        int priority)
 {
-	int bit = queue_no * 4;
-	edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
-			((priority & 0x7) << bit));
+    int bit = queue_no * 4;
+    edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
+            ((priority & 0x7) << bit));
 }
 
 /**
@@ -379,45 +379,45 @@ static void assign_priority_to_queue(unsigned ctlr, int queue_no,
  */
 static void map_dmach_param(unsigned ctlr)
 {
-	int i;
-	for (i = 0; i < EDMA_MAX_DMACH; i++)
-		edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
+    int i;
+    for (i = 0; i < EDMA_MAX_DMACH; i++)
+        edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
 }
 
 static inline void
 setup_dma_interrupt(unsigned lch,
-	void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data),
-	void *data)
+    void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data),
+    void *data)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(lch);
-	lch = EDMA_CHAN_SLOT(lch);
+    ctlr = EDMA_CTLR(lch);
+    lch = EDMA_CHAN_SLOT(lch);
 
-	if (!callback)
-		edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
-				BIT(lch & 0x1f));
+    if (!callback)
+        edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
+                BIT(lch & 0x1f));
 
-	edma_cc[ctlr]->intr_data[lch].callback = callback;
-	edma_cc[ctlr]->intr_data[lch].data = data;
+    edma_cc[ctlr]->intr_data[lch].callback = callback;
+    edma_cc[ctlr]->intr_data[lch].data = data;
 
-	if (callback) {
-		edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
-				BIT(lch & 0x1f));
-		edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
-				BIT(lch & 0x1f));
-	}
+    if (callback) {
+        edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
+                BIT(lch & 0x1f));
+        edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
+                BIT(lch & 0x1f));
+    }
 }
 
 static int irq2ctlr(int irq)
 {
-	if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
-		return 0;
-	else if (irq >= edma_cc[1]->irq_res_start &&
-		irq <= edma_cc[1]->irq_res_end)
-		return 1;
+    if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
+        return 0;
+    else if (irq >= edma_cc[1]->irq_res_start &&
+        irq <= edma_cc[1]->irq_res_end)
+        return 1;
 
-	return -1;
+    return -1;
 }
 
 /******************************************************************************
@@ -427,53 +427,53 @@ static int irq2ctlr(int irq)
  *****************************************************************************/
 static void dma_irq_handler(int irq, void *data)
 {
-	int i;
-	int ctlr;
-	unsigned int cnt = 0;
+    int i;
+    int ctlr;
+    unsigned int cnt = 0;
 
-	ctlr = irq2ctlr(irq);
-	if (ctlr < 0)
-		return ;
+    ctlr = irq2ctlr(irq);
+    if (ctlr < 0)
+        return ;
 
-	edma_dbg("dma_irq_handler\n");
+    edma_dbg("dma_irq_handler\n");
 
-	if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) &&
-	    (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
-		return ;
+    if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) &&
+        (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
+        return ;
 
-	while (1) {
-		int j;
-		if (edma_shadow0_read_array(ctlr, SH_IPR, 0) &
-				edma_shadow0_read_array(ctlr, SH_IER, 0))
-			j = 0;
-		else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) &
-				edma_shadow0_read_array(ctlr, SH_IER, 1))
-			j = 1;
-		else
-			break;
-		edma_dbg("IPR%d %08x\n", j,
-				edma_shadow0_read_array(ctlr, SH_IPR, j));
-		for (i = 0; i < 32; i++) {
-			int k = (j << 5) + i;
-			if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i))
-					&& (edma_shadow0_read_array(ctlr,
-							SH_IER, j) & BIT(i))) {
-				/* Clear the corresponding IPR bits */
-				edma_shadow0_write_array(ctlr, SH_ICR, j,
-							BIT(i));
-				if (edma_cc[ctlr]->intr_data[k].callback)
-					edma_cc[ctlr]->intr_data[k].callback(
-						k, DMA_COMPLETE,
-						edma_cc[ctlr]->intr_data[k].
-						data);
-			}
-		}
-		cnt++;
-		if (cnt > 10)
-			break;
-	}
-	edma_shadow0_write(ctlr, SH_IEVAL, 1);
-	return ;
+    while (1) {
+        int j;
+        if (edma_shadow0_read_array(ctlr, SH_IPR, 0) &
+                edma_shadow0_read_array(ctlr, SH_IER, 0))
+            j = 0;
+        else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) &
+                edma_shadow0_read_array(ctlr, SH_IER, 1))
+            j = 1;
+        else
+            break;
+        edma_dbg("IPR%d %08x\n", j,
+                edma_shadow0_read_array(ctlr, SH_IPR, j));
+        for (i = 0; i < 32; i++) {
+            int k = (j << 5) + i;
+            if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i))
+                    && (edma_shadow0_read_array(ctlr,
+                            SH_IER, j) & BIT(i))) {
+                /* Clear the corresponding IPR bits */
+                edma_shadow0_write_array(ctlr, SH_ICR, j,
+                            BIT(i));
+                if (edma_cc[ctlr]->intr_data[k].callback)
+                    edma_cc[ctlr]->intr_data[k].callback(
+                        k, DMA_COMPLETE,
+                        edma_cc[ctlr]->intr_data[k].
+                        data);
+            }
+        }
+        cnt++;
+        if (cnt > 10)
+            break;
+    }
+    edma_shadow0_write(ctlr, SH_IEVAL, 1);
+    return ;
 }
 
 /******************************************************************************
@@ -483,90 +483,90 @@ static void dma_irq_handler(int irq, void *data)
  *****************************************************************************/
 static void dma_ccerr_handler(int irq, void *data)
 {
-	int i;
-	int ctlr;
-	unsigned int cnt = 0;
+    int i;
+    int ctlr;
+    unsigned int cnt = 0;
 
-	ctlr = irq2ctlr(irq);
-	if (ctlr < 0)
-		return ;
+    ctlr = irq2ctlr(irq);
+    if (ctlr < 0)
+        return ;
 
-	edma_dbg("dma_ccerr_handler\n");
+    edma_dbg("dma_ccerr_handler\n");
 
-	if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
-	    (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
-	    (edma_read(ctlr, EDMA_QEMR) == 0) &&
-	    (edma_read(ctlr, EDMA_CCERR) == 0))
-		return ;
+    if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
+        (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
+        (edma_read(ctlr, EDMA_QEMR) == 0) &&
+        (edma_read(ctlr, EDMA_CCERR) == 0))
+        return ;
 
-	while (1) {
-		int j = -1;
-		if (edma_read_array(ctlr, EDMA_EMR, 0))
-			j = 0;
-		else if (edma_read_array(ctlr, EDMA_EMR, 1))
-			j = 1;
-		if (j >= 0) {
-			edma_dbg("EMR%d %08x\n", j,
-					edma_read_array(ctlr, EDMA_EMR, j));
-			for (i = 0; i < 32; i++) {
-				int k = (j << 5) + i;
-				if (edma_read_array(ctlr, EDMA_EMR, j) &
-							BIT(i)) {
-					/* Clear the corresponding EMR bits */
-					edma_write_array(ctlr, EDMA_EMCR, j,
-							BIT(i));
-					/* Clear any SER */
-					edma_shadow0_write_array(ctlr, SH_SECR,
-								j, BIT(i));
-					if (edma_cc[ctlr]->intr_data[k].
-								callback) {
-						edma_cc[ctlr]->intr_data[k].
-						callback(k,
-						DMA_CC_ERROR,
-						edma_cc[ctlr]->intr_data
-						[k].data);
-					}
-				}
-			}
-		} else if (edma_read(ctlr, EDMA_QEMR)) {
-			edma_dbg("QEMR %02x\n",
-				edma_read(ctlr, EDMA_QEMR));
-			for (i = 0; i < 8; i++) {
-				if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
-					/* Clear the corresponding IPR bits */
-					edma_write(ctlr, EDMA_QEMCR, BIT(i));
-					edma_shadow0_write(ctlr, SH_QSECR,
-								BIT(i));
+    while (1) {
+        int j = -1;
+        if (edma_read_array(ctlr, EDMA_EMR, 0))
+            j = 0;
+        else if (edma_read_array(ctlr, EDMA_EMR, 1))
+            j = 1;
+        if (j >= 0) {
+            edma_dbg("EMR%d %08x\n", j,
+                    edma_read_array(ctlr, EDMA_EMR, j));
+            for (i = 0; i < 32; i++) {
+                int k = (j << 5) + i;
+                if (edma_read_array(ctlr, EDMA_EMR, j) &
+                            BIT(i)) {
+                    /* Clear the corresponding EMR bits */
+                    edma_write_array(ctlr, EDMA_EMCR, j,
+                            BIT(i));
+                    /* Clear any SER */
+                    edma_shadow0_write_array(ctlr, SH_SECR,
+                                j, BIT(i));
+                    if (edma_cc[ctlr]->intr_data[k].
+                                callback) {
+                        edma_cc[ctlr]->intr_data[k].
+                        callback(k,
+                        DMA_CC_ERROR,
+                        edma_cc[ctlr]->intr_data
+                        [k].data);
+                    }
+                }
+            }
+        } else if (edma_read(ctlr, EDMA_QEMR)) {
+            edma_dbg("QEMR %02x\n",
+                edma_read(ctlr, EDMA_QEMR));
+            for (i = 0; i < 8; i++) {
+                if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
+                    /* Clear the corresponding IPR bits */
+                    edma_write(ctlr, EDMA_QEMCR, BIT(i));
+                    edma_shadow0_write(ctlr, SH_QSECR,
+                                BIT(i));
 
-					/* NOTE:  not reported!! */
-				}
-			}
-		} else if (edma_read(ctlr, EDMA_CCERR)) {
-			edma_dbg("CCERR %08x\n",
-				edma_read(ctlr, EDMA_CCERR));
-			/* FIXME:  CCERR.BIT(16) ignored!  much better
-			 * to just write CCERRCLR with CCERR value...
-			 */
-			for (i = 0; i < 8; i++) {
-				if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
-					/* Clear the corresponding IPR bits */
-					edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
+                    /* NOTE:  not reported!! */
+                }
+            }
+        } else if (edma_read(ctlr, EDMA_CCERR)) {
+            edma_dbg("CCERR %08x\n",
+                edma_read(ctlr, EDMA_CCERR));
+            /* FIXME:  CCERR.BIT(16) ignored!  much better
+             * to just write CCERRCLR with CCERR value...
+             */
+            for (i = 0; i < 8; i++) {
+                if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
+                    /* Clear the corresponding IPR bits */
+                    edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
 
-					/* NOTE:  not reported!! */
-				}
-			}
-		}
-		if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
-		    (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
-		    (edma_read(ctlr, EDMA_QEMR) == 0) &&
-		    (edma_read(ctlr, EDMA_CCERR) == 0))
-			break;
-		cnt++;
-		if (cnt > 10)
-			break;
-	}
-	edma_write(ctlr, EDMA_EEVAL, 1);
-	return ;
+                    /* NOTE:  not reported!! */
+                }
+            }
+        }
+        if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
+            (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
+            (edma_read(ctlr, EDMA_QEMR) == 0) &&
+            (edma_read(ctlr, EDMA_CCERR) == 0))
+            break;
+        cnt++;
+        if (cnt > 10)
+            break;
+    }
+    edma_write(ctlr, EDMA_EEVAL, 1);
+    return ;
 }
 
 /******************************************************************************
@@ -575,92 +575,92 @@ static void dma_ccerr_handler(int irq, void *data)
  *
  *****************************************************************************/
 
-#define tc_errs_handled	RT_FALSE/* disabled as long as they're NOPs */
+#define tc_errs_handled RT_FALSE/* disabled as long as they're NOPs */
 
 static void dma_tc0err_handler(int irq, void *data)
 {
-	edma_dbg("dma_tc0err_handler\n");
-	return ;
+    edma_dbg("dma_tc0err_handler\n");
+    return ;
 }
 
 static void dma_tc1err_handler(int irq, void *data)
 {
-	edma_dbg("dma_tc1err_handler\n");
-	return ;
+    edma_dbg("dma_tc1err_handler\n");
+    return ;
 }
 
 static int reserve_contiguous_slots(int ctlr, unsigned int id,
-				     unsigned int num_slots,
-				     unsigned int start_slot)
+                     unsigned int num_slots,
+                     unsigned int start_slot)
 {
-	int i, j;
-	unsigned int count = num_slots;
-	int stop_slot = start_slot;
-	DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
+    int i, j;
+    unsigned int count = num_slots;
+    int stop_slot = start_slot;
+    DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
 
-	for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
-		j = EDMA_CHAN_SLOT(i);
-		if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
-			/* Record our current beginning slot */
-			if (count == num_slots)
-				stop_slot = i;
+    for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
+        j = EDMA_CHAN_SLOT(i);
+        if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
+            /* Record our current beginning slot */
+            if (count == num_slots)
+                stop_slot = i;
 
-			count--;
-			set_bit(j, tmp_inuse);
+            count--;
+            set_bit(j, tmp_inuse);
 
-			if (count == 0)
-				break;
-		} else {
-			clear_bit(j, tmp_inuse);
+            if (count == 0)
+                break;
+        } else {
+            clear_bit(j, tmp_inuse);
 
-			if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
-				stop_slot = i;
-				break;
-			} else {
-				count = num_slots;
-			}
-		}
-	}
+            if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
+                stop_slot = i;
+                break;
+            } else {
+                count = num_slots;
+            }
+        }
+    }
 
-	/*
-	 * We have to clear any bits that we set
-	 * if we run out parameter RAM slots, i.e we do find a set
-	 * of contiguous parameter RAM slots but do not find the exact number
-	 * requested as we may reach the total number of parameter RAM slots
-	 */
-	if (i == edma_cc[ctlr]->num_slots)
-		stop_slot = i;
+    /*
+     * We have to clear any bits that we set
+     * if we run out parameter RAM slots, i.e we do find a set
+     * of contiguous parameter RAM slots but do not find the exact number
+     * requested as we may reach the total number of parameter RAM slots
+     */
+    if (i == edma_cc[ctlr]->num_slots)
+        stop_slot = i;
 
-	for (j = start_slot; j < stop_slot; j++)
-		if (test_bit(j, tmp_inuse))
-			clear_bit(j, edma_cc[ctlr]->edma_inuse);
+    for (j = start_slot; j < stop_slot; j++)
+        if (test_bit(j, tmp_inuse))
+            clear_bit(j, edma_cc[ctlr]->edma_inuse);
 
-	if (count)
-		return -RT_EBUSY;
+    if (count)
+        return -RT_EBUSY;
 
-	for (j = i - num_slots + 1; j <= i; ++j)
-		rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(j)),
-			&dummy_paramset, PARM_SIZE);
+    for (j = i - num_slots + 1; j <= i; ++j)
+        rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(j)),
+            &dummy_paramset, PARM_SIZE);
 
-	return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
+    return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
 }
 
 #if 0
 static int prepare_unused_channel_list(struct device *dev, void *data)
 {
-	struct platform_device *pdev = to_platform_device(dev);
-	int i, ctlr;
+    struct platform_device *pdev = to_platform_device(dev);
+    int i, ctlr;
 
-	for (i = 0; i < pdev->num_resources; i++) {
-		if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
-				(int)pdev->resource[i].start >= 0) {
-			ctlr = EDMA_CTLR(pdev->resource[i].start);
-			clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
-					edma_cc[ctlr]->edma_unused);
-		}
-	}
+    for (i = 0; i < pdev->num_resources; i++) {
+        if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
+                (int)pdev->resource[i].start >= 0) {
+            ctlr = EDMA_CTLR(pdev->resource[i].start);
+            clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
+                    edma_cc[ctlr]->edma_unused);
+        }
+    }
 
-	return 0;
+    return 0;
 }
 #endif
 
@@ -676,8 +676,8 @@ static rt_bool_t unused_chan_list_done;
  * @callback: optional; to be issued on DMA completion or errors
  * @data: passed to callback
  * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
- *	Controller (TC) executes requests using this channel.  Use
- *	EVENTQ_DEFAULT unless you really need a high priority queue.
+ *  Controller (TC) executes requests using this channel.  Use
+ *  EVENTQ_DEFAULT unless you really need a high priority queue.
  *
  * This allocates a DMA channel and its associated parameter RAM slot.
  * The parameter RAM is initialized to hold a dummy transfer.
@@ -701,77 +701,77 @@ static rt_bool_t unused_chan_list_done;
  * Returns the number of the channel, else negative errno.
  */
 int edma_alloc_channel(int channel,
-		void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data),
-		void *data,
-		enum dma_event_q eventq_no)
+        void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data),
+        void *data,
+        enum dma_event_q eventq_no)
 {
-	unsigned i, done = 0, ctlr = 0;
-	int ret = 0;
+    unsigned i, done = 0, ctlr = 0;
+    int ret = 0;
 #if 0
-	if (!unused_chan_list_done) {
-		/*
-		 * Scan all the platform devices to find out the EDMA channels
-		 * used and clear them in the unused list, making the rest
-		 * available for ARM usage.
-		 */
-		ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
-				prepare_unused_channel_list);
-		if (ret < 0)
-			return ret;
+    if (!unused_chan_list_done) {
+        /*
+         * Scan all the platform devices to find out the EDMA channels
+         * used and clear them in the unused list, making the rest
+         * available for ARM usage.
+         */
+        ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
+                prepare_unused_channel_list);
+        if (ret < 0)
+            return ret;
 
-		unused_chan_list_done = true;
-	}
+        unused_chan_list_done = true;
+    }
 #endif
 
-	if (channel >= 0) {
-		ctlr = EDMA_CTLR(channel);
-		channel = EDMA_CHAN_SLOT(channel);
- 		clear_bit(channel, edma_cc[ctlr]->edma_unused);
-	}
+    if (channel >= 0) {
+        ctlr = EDMA_CTLR(channel);
+        channel = EDMA_CHAN_SLOT(channel);
+        clear_bit(channel, edma_cc[ctlr]->edma_unused);
+    }
 
-	if (channel < 0) {
-		for (i = 0; i < arch_num_cc; i++) {
-			channel = 0;
-			for (;;) {
-				channel = find_next_bit(edma_cc[i]->edma_unused,
-						edma_cc[i]->num_channels,
-						channel);
-				if (channel == edma_cc[i]->num_channels)
-					break;
-				if (!test_and_set_bit(channel,
-						edma_cc[i]->edma_inuse)) {
-					done = 1;
-					ctlr = i;
-					break;
-				}
-				channel++;
-			}
-			if (done)
-				break;
-		}
-		if (!done)
-			return -RT_ENOMEM;
-	} else if (channel >= edma_cc[ctlr]->num_channels) {
-		return -RT_ERROR;
-	} else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
-		return -RT_EBUSY;
-	}
+    if (channel < 0) {
+        for (i = 0; i < arch_num_cc; i++) {
+            channel = 0;
+            for (;;) {
+                channel = find_next_bit(edma_cc[i]->edma_unused,
+                        edma_cc[i]->num_channels,
+                        channel);
+                if (channel == edma_cc[i]->num_channels)
+                    break;
+                if (!test_and_set_bit(channel,
+                        edma_cc[i]->edma_inuse)) {
+                    done = 1;
+                    ctlr = i;
+                    break;
+                }
+                channel++;
+            }
+            if (done)
+                break;
+        }
+        if (!done)
+            return -RT_ENOMEM;
+    } else if (channel >= edma_cc[ctlr]->num_channels) {
+        return -RT_ERROR;
+    } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
+        return -RT_EBUSY;
+    }
 
-	/* ensure access through shadow region 0 */
-	edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
+    /* ensure access through shadow region 0 */
+    edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
 
-	/* ensure no events are pending */
-	edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
-	rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)),
-			&dummy_paramset, PARM_SIZE);
+    /* ensure no events are pending */
+    edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
+    rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)),
+            &dummy_paramset, PARM_SIZE);
 
-	if (callback)
-		setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
-					callback, data);
+    if (callback)
+        setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
+                    callback, data);
 
-	map_dmach_queue(ctlr, channel, eventq_no);
+    map_dmach_queue(ctlr, channel, eventq_no);
 
-	return EDMA_CTLR_CHAN(ctlr, channel);
+    return EDMA_CTLR_CHAN(ctlr, channel);
 }
 
 
@@ -788,20 +788,20 @@ int edma_alloc_channel(int channel,
  */
 void edma_free_channel(unsigned channel)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(channel);
-	channel = EDMA_CHAN_SLOT(channel);
+    ctlr = EDMA_CTLR(channel);
+    channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel >= edma_cc[ctlr]->num_channels)
-		return;
+    if (channel >= edma_cc[ctlr]->num_channels)
+        return;
 
-	setup_dma_interrupt(channel, RT_NULL, RT_NULL);
-	/* REVISIT should probably take out of shadow region 0 */
+    setup_dma_interrupt(channel, RT_NULL, RT_NULL);
+    /* REVISIT should probably take out of shadow region 0 */
 
-	rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)),
-			&dummy_paramset, PARM_SIZE);
-	clear_bit(channel, edma_cc[ctlr]->edma_inuse);
+    rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)),
+            &dummy_paramset, PARM_SIZE);
+    clear_bit(channel, edma_cc[ctlr]->edma_inuse);
 }
 
 
@@ -821,30 +821,30 @@ void edma_free_channel(unsigned channel)
  */
 int edma_alloc_slot(unsigned ctlr, int slot)
 {
-	if (slot >= 0)
-		slot = EDMA_CHAN_SLOT(slot);
+    if (slot >= 0)
+        slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < 0) {
-		slot = edma_cc[ctlr]->num_channels;
-		for (;;) {
-			slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
-					edma_cc[ctlr]->num_slots, slot);
-			if (slot == edma_cc[ctlr]->num_slots)
-				return -RT_ENOMEM;
-			if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
-				break;
-		}
-	} else if (slot < edma_cc[ctlr]->num_channels ||
-			slot >= edma_cc[ctlr]->num_slots) {
-		return -RT_ERROR;
-	} else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
-		return -RT_EBUSY;
-	}
+    if (slot < 0) {
+        slot = edma_cc[ctlr]->num_channels;
+        for (;;) {
+            slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
+                    edma_cc[ctlr]->num_slots, slot);
+            if (slot == edma_cc[ctlr]->num_slots)
+                return -RT_ENOMEM;
+            if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
+                break;
+        }
+    } else if (slot < edma_cc[ctlr]->num_channels ||
+            slot >= edma_cc[ctlr]->num_slots) {
+        return -RT_ERROR;
+    } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
+        return -RT_EBUSY;
+    }
 
-	rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)),
-			&dummy_paramset, PARM_SIZE);
+    rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)),
+            &dummy_paramset, PARM_SIZE);
 
-	return EDMA_CTLR_CHAN(ctlr, slot);
+    return EDMA_CTLR_CHAN(ctlr, slot);
 }
 
 
@@ -858,18 +858,18 @@ int edma_alloc_slot(unsigned ctlr, int slot)
  */
 void edma_free_slot(unsigned slot)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(slot);
-	slot = EDMA_CHAN_SLOT(slot);
+    ctlr = EDMA_CTLR(slot);
+    slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_cc[ctlr]->num_channels ||
-		slot >= edma_cc[ctlr]->num_slots)
-		return;
+    if (slot < edma_cc[ctlr]->num_channels ||
+        slot >= edma_cc[ctlr]->num_slots)
+        return;
 
-	rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)),
-			&dummy_paramset, PARM_SIZE);
-	clear_bit(slot, edma_cc[ctlr]->edma_inuse);
+    rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)),
+            &dummy_paramset, PARM_SIZE);
+    clear_bit(slot, edma_cc[ctlr]->edma_inuse);
 }
 
 
@@ -901,35 +901,35 @@ void edma_free_slot(unsigned slot)
  */
 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
 {
-	/*
-	 * The start slot requested should be greater than
-	 * the number of channels and lesser than the total number
-	 * of slots
-	 */
-	if ((id != EDMA_CONT_PARAMS_ANY) &&
-		(slot < edma_cc[ctlr]->num_channels ||
-		slot >= edma_cc[ctlr]->num_slots))
-		return -RT_ERROR;
+    /*
+     * The start slot requested should be greater than
+     * the number of channels and lesser than the total number
+     * of slots
+     */
+    if ((id != EDMA_CONT_PARAMS_ANY) &&
+        (slot < edma_cc[ctlr]->num_channels ||
+        slot >= edma_cc[ctlr]->num_slots))
+        return -RT_ERROR;
 
-	/*
-	 * The number of parameter RAM slots requested cannot be less than 1
-	 * and cannot be more than the number of slots minus the number of
-	 * channels
-	 */
-	if (count < 1 || count >
-		(edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
-		return -RT_ERROR;
+    /*
+     * The number of parameter RAM slots requested cannot be less than 1
+     * and cannot be more than the number of slots minus the number of
+     * channels
+     */
+    if (count < 1 || count >
+        (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
+        return -RT_ERROR;
 
-	switch (id) {
-	case EDMA_CONT_PARAMS_ANY:
-		return reserve_contiguous_slots(ctlr, id, count,
-						 edma_cc[ctlr]->num_channels);
-	case EDMA_CONT_PARAMS_FIXED_EXACT:
-	case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
-		return reserve_contiguous_slots(ctlr, id, count, slot);
-	default:
-		return -RT_ERROR;
-	}
+    switch (id) {
+    case EDMA_CONT_PARAMS_ANY:
+        return reserve_contiguous_slots(ctlr, id, count,
+                         edma_cc[ctlr]->num_channels);
+    case EDMA_CONT_PARAMS_FIXED_EXACT:
+    case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
+        return reserve_contiguous_slots(ctlr, id, count, slot);
+    default:
+        return -RT_ERROR;
+    }
 
 }
 
@@ -949,27 +949,27 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
  */
 int edma_free_cont_slots(unsigned slot, int count)
 {
-	unsigned ctlr, slot_to_free;
-	int i;
+    unsigned ctlr, slot_to_free;
+    int i;
 
-	ctlr = EDMA_CTLR(slot);
-	slot = EDMA_CHAN_SLOT(slot);
+    ctlr = EDMA_CTLR(slot);
+    slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_cc[ctlr]->num_channels ||
-		slot >= edma_cc[ctlr]->num_slots ||
-		count < 1)
-		return -RT_ERROR;
+    if (slot < edma_cc[ctlr]->num_channels ||
+        slot >= edma_cc[ctlr]->num_slots ||
+        count < 1)
+        return -RT_ERROR;
 
-	for (i = slot; i < slot + count; ++i) {
-		ctlr = EDMA_CTLR(i);
-		slot_to_free = EDMA_CHAN_SLOT(i);
+    for (i = slot; i < slot + count; ++i) {
+        ctlr = EDMA_CTLR(i);
+        slot_to_free = EDMA_CHAN_SLOT(i);
 
-		rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free)),
-			&dummy_paramset, PARM_SIZE);
-		clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
-	}
+        rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free)),
+            &dummy_paramset, PARM_SIZE);
+        clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
+    }
 
-	return 0;
+    return 0;
 }
 
 
@@ -983,35 +983,35 @@ int edma_free_cont_slots(unsigned slot, int count)
  * @src_port: physical address of source (memory, controller FIFO, etc)
  * @addressMode: INCR, except in very rare cases
  * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
- *	width to use when addressing the fifo (e.g. W8BIT, W32BIT)
+ *  width to use when addressing the fifo (e.g. W8BIT, W32BIT)
  *
  * Note that the source address is modified during the DMA transfer
  * according to edma_set_src_index().
  */
 void edma_set_src(unsigned slot, rt_uint32_t src_port,
-				enum address_mode mode, enum fifo_width width)
+                enum address_mode mode, enum fifo_width width)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(slot);
-	slot = EDMA_CHAN_SLOT(slot);
+    ctlr = EDMA_CTLR(slot);
+    slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_cc[ctlr]->num_slots) {
-		unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
+    if (slot < edma_cc[ctlr]->num_slots) {
+        unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
 
-		if (mode) {
-			/* set SAM and program FWID */
-			i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
-		} else {
-			/* clear SAM */
-			i &= ~SAM;
-		}
-		edma_parm_write(ctlr, PARM_OPT, slot, i);
+        if (mode) {
+            /* set SAM and program FWID */
+            i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
+        } else {
+            /* clear SAM */
+            i &= ~SAM;
+        }
+        edma_parm_write(ctlr, PARM_OPT, slot, i);
 
-		/* set the source port address
-		   in source register of param structure */
-		edma_parm_write(ctlr, PARM_SRC, slot, src_port);
-	}
+        /* set the source port address
+           in source register of param structure */
+        edma_parm_write(ctlr, PARM_SRC, slot, src_port);
+    }
 }
 
 
@@ -1021,34 +1021,34 @@ void edma_set_src(unsigned slot, rt_uint32_t src_port,
  * @dest_port: physical address of destination (memory, controller FIFO, etc)
  * @addressMode: INCR, except in very rare cases
  * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
- *	width to use when addressing the fifo (e.g. W8BIT, W32BIT)
+ *  width to use when addressing the fifo (e.g. W8BIT, W32BIT)
  *
  * Note that the destination address is modified during the DMA transfer
  * according to edma_set_dest_index().
  */
 void edma_set_dest(unsigned slot, rt_uint32_t dest_port,
-				 enum address_mode mode, enum fifo_width width)
+                 enum address_mode mode, enum fifo_width width)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(slot);
-	slot = EDMA_CHAN_SLOT(slot);
+    ctlr = EDMA_CTLR(slot);
+    slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_cc[ctlr]->num_slots) {
-		unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
+    if (slot < edma_cc[ctlr]->num_slots) {
+        unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
 
-		if (mode) {
-			/* set DAM and program FWID */
-			i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
-		} else {
-			/* clear DAM */
-			i &= ~DAM;
-		}
-		edma_parm_write(ctlr, PARM_OPT, slot, i);
-		/* set the destination port address
-		   in dest register of param structure */
-		edma_parm_write(ctlr, PARM_DST, slot, dest_port);
-	}
+        if (mode) {
+            /* set DAM and program FWID */
+            i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
+        } else {
+            /* clear DAM */
+            i &= ~DAM;
+        }
+        edma_parm_write(ctlr, PARM_OPT, slot, i);
+        /* set the destination port address
+           in dest register of param structure */
+        edma_parm_write(ctlr, PARM_DST, slot, dest_port);
+    }
 }
 
 
@@ -1063,17 +1063,17 @@ void edma_set_dest(unsigned slot, rt_uint32_t dest_port,
  */
 void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst)
 {
-	struct edmacc_param temp;
-	unsigned ctlr;
+    struct edmacc_param temp;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(slot);
-	slot = EDMA_CHAN_SLOT(slot);
+    ctlr = EDMA_CTLR(slot);
+    slot = EDMA_CHAN_SLOT(slot);
 
-	edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
-	if (src != RT_NULL)
-		*src = temp.src;
-	if (dst != RT_NULL)
-		*dst = temp.dst;
+    edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
+    if (src != RT_NULL)
+        *src = temp.src;
+    if (dst != RT_NULL)
+        *dst = temp.dst;
 }
 
 
@@ -1089,17 +1089,17 @@ void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst)
  */
 void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(slot);
-	slot = EDMA_CHAN_SLOT(slot);
+    ctlr = EDMA_CTLR(slot);
+    slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_cc[ctlr]->num_slots) {
-		edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
-				0xffff0000, src_bidx);
-		edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
-				0xffff0000, src_cidx);
-	}
+    if (slot < edma_cc[ctlr]->num_slots) {
+        edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
+                0xffff0000, src_bidx);
+        edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
+                0xffff0000, src_cidx);
+    }
 }
 
 
@@ -1115,17 +1115,17 @@ void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx)
  */
 void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_cidx)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(slot);
-	slot = EDMA_CHAN_SLOT(slot);
+    ctlr = EDMA_CTLR(slot);
+    slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_cc[ctlr]->num_slots) {
-		edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
-				0x0000ffff, dest_bidx << 16);
-		edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
-				0x0000ffff, dest_cidx << 16);
-	}
+    if (slot < edma_cc[ctlr]->num_slots) {
+        edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
+                0x0000ffff, dest_bidx << 16);
+        edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
+                0x0000ffff, dest_cidx << 16);
+    }
 }
 
 
@@ -1136,7 +1136,7 @@ void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_ci
  * @bcnt: how many arrays per frame (at least one)
  * @ccnt: how many frames per block (at least one)
  * @bcnt_rld: used only for A-Synchronized transfers; this specifies
- *	the value to reload into bcnt when it decrements to zero
+ *  the value to reload into bcnt when it decrements to zero
  * @sync_mode: ASYNC or ABSYNC
  *
  * See the EDMA3 documentation to understand how to configure and link
@@ -1159,25 +1159,25 @@ void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_ci
  * efficient burst modes to access memory.
  */
 void edma_set_transfer_params(unsigned slot,
-		rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt,
-		rt_uint16_t bcnt_rld, enum sync_dimension sync_mode)
+        rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt,
+        rt_uint16_t bcnt_rld, enum sync_dimension sync_mode)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(slot);
-	slot = EDMA_CHAN_SLOT(slot);
+    ctlr = EDMA_CTLR(slot);
+    slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot < edma_cc[ctlr]->num_slots) {
-		edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
-				0x0000ffff, bcnt_rld << 16);
-		if (sync_mode == ASYNC)
-			edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
-		else
-			edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
-		/* Set the acount, bcount, ccount registers */
-		edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
-		edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
-	}
+    if (slot < edma_cc[ctlr]->num_slots) {
+        edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
+                0x0000ffff, bcnt_rld << 16);
+        if (sync_mode == ASYNC)
+            edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
+        else
+            edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
+        /* Set the acount, bcount, ccount registers */
+        edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
+        edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
+    }
 }
 
 
@@ -1190,19 +1190,19 @@ void edma_set_transfer_params(unsigned slot,
  */
 void edma_link(unsigned from, unsigned to)
 {
-	unsigned ctlr_from, ctlr_to;
+    unsigned ctlr_from, ctlr_to;
 
-	ctlr_from = EDMA_CTLR(from);
-	from = EDMA_CHAN_SLOT(from);
-	ctlr_to = EDMA_CTLR(to);
-	to = EDMA_CHAN_SLOT(to);
+    ctlr_from = EDMA_CTLR(from);
+    from = EDMA_CHAN_SLOT(from);
+    ctlr_to = EDMA_CTLR(to);
+    to = EDMA_CHAN_SLOT(to);
 
-	if (from >= edma_cc[ctlr_from]->num_slots)
-		return;
-	if (to >= edma_cc[ctlr_to]->num_slots)
-		return;
-	edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
-				PARM_OFFSET(to));
+    if (from >= edma_cc[ctlr_from]->num_slots)
+        return;
+    if (to >= edma_cc[ctlr_to]->num_slots)
+        return;
+    edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
+                PARM_OFFSET(to));
 }
 
 
@@ -1215,14 +1215,14 @@ void edma_link(unsigned from, unsigned to)
  */
 void edma_unlink(unsigned from)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(from);
-	from = EDMA_CHAN_SLOT(from);
+    ctlr = EDMA_CTLR(from);
+    from = EDMA_CHAN_SLOT(from);
 
-	if (from >= edma_cc[ctlr]->num_slots)
-		return;
-	edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
+    if (from >= edma_cc[ctlr]->num_slots)
+        return;
+    edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
 }
 
 
@@ -1242,15 +1242,15 @@ void edma_unlink(unsigned from)
  */
 void edma_write_slot(unsigned slot, const struct edmacc_param *param)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(slot);
-	slot = EDMA_CHAN_SLOT(slot);
+    ctlr = EDMA_CTLR(slot);
+    slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot >= edma_cc[ctlr]->num_slots)
-		return;
-	rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), param,
-			PARM_SIZE);
+    if (slot >= edma_cc[ctlr]->num_slots)
+        return;
+    rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), param,
+            PARM_SIZE);
 }
 
 
@@ -1264,15 +1264,15 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param)
  */
 void edma_read_slot(unsigned slot, struct edmacc_param *param)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(slot);
-	slot = EDMA_CHAN_SLOT(slot);
+    ctlr = EDMA_CTLR(slot);
+    slot = EDMA_CHAN_SLOT(slot);
 
-	if (slot >= edma_cc[ctlr]->num_slots)
-		return;
-	rt_memcpy(param, (void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)),
-			PARM_SIZE);
+    if (slot >= edma_cc[ctlr]->num_slots)
+        return;
+    rt_memcpy(param, (void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)),
+            PARM_SIZE);
 }
 
 
@@ -1289,16 +1289,16 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param)
  */
 void edma_pause(unsigned channel)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(channel);
-	channel = EDMA_CHAN_SLOT(channel);
+    ctlr = EDMA_CTLR(channel);
+    channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_cc[ctlr]->num_channels) {
-		unsigned int mask = BIT(channel & 0x1f);
+    if (channel < edma_cc[ctlr]->num_channels) {
+        unsigned int mask = BIT(channel & 0x1f);
 
-		edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
-	}
+        edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
+    }
 }
 
 
@@ -1310,16 +1310,16 @@ void edma_pause(unsigned channel)
  */
 void edma_resume(unsigned channel)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(channel);
-	channel = EDMA_CHAN_SLOT(channel);
+    ctlr = EDMA_CTLR(channel);
+    channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_cc[ctlr]->num_channels) {
-		unsigned int mask = BIT(channel & 0x1f);
+    if (channel < edma_cc[ctlr]->num_channels) {
+        unsigned int mask = BIT(channel & 0x1f);
 
-		edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
-	}
+        edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
+    }
 }
 
 
@@ -1336,38 +1336,38 @@ void edma_resume(unsigned channel)
  */
 int edma_start(unsigned channel)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(channel);
-	channel = EDMA_CHAN_SLOT(channel);
+    ctlr = EDMA_CTLR(channel);
+    channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_cc[ctlr]->num_channels) {
-		int j = channel >> 5;
-		unsigned int mask = BIT(channel & 0x1f);
+    if (channel < edma_cc[ctlr]->num_channels) {
+        int j = channel >> 5;
+        unsigned int mask = BIT(channel & 0x1f);
 
-		/* EDMA channels without event association */
-		if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
-			edma_dbg("EDMA: ESR%d %08x\n", j,
-				edma_shadow0_read_array(ctlr, SH_ESR, j));
-			edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
-			return 0;
-		}
+        /* EDMA channels without event association */
+        if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
+            edma_dbg("EDMA: ESR%d %08x\n", j,
+                edma_shadow0_read_array(ctlr, SH_ESR, j));
+            edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
+            return 0;
+        }
 
-		/* EDMA channel with event association */
-		edma_dbg("EDMA: ER%d %08x\n", j,
-			edma_shadow0_read_array(ctlr, SH_ER, j));
-		/* Clear any pending event or error */
-		edma_write_array(ctlr, EDMA_ECR, j, mask);
-		edma_write_array(ctlr, EDMA_EMCR, j, mask);
-		/* Clear any SER */
-		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
-		edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
-		edma_dbg("EDMA: EER%d %08x\n", j,
-			edma_shadow0_read_array(ctlr, SH_EER, j));
-		return 0;
-	}
+        /* EDMA channel with event association */
+        edma_dbg("EDMA: ER%d %08x\n", j,
+            edma_shadow0_read_array(ctlr, SH_ER, j));
+        /* Clear any pending event or error */
+        edma_write_array(ctlr, EDMA_ECR, j, mask);
+        edma_write_array(ctlr, EDMA_EMCR, j, mask);
+        /* Clear any SER */
+        edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+        edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
+        edma_dbg("EDMA: EER%d %08x\n", j,
+            edma_shadow0_read_array(ctlr, SH_EER, j));
+        return 0;
+    }
 
-	return -RT_ERROR;
+    return -RT_ERROR;
 }
 
 
@@ -1382,27 +1382,27 @@ int edma_start(unsigned channel)
  */
 void edma_stop(unsigned channel)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(channel);
-	channel = EDMA_CHAN_SLOT(channel);
+    ctlr = EDMA_CTLR(channel);
+    channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_cc[ctlr]->num_channels) {
-		int j = channel >> 5;
-		unsigned int mask = BIT(channel & 0x1f);
+    if (channel < edma_cc[ctlr]->num_channels) {
+        int j = channel >> 5;
+        unsigned int mask = BIT(channel & 0x1f);
 
-		edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
-		edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
-		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
-		edma_write_array(ctlr, EDMA_EMCR, j, mask);
+        edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
+        edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
+        edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+        edma_write_array(ctlr, EDMA_EMCR, j, mask);
 
-		edma_dbg("EDMA: EER%d %08x\n", j,
-				edma_shadow0_read_array(ctlr, SH_EER, j));
+        edma_dbg("EDMA: EER%d %08x\n", j,
+                edma_shadow0_read_array(ctlr, SH_EER, j));
 
-		/* REVISIT:  consider guarding against inappropriate event
-		 * chaining by overwriting with dummy_paramset.
-		 */
-	}
+        /* REVISIT:  consider guarding against inappropriate event
+         * chaining by overwriting with dummy_paramset.
+         */
+    }
 }
 
 
@@ -1421,45 +1421,45 @@ void edma_stop(unsigned channel)
 
 void edma_clean_channel(unsigned channel)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(channel);
-	channel = EDMA_CHAN_SLOT(channel);
+    ctlr = EDMA_CTLR(channel);
+    channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel < edma_cc[ctlr]->num_channels) {
-		int j = (channel >> 5);
-		unsigned int mask = BIT(channel & 0x1f);
+    if (channel < edma_cc[ctlr]->num_channels) {
+        int j = (channel >> 5);
+        unsigned int mask = BIT(channel & 0x1f);
 
-		edma_dbg("EDMA: EMR%d %08x\n", j,
-				edma_read_array(ctlr, EDMA_EMR, j));
-		edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
-		/* Clear the corresponding EMR bits */
-		edma_write_array(ctlr, EDMA_EMCR, j, mask);
-		/* Clear any SER */
-		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
-		edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
-	}
+        edma_dbg("EDMA: EMR%d %08x\n", j,
+                edma_read_array(ctlr, EDMA_EMR, j));
+        edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
+        /* Clear the corresponding EMR bits */
+        edma_write_array(ctlr, EDMA_EMCR, j, mask);
+        /* Clear any SER */
+        edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
+        edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
+    }
 }
 
 
 /*
  * edma_clear_event - clear an outstanding event on the DMA channel
  * Arguments:
- *	channel - channel number
+ *  channel - channel number
  */
 void edma_clear_event(unsigned channel)
 {
-	unsigned ctlr;
+    unsigned ctlr;
 
-	ctlr = EDMA_CTLR(channel);
-	channel = EDMA_CHAN_SLOT(channel);
+    ctlr = EDMA_CTLR(channel);
+    channel = EDMA_CHAN_SLOT(channel);
 
-	if (channel >= edma_cc[ctlr]->num_channels)
-		return;
-	if (channel < 32)
-		edma_write(ctlr, EDMA_ECR, BIT(channel));
-	else
-		edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
+    if (channel >= edma_cc[ctlr]->num_channels)
+        return;
+    if (channel < 32)
+        edma_write(ctlr, EDMA_ECR, BIT(channel));
+    else
+        edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
 }
 
 
@@ -1467,112 +1467,112 @@ void edma_clear_event(unsigned channel)
 
 int edma_init(struct edma_soc_info **info)
 {
-	//struct edma_soc_info	**info = pdev->dev.platform_data;
-	const rt_int8_t		(*queue_priority_mapping)[2];
-	const rt_int8_t		(*queue_tc_mapping)[2];
-	int			i, j, off, ln, found = 0;
-	int			status = -1;
-	const rt_int16_t		(*rsv_chans)[2];
-	const rt_int16_t		(*rsv_slots)[2];
-	int			irq[EDMA_MAX_CC] = {0, 0};
-	int			err_irq[EDMA_MAX_CC] = {0, 0};
+    //struct edma_soc_info  **info = pdev->dev.platform_data;
+    const rt_int8_t     (*queue_priority_mapping)[2];
+    const rt_int8_t     (*queue_tc_mapping)[2];
+    int         i, j, off, ln, found = 0;
+    int         status = -1;
+    const rt_int16_t        (*rsv_chans)[2];
+    const rt_int16_t        (*rsv_slots)[2];
+    int         irq[EDMA_MAX_CC] = {0, 0};
+    int         err_irq[EDMA_MAX_CC] = {0, 0};
 
-	RT_ASSERT(info != RT_NULL);
+    RT_ASSERT(info != RT_NULL);
 
-	psc_change_state(DAVINCI_DM365_LPSC_TPCC, PSC_ENABLE);
-	psc_change_state(DAVINCI_DM365_LPSC_TPTC0, PSC_ENABLE);
-	psc_change_state(DAVINCI_DM365_LPSC_TPTC1, PSC_ENABLE);
-	psc_change_state(DAVINCI_DM365_LPSC_TPTC2, PSC_ENABLE);
-	psc_change_state(DAVINCI_DM365_LPSC_TPTC3, PSC_ENABLE);
+    psc_change_state(DAVINCI_DM365_LPSC_TPCC, PSC_ENABLE);
+    psc_change_state(DAVINCI_DM365_LPSC_TPTC0, PSC_ENABLE);
+    psc_change_state(DAVINCI_DM365_LPSC_TPTC1, PSC_ENABLE);
+    psc_change_state(DAVINCI_DM365_LPSC_TPTC2, PSC_ENABLE);
+    psc_change_state(DAVINCI_DM365_LPSC_TPTC3, PSC_ENABLE);
 
-	edmacc_regs_base[0] = (void *)EDMA_CC0_BASE_REG;
+    edmacc_regs_base[0] = (void *)EDMA_CC0_BASE_REG;
 
-	edma_cc[0] = rt_malloc(sizeof(struct edma));
-	if (!edma_cc[0]) {
-		status = -RT_ENOMEM;
-		goto fail1;
-	}
-	rt_memset(edma_cc[0], 0, sizeof(struct edma));
+    edma_cc[0] = rt_malloc(sizeof(struct edma));
+    if (!edma_cc[0]) {
+        status = -RT_ENOMEM;
+        goto fail1;
+    }
+    rt_memset(edma_cc[0], 0, sizeof(struct edma));
 
-	edma_cc[0]->num_channels = min_t(unsigned, info[0]->n_channel,
-						EDMA_MAX_DMACH);
-	edma_cc[0]->num_slots = min_t(unsigned, info[0]->n_slot,
-						EDMA_MAX_PARAMENTRY);
-	edma_cc[0]->num_cc = min_t(unsigned, info[0]->n_cc,
-						EDMA_MAX_CC);
+    edma_cc[0]->num_channels = min_t(unsigned, info[0]->n_channel,
+                        EDMA_MAX_DMACH);
+    edma_cc[0]->num_slots = min_t(unsigned, info[0]->n_slot,
+                        EDMA_MAX_PARAMENTRY);
+    edma_cc[0]->num_cc = min_t(unsigned, info[0]->n_cc,
+                        EDMA_MAX_CC);
 
-	edma_cc[0]->default_queue = info[0]->default_queue;
-	if (!edma_cc[0]->default_queue)
-		edma_cc[0]->default_queue = EVENTQ_1;
+    edma_cc[0]->default_queue = info[0]->default_queue;
+    if (!edma_cc[0]->default_queue)
+        edma_cc[0]->default_queue = EVENTQ_1;
 
-	edma_dbg("DMA REG BASE ADDR=%p\n",
-		edmacc_regs_base[j]);
+    edma_dbg("DMA REG BASE ADDR=%p\n",
+        edmacc_regs_base[j]);
 
-	for (i = 0; i < edma_cc[0]->num_slots; i++)
-		rt_memcpy((void *)(edmacc_regs_base[0] + PARM_OFFSET(i)),
-				&dummy_paramset, PARM_SIZE);
+    for (i = 0; i < edma_cc[0]->num_slots; i++)
+        rt_memcpy((void *)(edmacc_regs_base[0] + PARM_OFFSET(i)),
+                &dummy_paramset, PARM_SIZE);
 
-	/* Mark all channels as unused */
-	rt_memset(edma_cc[0]->edma_unused, 0xff,
-		sizeof(edma_cc[0]->edma_unused));
+    /* Mark all channels as unused */
+    rt_memset(edma_cc[0]->edma_unused, 0xff,
+        sizeof(edma_cc[0]->edma_unused));
 
-	edma_cc[0]->irq_res_start = IRQ_CCINT0;
-	rt_hw_interrupt_install(IRQ_CCINT0, dma_irq_handler, RT_NULL, "edma");
-	rt_hw_interrupt_umask(IRQ_CCINT0);
+    edma_cc[0]->irq_res_start = IRQ_CCINT0;
+    rt_hw_interrupt_install(IRQ_CCINT0, dma_irq_handler, RT_NULL, "edma");
+    rt_hw_interrupt_umask(IRQ_CCINT0);
 
-	edma_cc[0]->irq_res_end = IRQ_CCERRINT;
-	rt_hw_interrupt_install(IRQ_CCERRINT, dma_ccerr_handler, RT_NULL, "edma_error");
-	rt_hw_interrupt_umask(IRQ_CCERRINT);
+    edma_cc[0]->irq_res_end = IRQ_CCERRINT;
+    rt_hw_interrupt_install(IRQ_CCERRINT, dma_ccerr_handler, RT_NULL, "edma_error");
+    rt_hw_interrupt_umask(IRQ_CCERRINT);
 
-	/* Everything lives on transfer controller 1 until otherwise
-	 * specified. This way, long transfers on the low priority queue
-	 * started by the codec engine will not cause audio defects.
-	 */
-	for (i = 0; i < edma_cc[0]->num_channels; i++)
-		map_dmach_queue(0, i, EVENTQ_1);
+    /* Everything lives on transfer controller 1 until otherwise
+     * specified. This way, long transfers on the low priority queue
+     * started by the codec engine will not cause audio defects.
+     */
+    for (i = 0; i < edma_cc[0]->num_channels; i++)
+        map_dmach_queue(0, i, EVENTQ_1);
 
-	queue_tc_mapping = info[0]->queue_tc_mapping;
-	queue_priority_mapping = info[0]->queue_priority_mapping;
+    queue_tc_mapping = info[0]->queue_tc_mapping;
+    queue_priority_mapping = info[0]->queue_priority_mapping;
 
-	/* Event queue to TC mapping */
-	for (i = 0; queue_tc_mapping[i][0] != -1; i++)
-		map_queue_tc(0, queue_tc_mapping[i][0],
-				queue_tc_mapping[i][1]);
+    /* Event queue to TC mapping */
+    for (i = 0; queue_tc_mapping[i][0] != -1; i++)
+        map_queue_tc(0, queue_tc_mapping[i][0],
+                queue_tc_mapping[i][1]);
 
-	/* Event queue priority mapping */
-	for (i = 0; queue_priority_mapping[i][0] != -1; i++)
-		assign_priority_to_queue(0,
-					queue_priority_mapping[i][0],
-					queue_priority_mapping[i][1]);
+    /* Event queue priority mapping */
+    for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+        assign_priority_to_queue(0,
+                    queue_priority_mapping[i][0],
+                    queue_priority_mapping[i][1]);
 
-	/* Map the channel to param entry if channel mapping logic
-	 * exist
-	 */
-	if (edma_read(0, EDMA_CCCFG) & CHMAP_EXIST)
-		map_dmach_param(0);
+    /* Map the channel to param entry if channel mapping logic
+     * exist
+     */
+    if (edma_read(0, EDMA_CCCFG) & CHMAP_EXIST)
+        map_dmach_param(0);
 
-	for (i = 0; i < info[0]->n_region; i++) {
-		edma_write_array2(0, EDMA_DRAE, i, 0, 0x0);
-		edma_write_array2(0, EDMA_DRAE, i, 1, 0x0);
-		edma_write_array(0, EDMA_QRAE, i, 0x0);
-	}
-	arch_num_cc++;
+    for (i = 0; i < info[0]->n_region; i++) {
+        edma_write_array2(0, EDMA_DRAE, i, 0, 0x0);
+        edma_write_array2(0, EDMA_DRAE, i, 1, 0x0);
+        edma_write_array(0, EDMA_QRAE, i, 0x0);
+    }
+    arch_num_cc++;
 
-	if (tc_errs_handled) {
- 		rt_hw_interrupt_install(IRQ_TCERRINT0, dma_tc0err_handler, "edma_tc0");
-		rt_hw_interrupt_umask(IRQ_TCERRINT0);
-		rt_hw_interrupt_install(IRQ_TCERRINT, dma_tc1err_handler, "edma_tc1");
-		rt_hw_interrupt_umask(IRQ_TCERRINT);
-	}
+    if (tc_errs_handled) {
+        rt_hw_interrupt_install(IRQ_TCERRINT0, dma_tc0err_handler, "edma_tc0");
+        rt_hw_interrupt_umask(IRQ_TCERRINT0);
+        rt_hw_interrupt_install(IRQ_TCERRINT, dma_tc1err_handler, "edma_tc1");
+        rt_hw_interrupt_umask(IRQ_TCERRINT);
+    }
 
-	return 0;
+    return 0;
 
 fail:
 
 fail1:
-	rt_free(edma_cc[0]);
+    rt_free(edma_cc[0]);
 
-	return status;
+    return status;
 }
 
 
diff --git a/bsp/dm365/platform/edma.h b/bsp/dm365/platform/edma.h
index 4264767318..57007f5bbb 100644
--- a/bsp/dm365/platform/edma.h
+++ b/bsp/dm365/platform/edma.h
@@ -4,22 +4,22 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 /*
  * This EDMA3 programming framework exposes two basic kinds of resource:
  *
- *  Channel	Triggers transfers, usually from a hardware event but
- *		also manually or by "chaining" from DMA completions.
- *		Each channel is coupled to a Parameter RAM (PaRAM) slot.
+ *  Channel Triggers transfers, usually from a hardware event but
+ *      also manually or by "chaining" from DMA completions.
+ *      Each channel is coupled to a Parameter RAM (PaRAM) slot.
  *
- *  Slot	Each PaRAM slot holds a DMA transfer descriptor (PaRAM
- *		"set"), source and destination addresses, a link to a
- *		next PaRAM slot (if any), options for the transfer, and
- *		instructions for updating those addresses.  There are
- *		more than twice as many slots as event channels.
+ *  Slot    Each PaRAM slot holds a DMA transfer descriptor (PaRAM
+ *      "set"), source and destination addresses, a link to a
+ *      next PaRAM slot (if any), options for the transfer, and
+ *      instructions for updating those addresses.  There are
+ *      more than twice as many slots as event channels.
  *
  * Each PaRAM set describes a sequence of transfers, either for one large
  * buffer or for several discontiguous smaller buffers.  An EDMA transfer
@@ -52,14 +52,14 @@
 
 /* PaRAM slots are laid out like this */
 struct edmacc_param {
-	unsigned int opt;
-	unsigned int src;
-	unsigned int a_b_cnt;
-	unsigned int dst;
-	unsigned int src_dst_bidx;
-	unsigned int link_bcntrld;
-	unsigned int src_dst_cidx;
-	unsigned int ccnt;
+    unsigned int opt;
+    unsigned int src;
+    unsigned int a_b_cnt;
+    unsigned int dst;
+    unsigned int src_dst_bidx;
+    unsigned int link_bcntrld;
+    unsigned int src_dst_cidx;
+    unsigned int ccnt;
 };
 
 #define CCINT0_INTERRUPT     16
@@ -68,110 +68,110 @@ struct edmacc_param {
 #define TCERRINT1_INTERRUPT   19
 
 /* fields in edmacc_param.opt */
-#define SAM		BIT(0)
-#define DAM		BIT(1)
-#define SYNCDIM		BIT(2)
-#define STATIC		BIT(3)
-#define EDMA_FWID	(0x07 << 8)
-#define TCCMODE		BIT(11)
-#define EDMA_TCC(t)	((t) << 12)
-#define TCINTEN		BIT(20)
-#define ITCINTEN	BIT(21)
-#define TCCHEN		BIT(22)
-#define ITCCHEN		BIT(23)
+#define SAM     BIT(0)
+#define DAM     BIT(1)
+#define SYNCDIM     BIT(2)
+#define STATIC      BIT(3)
+#define EDMA_FWID   (0x07 << 8)
+#define TCCMODE     BIT(11)
+#define EDMA_TCC(t) ((t) << 12)
+#define TCINTEN     BIT(20)
+#define ITCINTEN    BIT(21)
+#define TCCHEN      BIT(22)
+#define ITCCHEN     BIT(23)
 
 #define TRWORD (0x7<<2)
 #define PAENTRY (0x1ff<<5)
 
 /* DM365 specific EDMA3 Events Information */
 enum dm365_edma_ch {
-	DM365_DMA_TIMER3_TINT6,
-	DM365_DMA_TIMER3_TINT7,
-	DM365_DMA_MCBSP_TX = 2,
-	DM365_DMA_VCIF_TX = 2,
-	DM365_DMA_MCBSP_RX = 3,
-	DM365_DMA_VCIF_RX = 3,
-	DM365_DMA_VPSS_EVT1,
-	DM365_DMA_VPSS_EVT2,
-	DM365_DMA_VPSS_EVT3,
-	DM365_DMA_VPSS_EVT4,
-	DM365_DMA_TIMER2_TINT4,
-	DM365_DMA_TIMER2_TINT5,
-	DM365_DMA_SPI2XEVT,
-	DM365_DMA_SPI2REVT,
-	DM365_DMA_IMCOP_IMX0INT = 12,
-	DM365_DMA_KALEIDO_ARMINT = 12,
-	DM365_DMA_IMCOP_SEQINT,
-	DM365_DMA_SPI1XEVT,
-	DM365_DMA_SPI1REVT,
-	DM365_DMA_SPI0XEVT,
-	DM365_DMA_SPI0REVT,
-	DM365_DMA_URXEVT0 = 18,
-	DM365_DMA_SPI3XEVT = 18,
-	DM365_DMA_UTXEVT0 = 19,
-	DM365_DMA_SPI3REVT = 19,
-	DM365_DMA_URXEVT1,
-	DM365_DMA_UTXEVT1,
-	DM365_DMA_TIMER4_TINT8,
-	DM365_DMA_TIMER4_TINT9,
-	DM365_DMA_RTOINT,
-	DM365_DMA_GPIONT9,
-	DM365_DMA_MMC0RXEVT = 26,
-	DM365_DMA_MEMSTK_MSEVT = 26,
-	DM365_DMA_MMC0TXEVT,
-	DM365_DMA_I2C_ICREVT,
-	DM365_DMA_I2C_ICXEVT,
-	DM365_DMA_MMC1RXEVT,
-	DM365_DMA_MMC1TXEVT,
-	DM365_DMA_GPIOINT0,
-	DM365_DMA_GPIOINT1,
-	DM365_DMA_GPIOINT2,
-	DM365_DMA_GPIOINT3,
-	DM365_DMA_GPIOINT4,
-	DM365_DMA_GPIOINT5,
-	DM365_DMA_GPIOINT6,
-	DM365_DMA_GPIOINT7,
-	DM365_DMA_GPIOINT10 = 40,
-	DM365_DMA_EMAC_RXTHREESH = 40,
-	DM365_DMA_GPIOINT11 = 41,
-	DM365_DMA_EMAC_RXPULSE = 41,
-	DM365_DMA_GPIOINT12 = 42,
-	DM365_DMA_EMAC_TXPULSE = 42,
-	DM365_DMA_GPIOINT13 = 43,
-	DM365_DMA_EMAC_MISCPULSE = 43,
-	DM365_DMA_GPIOINT14 = 44,
-	DM365_DMA_SPI4XEVT = 44,
-	DM365_DMA_GPIOINT15 = 45,
-	DM365_DMA_SPI4REVT = 45,
-	DM365_DMA_ADC_ADINT,
-	DM365_DMA_GPIOINT8,
-	DM365_DMA_TIMER0_TINT0,
-	DM365_DMA_TIMER0_TINT1,
-	DM365_DMA_TIMER1_TINT2,
-	DM365_DMA_TIMER1_TINT3,
-	DM365_DMA_PWM0,
-	DM365_DMA_PWM1 = 53,
-	DM365_DMA_IMCOP_IMX1INT = 53,
-	DM365_DMA_PWM2 = 54,
-	DM365_DMA_IMCOP_NSFINT = 54,
-	DM365_DMA_PWM3 = 55,
-	DM365_DMA_KALEIDO6_CP_UNDEF = 55,
-	DM365_DMA_IMCOP_VLCDINT = 56,
-	DM365_DMA_KALEIDO5_CP_ECDCMP = 56,
-	DM365_DMA_IMCOP_BIMINT = 57,
-	DM365_DMA_KALEIDO8_CP_ME = 57,
-	DM365_DMA_IMCOP_DCTINT = 58,
-	DM365_DMA_KALEIDO1_CP_CALC = 58,
-	DM365_DMA_IMCOP_QIQINT = 59,
-	DM365_DMA_KALEIDO7_CP_IPE = 59,
-	DM365_DMA_IMCOP_BPSINT = 60,
-	DM365_DMA_KALEIDO2_CP_BS = 60,
-	DM365_DMA_IMCOP_VLCDERRINT = 61,
-	DM365_DMA_KALEIDO0_CP_LPF = 61,
-	DM365_DMA_IMCOP_RCNTINT = 62,
-	DM365_DMA_KALEIDO3_CP_MC = 62,
-	DM365_DMA_IMCOP_COPCINT = 63,
-	DM365_DMA_KALEIDO4_CP_ECDEND = 63,
+    DM365_DMA_TIMER3_TINT6,
+    DM365_DMA_TIMER3_TINT7,
+    DM365_DMA_MCBSP_TX = 2,
+    DM365_DMA_VCIF_TX = 2,
+    DM365_DMA_MCBSP_RX = 3,
+    DM365_DMA_VCIF_RX = 3,
+    DM365_DMA_VPSS_EVT1,
+    DM365_DMA_VPSS_EVT2,
+    DM365_DMA_VPSS_EVT3,
+    DM365_DMA_VPSS_EVT4,
+    DM365_DMA_TIMER2_TINT4,
+    DM365_DMA_TIMER2_TINT5,
+    DM365_DMA_SPI2XEVT,
+    DM365_DMA_SPI2REVT,
+    DM365_DMA_IMCOP_IMX0INT = 12,
+    DM365_DMA_KALEIDO_ARMINT = 12,
+    DM365_DMA_IMCOP_SEQINT,
+    DM365_DMA_SPI1XEVT,
+    DM365_DMA_SPI1REVT,
+    DM365_DMA_SPI0XEVT,
+    DM365_DMA_SPI0REVT,
+    DM365_DMA_URXEVT0 = 18,
+    DM365_DMA_SPI3XEVT = 18,
+    DM365_DMA_UTXEVT0 = 19,
+    DM365_DMA_SPI3REVT = 19,
+    DM365_DMA_URXEVT1,
+    DM365_DMA_UTXEVT1,
+    DM365_DMA_TIMER4_TINT8,
+    DM365_DMA_TIMER4_TINT9,
+    DM365_DMA_RTOINT,
+    DM365_DMA_GPIONT9,
+    DM365_DMA_MMC0RXEVT = 26,
+    DM365_DMA_MEMSTK_MSEVT = 26,
+    DM365_DMA_MMC0TXEVT,
+    DM365_DMA_I2C_ICREVT,
+    DM365_DMA_I2C_ICXEVT,
+    DM365_DMA_MMC1RXEVT,
+    DM365_DMA_MMC1TXEVT,
+    DM365_DMA_GPIOINT0,
+    DM365_DMA_GPIOINT1,
+    DM365_DMA_GPIOINT2,
+    DM365_DMA_GPIOINT3,
+    DM365_DMA_GPIOINT4,
+    DM365_DMA_GPIOINT5,
+    DM365_DMA_GPIOINT6,
+    DM365_DMA_GPIOINT7,
+    DM365_DMA_GPIOINT10 = 40,
+    DM365_DMA_EMAC_RXTHREESH = 40,
+    DM365_DMA_GPIOINT11 = 41,
+    DM365_DMA_EMAC_RXPULSE = 41,
+    DM365_DMA_GPIOINT12 = 42,
+    DM365_DMA_EMAC_TXPULSE = 42,
+    DM365_DMA_GPIOINT13 = 43,
+    DM365_DMA_EMAC_MISCPULSE = 43,
+    DM365_DMA_GPIOINT14 = 44,
+    DM365_DMA_SPI4XEVT = 44,
+    DM365_DMA_GPIOINT15 = 45,
+    DM365_DMA_SPI4REVT = 45,
+    DM365_DMA_ADC_ADINT,
+    DM365_DMA_GPIOINT8,
+    DM365_DMA_TIMER0_TINT0,
+    DM365_DMA_TIMER0_TINT1,
+    DM365_DMA_TIMER1_TINT2,
+    DM365_DMA_TIMER1_TINT3,
+    DM365_DMA_PWM0,
+    DM365_DMA_PWM1 = 53,
+    DM365_DMA_IMCOP_IMX1INT = 53,
+    DM365_DMA_PWM2 = 54,
+    DM365_DMA_IMCOP_NSFINT = 54,
+    DM365_DMA_PWM3 = 55,
+    DM365_DMA_KALEIDO6_CP_UNDEF = 55,
+    DM365_DMA_IMCOP_VLCDINT = 56,
+    DM365_DMA_KALEIDO5_CP_ECDCMP = 56,
+    DM365_DMA_IMCOP_BIMINT = 57,
+    DM365_DMA_KALEIDO8_CP_ME = 57,
+    DM365_DMA_IMCOP_DCTINT = 58,
+    DM365_DMA_KALEIDO1_CP_CALC = 58,
+    DM365_DMA_IMCOP_QIQINT = 59,
+    DM365_DMA_KALEIDO7_CP_IPE = 59,
+    DM365_DMA_IMCOP_BPSINT = 60,
+    DM365_DMA_KALEIDO2_CP_BS = 60,
+    DM365_DMA_IMCOP_VLCDERRINT = 61,
+    DM365_DMA_KALEIDO0_CP_LPF = 61,
+    DM365_DMA_IMCOP_RCNTINT = 62,
+    DM365_DMA_KALEIDO3_CP_MC = 62,
+    DM365_DMA_IMCOP_COPCINT = 63,
+    DM365_DMA_KALEIDO4_CP_ECDEND = 63,
 };
 /* end DM365 specific info */
 
@@ -183,48 +183,48 @@ enum dm365_edma_ch {
 #define DMA_TC2_ERROR 4
 
 enum address_mode {
-	INCR = 0,
-	FIFO = 1
+    INCR = 0,
+    FIFO = 1
 };
 
 enum fifo_width {
-	W8BIT = 0,
-	W16BIT = 1,
-	W32BIT = 2,
-	W64BIT = 3,
-	W128BIT = 4,
-	W256BIT = 5
+    W8BIT = 0,
+    W16BIT = 1,
+    W32BIT = 2,
+    W64BIT = 3,
+    W128BIT = 4,
+    W256BIT = 5
 };
 
 enum dma_event_q {
-	EVENTQ_0 = 0,
-	EVENTQ_1 = 1,
-	EVENTQ_2 = 2,
-	EVENTQ_3 = 3,
-	EVENTQ_DEFAULT = -1
+    EVENTQ_0 = 0,
+    EVENTQ_1 = 1,
+    EVENTQ_2 = 2,
+    EVENTQ_3 = 3,
+    EVENTQ_DEFAULT = -1
 };
 
 enum sync_dimension {
-	ASYNC = 0,
-	ABSYNC = 1
+    ASYNC = 0,
+    ABSYNC = 1
 };
 
-#define EDMA_CTLR_CHAN(ctlr, chan)	(((ctlr) << 16) | (chan))
-#define EDMA_CTLR(i)			((i) >> 16)
-#define EDMA_CHAN_SLOT(i)		((i) & 0xffff)
+#define EDMA_CTLR_CHAN(ctlr, chan)  (((ctlr) << 16) | (chan))
+#define EDMA_CTLR(i)            ((i) >> 16)
+#define EDMA_CHAN_SLOT(i)       ((i) & 0xffff)
 
-#define EDMA_CHANNEL_ANY		-1	/* for edma_alloc_channel() */
-#define EDMA_SLOT_ANY			-1	/* for edma_alloc_slot() */
-#define EDMA_CONT_PARAMS_ANY		 1001
-#define EDMA_CONT_PARAMS_FIXED_EXACT	 1002
+#define EDMA_CHANNEL_ANY        -1  /* for edma_alloc_channel() */
+#define EDMA_SLOT_ANY           -1  /* for edma_alloc_slot() */
+#define EDMA_CONT_PARAMS_ANY         1001
+#define EDMA_CONT_PARAMS_FIXED_EXACT     1002
 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
 
 #define EDMA_MAX_CC               2
 
 /* alloc/free DMA channels and their dedicated parameter RAM slots */
 int edma_alloc_channel(int channel,
-	void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data),
-	void *data, enum dma_event_q);
+    void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data),
+    void *data, enum dma_event_q);
 void edma_free_channel(unsigned channel);
 
 /* alloc/free parameter RAM slots */
@@ -237,14 +237,14 @@ int edma_free_cont_slots(unsigned slot, int count);
 
 /* calls that operate on part of a parameter RAM slot */
 void edma_set_src(unsigned slot, rt_uint32_t src_port,
-				enum address_mode mode, enum fifo_width);
+                enum address_mode mode, enum fifo_width);
 void edma_set_dest(unsigned slot, rt_uint32_t dest_port,
-				 enum address_mode mode, enum fifo_width);
+                 enum address_mode mode, enum fifo_width);
 void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst);
 void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx);
 void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_cidx);
 void edma_set_transfer_params(unsigned slot, rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt,
-		rt_uint16_t bcnt_rld, enum sync_dimension sync_mode);
+        rt_uint16_t bcnt_rld, enum sync_dimension sync_mode);
 void edma_link(unsigned from, unsigned to);
 void edma_unlink(unsigned from);
 
@@ -263,26 +263,26 @@ void edma_resume(unsigned channel);
 
 struct edma_rsv_info {
 
-	const rt_int16_t	(*rsv_chans)[2];
-	const rt_int16_t	(*rsv_slots)[2];
+    const rt_int16_t    (*rsv_chans)[2];
+    const rt_int16_t    (*rsv_slots)[2];
 };
 
 /* platform_data for EDMA driver */
 struct edma_soc_info {
 
-	/* how many dma resources of each type */
-	unsigned	n_channel;
-	unsigned	n_region;
-	unsigned	n_slot;
-	unsigned	n_tc;
-	unsigned	n_cc;
-	enum dma_event_q	default_queue;
+    /* how many dma resources of each type */
+    unsigned    n_channel;
+    unsigned    n_region;
+    unsigned    n_slot;
+    unsigned    n_tc;
+    unsigned    n_cc;
+    enum dma_event_q    default_queue;
 
-	/* Resource reservation for other cores */
-	struct edma_rsv_info	*rsv;
+    /* Resource reservation for other cores */
+    struct edma_rsv_info    *rsv;
 
-	const rt_int8_t	(*queue_tc_mapping)[2];
-	const rt_int8_t	(*queue_priority_mapping)[2];
+    const rt_int8_t (*queue_tc_mapping)[2];
+    const rt_int8_t (*queue_priority_mapping)[2];
 };
 
 int edma_init(struct edma_soc_info **info);
diff --git a/bsp/dm365/platform/interrupt.c b/bsp/dm365/platform/interrupt.c
index 72171990d0..6334072bcd 100644
--- a/bsp/dm365/platform/interrupt.c
+++ b/bsp/dm365/platform/interrupt.c
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 
@@ -13,7 +13,7 @@
 #include <rthw.h>
 #include "dm36x.h"
 
-#define MAX_HANDLERS	64
+#define MAX_HANDLERS    64
 
 extern rt_uint32_t rt_interrupt_nest;
 
@@ -23,95 +23,95 @@ struct rt_irq_desc irq_desc[MAX_HANDLERS];
 rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
 rt_uint32_t rt_thread_switch_interrupt_flag;
 
-#define IRQ_BIT(irq)		((irq) & 0x1f)
+#define IRQ_BIT(irq)        ((irq) & 0x1f)
 
-#define FIQ_REG0_OFFSET		0x0000
-#define FIQ_REG1_OFFSET		0x0004
-#define IRQ_REG0_OFFSET		0x0008
-#define IRQ_REG1_OFFSET		0x000C
-#define IRQ_ENT_REG0_OFFSET	0x0018
-#define IRQ_ENT_REG1_OFFSET	0x001C
-#define IRQ_INCTL_REG_OFFSET	0x0020
-#define IRQ_EABASE_REG_OFFSET	0x0024
-#define IRQ_INTPRI0_REG_OFFSET	0x0030
-#define IRQ_INTPRI7_REG_OFFSET	0x004C
+#define FIQ_REG0_OFFSET     0x0000
+#define FIQ_REG1_OFFSET     0x0004
+#define IRQ_REG0_OFFSET     0x0008
+#define IRQ_REG1_OFFSET     0x000C
+#define IRQ_ENT_REG0_OFFSET 0x0018
+#define IRQ_ENT_REG1_OFFSET 0x001C
+#define IRQ_INCTL_REG_OFFSET    0x0020
+#define IRQ_EABASE_REG_OFFSET   0x0024
+#define IRQ_INTPRI0_REG_OFFSET  0x0030
+#define IRQ_INTPRI7_REG_OFFSET  0x004C
 
 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 static const rt_uint8_t dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
-	[IRQ_DM3XX_VPSSINT0]	= 2,
-	[IRQ_DM3XX_VPSSINT1]	= 6,
-	[IRQ_DM3XX_VPSSINT2]	= 6,
-	[IRQ_DM3XX_VPSSINT3]	= 6,
-	[IRQ_DM3XX_VPSSINT4]	= 6,
-	[IRQ_DM3XX_VPSSINT5]	= 6,
-	[IRQ_DM3XX_VPSSINT6]	= 6,
-	[IRQ_DM3XX_VPSSINT7]	= 7,
-	[IRQ_DM3XX_VPSSINT8]	= 6,
-	[IRQ_ASQINT]		= 6,
-	[IRQ_DM365_IMXINT0]	= 6,
-	[IRQ_DM3XX_IMCOPINT]	= 6,
-	[IRQ_USBINT]		= 4,
-	[IRQ_DM3XX_RTOINT]	= 4,
-	[IRQ_DM3XX_TINT5]	= 7,
-	[IRQ_DM3XX_TINT6]	= 7,
-	[IRQ_CCINT0]		= 5,	/* dma */
-	[IRQ_DM3XX_SPINT1_0]	= 5,	/* dma */
-	[IRQ_DM3XX_SPINT1_1]	= 5,	/* dma */
-	[IRQ_DM3XX_SPINT2_0]	= 5,	/* dma */
-	[IRQ_DM365_PSCINT]	= 7,
-	[IRQ_DM3XX_SPINT2_1]	= 7,
-	[IRQ_DM3XX_TINT7]	= 4,
-	[IRQ_DM3XX_SDIOINT0]	= 7,
-	[IRQ_DM365_MBXINT]	= 7,
-	[IRQ_DM365_MBRINT]	= 7,
-	[IRQ_DM3XX_MMCINT0]	= 7,
-	[IRQ_DM3XX_MMCINT1]	= 7,
-	[IRQ_DM3XX_PWMINT3]	= 7,
-	[IRQ_DM365_DDRINT]	= 7,
-	[IRQ_DM365_AEMIFINT]	= 7,
-	[IRQ_DM3XX_SDIOINT1]	= 4,
-	[IRQ_DM365_TINT0]	= 2,	/* clockevent */
-	[IRQ_DM365_TINT1]	= 2,	/* clocksource */
-	[IRQ_DM365_TINT2]	= 7,	/* DSP timer */
-	[IRQ_DM365_TINT3]	= 7,	/* system tick */
-	[IRQ_PWMINT0]		= 7,
-	[IRQ_PWMINT1]		= 7,
-	[IRQ_DM365_PWMINT2]	= 7,
-	[IRQ_DM365_IICINT]	= 3,
-	[IRQ_UARTINT0]		= 3,
-	[IRQ_UARTINT1]		= 3,
-	[IRQ_DM3XX_SPINT0_0]	= 3,
-	[IRQ_DM3XX_SPINT0_1]	= 3,
-	[IRQ_DM3XX_GPIO0]	= 3,
-	[IRQ_DM3XX_GPIO1]	= 7,
-	[IRQ_DM3XX_GPIO2]	= 4,
-	[IRQ_DM3XX_GPIO3]	= 4,
-	[IRQ_DM3XX_GPIO4]	= 7,
-	[IRQ_DM3XX_GPIO5]	= 7,
-	[IRQ_DM3XX_GPIO6]	= 7,
-	[IRQ_DM3XX_GPIO7]	= 7,
-	[IRQ_DM3XX_GPIO8]	= 7,
-	[IRQ_DM3XX_GPIO9]	= 7,
-	[IRQ_DM365_GPIO10]	= 7,
-	[IRQ_DM365_GPIO11]	= 7,
-	[IRQ_DM365_GPIO12]	= 7,
-	[IRQ_DM365_GPIO13]	= 7,
-	[IRQ_DM365_GPIO14]	= 7,
-	[IRQ_DM365_GPIO15]	= 7,
-	[IRQ_DM365_KEYINT]	= 7,
-	[IRQ_DM365_COMMTX]	= 7,
-	[IRQ_DM365_COMMRX]	= 7,
-	[IRQ_EMUINT]		= 7,
+    [IRQ_DM3XX_VPSSINT0]    = 2,
+    [IRQ_DM3XX_VPSSINT1]    = 6,
+    [IRQ_DM3XX_VPSSINT2]    = 6,
+    [IRQ_DM3XX_VPSSINT3]    = 6,
+    [IRQ_DM3XX_VPSSINT4]    = 6,
+    [IRQ_DM3XX_VPSSINT5]    = 6,
+    [IRQ_DM3XX_VPSSINT6]    = 6,
+    [IRQ_DM3XX_VPSSINT7]    = 7,
+    [IRQ_DM3XX_VPSSINT8]    = 6,
+    [IRQ_ASQINT]        = 6,
+    [IRQ_DM365_IMXINT0] = 6,
+    [IRQ_DM3XX_IMCOPINT]    = 6,
+    [IRQ_USBINT]        = 4,
+    [IRQ_DM3XX_RTOINT]  = 4,
+    [IRQ_DM3XX_TINT5]   = 7,
+    [IRQ_DM3XX_TINT6]   = 7,
+    [IRQ_CCINT0]        = 5,    /* dma */
+    [IRQ_DM3XX_SPINT1_0]    = 5,    /* dma */
+    [IRQ_DM3XX_SPINT1_1]    = 5,    /* dma */
+    [IRQ_DM3XX_SPINT2_0]    = 5,    /* dma */
+    [IRQ_DM365_PSCINT]  = 7,
+    [IRQ_DM3XX_SPINT2_1]    = 7,
+    [IRQ_DM3XX_TINT7]   = 4,
+    [IRQ_DM3XX_SDIOINT0]    = 7,
+    [IRQ_DM365_MBXINT]  = 7,
+    [IRQ_DM365_MBRINT]  = 7,
+    [IRQ_DM3XX_MMCINT0] = 7,
+    [IRQ_DM3XX_MMCINT1] = 7,
+    [IRQ_DM3XX_PWMINT3] = 7,
+    [IRQ_DM365_DDRINT]  = 7,
+    [IRQ_DM365_AEMIFINT]    = 7,
+    [IRQ_DM3XX_SDIOINT1]    = 4,
+    [IRQ_DM365_TINT0]   = 2,    /* clockevent */
+    [IRQ_DM365_TINT1]   = 2,    /* clocksource */
+    [IRQ_DM365_TINT2]   = 7,    /* DSP timer */
+    [IRQ_DM365_TINT3]   = 7,    /* system tick */
+    [IRQ_PWMINT0]       = 7,
+    [IRQ_PWMINT1]       = 7,
+    [IRQ_DM365_PWMINT2] = 7,
+    [IRQ_DM365_IICINT]  = 3,
+    [IRQ_UARTINT0]      = 3,
+    [IRQ_UARTINT1]      = 3,
+    [IRQ_DM3XX_SPINT0_0]    = 3,
+    [IRQ_DM3XX_SPINT0_1]    = 3,
+    [IRQ_DM3XX_GPIO0]   = 3,
+    [IRQ_DM3XX_GPIO1]   = 7,
+    [IRQ_DM3XX_GPIO2]   = 4,
+    [IRQ_DM3XX_GPIO3]   = 4,
+    [IRQ_DM3XX_GPIO4]   = 7,
+    [IRQ_DM3XX_GPIO5]   = 7,
+    [IRQ_DM3XX_GPIO6]   = 7,
+    [IRQ_DM3XX_GPIO7]   = 7,
+    [IRQ_DM3XX_GPIO8]   = 7,
+    [IRQ_DM3XX_GPIO9]   = 7,
+    [IRQ_DM365_GPIO10]  = 7,
+    [IRQ_DM365_GPIO11]  = 7,
+    [IRQ_DM365_GPIO12]  = 7,
+    [IRQ_DM365_GPIO13]  = 7,
+    [IRQ_DM365_GPIO14]  = 7,
+    [IRQ_DM365_GPIO15]  = 7,
+    [IRQ_DM365_KEYINT]  = 7,
+    [IRQ_DM365_COMMTX]  = 7,
+    [IRQ_DM365_COMMRX]  = 7,
+    [IRQ_EMUINT]        = 7,
 };
 
 static inline unsigned int davinci_irq_readl(int offset)
 {
-	return davinci_readl(DAVINCI_ARM_INTC_BASE + offset);
+    return davinci_readl(DAVINCI_ARM_INTC_BASE + offset);
 }
 
 static inline void davinci_irq_writel(unsigned long value, int offset)
 {
-	davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset);
+    davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset);
 }
 
 /**
@@ -121,8 +121,8 @@ static inline void davinci_irq_writel(unsigned long value, int offset)
 
 rt_isr_handler_t rt_hw_interrupt_handle(int vector, void *param)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-	return RT_NULL;
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    return RT_NULL;
 }
 
 /**
@@ -130,59 +130,59 @@ rt_isr_handler_t rt_hw_interrupt_handle(int vector, void *param)
  */
 void rt_hw_interrupt_init(void)
 {
-	int i;
-	register rt_uint32_t idx;
-	const rt_uint8_t *priority;
-	priority = dm365_default_priorities;
+    int i;
+    register rt_uint32_t idx;
+    const rt_uint8_t *priority;
+    priority = dm365_default_priorities;
 
-	/* Clear all interrupt requests */
-	davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
-	davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
-	davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
-	davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
+    /* Clear all interrupt requests */
+    davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
+    davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
+    davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
+    davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
 
-	/* Disable all interrupts */
-	davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
-	davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
+    /* Disable all interrupts */
+    davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
+    davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
 
-	/* Interrupts disabled immediately, IRQ entry reflects all */
-	davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
+    /* Interrupts disabled immediately, IRQ entry reflects all */
+    davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
 
-	/* we don't use the hardware vector table, just its entry addresses */
-	davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
+    /* we don't use the hardware vector table, just its entry addresses */
+    davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
 
-	/* Clear all interrupt requests */
-	davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
-	davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
-	davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
-	davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
+    /* Clear all interrupt requests */
+    davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
+    davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
+    davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
+    davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
 
-	for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
-		unsigned	j;
-		rt_uint32_t	pri;
+    for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
+        unsigned    j;
+        rt_uint32_t pri;
 
-		for (j = 0, pri = 0; j < 32; j += 4, priority++)
-			pri |= (*priority & 0x07) << j;
-		davinci_irq_writel(pri, i);
-	}
+        for (j = 0, pri = 0; j < 32; j += 4, priority++)
+            pri |= (*priority & 0x07) << j;
+        davinci_irq_writel(pri, i);
+    }
 
-	/* init exceptions table */
-	for(idx=0; idx < MAX_HANDLERS; idx++)
-	{
-		
-		irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
-		irq_desc[idx].param = RT_NULL;
-	#ifdef RT_USING_INTERRUPT_INFO
-		rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
-		irq_desc[idx].counter = 0;
-	#endif
-	}
+    /* init exceptions table */
+    for(idx=0; idx < MAX_HANDLERS; idx++)
+    {
 
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
+        irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
+        irq_desc[idx].param = RT_NULL;
+    #ifdef RT_USING_INTERRUPT_INFO
+        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
+        irq_desc[idx].counter = 0;
+    #endif
+    }
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
 }
 
 /**
@@ -191,20 +191,20 @@ void rt_hw_interrupt_init(void)
  */
 void rt_hw_interrupt_mask(int irq)
 {
-	unsigned int mask;
-	rt_uint32_t l;
+    unsigned int mask;
+    rt_uint32_t l;
 
-	mask = 1 << IRQ_BIT(irq);
+    mask = 1 << IRQ_BIT(irq);
 
-	if (irq > 31) {
-		l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
-		l &= ~mask;
-		davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
-	} else {
-		l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
-		l &= ~mask;
-		davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
-	}
+    if (irq > 31) {
+        l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
+        l &= ~mask;
+        davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
+    } else {
+        l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
+        l &= ~mask;
+        davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
+    }
 }
 
 /**
@@ -213,20 +213,20 @@ void rt_hw_interrupt_mask(int irq)
  */
 void rt_hw_interrupt_umask(int irq)
 {
-	unsigned int mask;
-	rt_uint32_t l;
+    unsigned int mask;
+    rt_uint32_t l;
 
-	mask = 1 << IRQ_BIT(irq);
+    mask = 1 << IRQ_BIT(irq);
 
-	if (irq > 31) {
-		l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
-		l |= mask;
-		davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
-	} else {
-		l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
-		l |= mask;
-		davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
-	}
+    if (irq > 31) {
+        l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
+        l |= mask;
+        davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
+    } else {
+        l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
+        l |= mask;
+        davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
+    }
 }
 
 /**
@@ -239,25 +239,25 @@ void rt_hw_interrupt_umask(int irq)
  */
 
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-									void *param, const char *name)
+                                    void *param, const char *name)
 {
-	rt_isr_handler_t old_handler = RT_NULL;
+    rt_isr_handler_t old_handler = RT_NULL;
 
-	if(vector < MAX_HANDLERS)
-	{
-		old_handler = irq_desc[vector].handler;
-		if (handler != RT_NULL)
-		{
-			irq_desc[vector].handler = (rt_isr_handler_t)handler;
-			irq_desc[vector].param = param;
-		#ifdef RT_USING_INTERRUPT_INFO
-			rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
-			irq_desc[vector].counter = 0;
-		#endif
-		}
-	}
+    if(vector < MAX_HANDLERS)
+    {
+        old_handler = irq_desc[vector].handler;
+        if (handler != RT_NULL)
+        {
+            irq_desc[vector].handler = (rt_isr_handler_t)handler;
+            irq_desc[vector].param = param;
+        #ifdef RT_USING_INTERRUPT_INFO
+            rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
+            irq_desc[vector].counter = 0;
+        #endif
+        }
+    }
 
-	return old_handler;
+    return old_handler;
 
 }
 
@@ -265,16 +265,16 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
 #ifdef RT_USING_INTERRUPT_INFO
 void list_irq(void)
 {
-	int irq;
-	
-	rt_kprintf("number\tcount\tname\n");
-	for (irq = 0; irq < MAX_HANDLERS; irq++)
-	{
-		if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
-		{
-			rt_kprintf("%02ld: %10ld  %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
-		}
-	}
+    int irq;
+
+    rt_kprintf("number\tcount\tname\n");
+    for (irq = 0; irq < MAX_HANDLERS; irq++)
+    {
+        if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
+        {
+            rt_kprintf("%02ld: %10ld  %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
+        }
+    }
 }
 
 #include <finsh.h>
diff --git a/bsp/dm365/platform/irqs.h b/bsp/dm365/platform/irqs.h
index 1588fc4b2f..b8c4ecc9e4 100644
--- a/bsp/dm365/platform/irqs.h
+++ b/bsp/dm365/platform/irqs.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 #ifndef __DM36X_IRQS_H__
@@ -18,7 +18,7 @@ extern "C" {
 /* Base address */
 #define DAVINCI_ARM_INTC_BASE 0x01C48000
 
-#define DAVINCI_N_AINTC_IRQ	64
+#define DAVINCI_N_AINTC_IRQ 64
 
 /* Interrupt lines */
 #define IRQ_VDINT0       0
@@ -88,100 +88,100 @@ extern "C" {
 /*
  * Base Interrupts common across DM355 and DM365
  */
-#define IRQ_DM3XX_VPSSINT0	0
-#define IRQ_DM3XX_VPSSINT1	1
-#define IRQ_DM3XX_VPSSINT2	2
-#define IRQ_DM3XX_VPSSINT3	3
-#define IRQ_DM3XX_VPSSINT4	4
-#define IRQ_DM3XX_VPSSINT5	5
-#define IRQ_DM3XX_VPSSINT6	6
-#define IRQ_DM3XX_VPSSINT7	7
-#define IRQ_DM3XX_VPSSINT8	8
-#define IRQ_DM3XX_IMCOPINT	11
-#define IRQ_DM3XX_RTOINT	13
-#define IRQ_DM3XX_TINT4		13
-#define IRQ_DM3XX_TINT2_TINT12	13
-#define IRQ_DM3XX_TINT5		14
-#define IRQ_DM3XX_TINT2_TINT34	14
-#define IRQ_DM3XX_TINT6		15
-#define IRQ_DM3XX_TINT3_TINT12	15
-#define IRQ_DM3XX_SPINT1_0	17
-#define IRQ_DM3XX_SPINT1_1	18
-#define IRQ_DM3XX_SPINT2_0	19
-#define IRQ_DM3XX_SPINT2_1	21
-#define IRQ_DM3XX_TINT7		22
-#define IRQ_DM3XX_TINT3_TINT34	22
-#define IRQ_DM3XX_SDIOINT0	23
-#define IRQ_DM3XX_MMCINT0	26
-#define IRQ_DM3XX_MSINT		26
-#define IRQ_DM3XX_MMCINT1	27
-#define IRQ_DM3XX_PWMINT3	28
-#define IRQ_DM3XX_SDIOINT1	31
-#define IRQ_DM3XX_SPINT0_0	42
-#define IRQ_DM3XX_SPINT0_1	43
-#define IRQ_DM3XX_GPIO0		44
-#define IRQ_DM3XX_GPIO1		45
-#define IRQ_DM3XX_GPIO2		46
-#define IRQ_DM3XX_GPIO3		47
-#define IRQ_DM3XX_GPIO4		48
-#define IRQ_DM3XX_GPIO5		49
-#define IRQ_DM3XX_GPIO6		50
-#define IRQ_DM3XX_GPIO7		51
-#define IRQ_DM3XX_GPIO8		52
-#define IRQ_DM3XX_GPIO9		53
+#define IRQ_DM3XX_VPSSINT0  0
+#define IRQ_DM3XX_VPSSINT1  1
+#define IRQ_DM3XX_VPSSINT2  2
+#define IRQ_DM3XX_VPSSINT3  3
+#define IRQ_DM3XX_VPSSINT4  4
+#define IRQ_DM3XX_VPSSINT5  5
+#define IRQ_DM3XX_VPSSINT6  6
+#define IRQ_DM3XX_VPSSINT7  7
+#define IRQ_DM3XX_VPSSINT8  8
+#define IRQ_DM3XX_IMCOPINT  11
+#define IRQ_DM3XX_RTOINT    13
+#define IRQ_DM3XX_TINT4     13
+#define IRQ_DM3XX_TINT2_TINT12  13
+#define IRQ_DM3XX_TINT5     14
+#define IRQ_DM3XX_TINT2_TINT34  14
+#define IRQ_DM3XX_TINT6     15
+#define IRQ_DM3XX_TINT3_TINT12  15
+#define IRQ_DM3XX_SPINT1_0  17
+#define IRQ_DM3XX_SPINT1_1  18
+#define IRQ_DM3XX_SPINT2_0  19
+#define IRQ_DM3XX_SPINT2_1  21
+#define IRQ_DM3XX_TINT7     22
+#define IRQ_DM3XX_TINT3_TINT34  22
+#define IRQ_DM3XX_SDIOINT0  23
+#define IRQ_DM3XX_MMCINT0   26
+#define IRQ_DM3XX_MSINT     26
+#define IRQ_DM3XX_MMCINT1   27
+#define IRQ_DM3XX_PWMINT3   28
+#define IRQ_DM3XX_SDIOINT1  31
+#define IRQ_DM3XX_SPINT0_0  42
+#define IRQ_DM3XX_SPINT0_1  43
+#define IRQ_DM3XX_GPIO0     44
+#define IRQ_DM3XX_GPIO1     45
+#define IRQ_DM3XX_GPIO2     46
+#define IRQ_DM3XX_GPIO3     47
+#define IRQ_DM3XX_GPIO4     48
+#define IRQ_DM3XX_GPIO5     49
+#define IRQ_DM3XX_GPIO6     50
+#define IRQ_DM3XX_GPIO7     51
+#define IRQ_DM3XX_GPIO8     52
+#define IRQ_DM3XX_GPIO9     53
 
 /* DaVinci DM365-specific Interrupts */
-#define IRQ_DM365_INSFINT	7
-#define IRQ_DM365_IMXINT1	8
-#define IRQ_DM365_IMXINT0	10
-#define IRQ_DM365_KLD_ARMINT	10
-#define IRQ_DM365_CCERRINT	17
-#define IRQ_DM365_TCERRINT0	18
-#define IRQ_DM365_SPINT2_0	19
-#define IRQ_DM365_PSCINT	20
-#define IRQ_DM365_TVINT		20
-#define IRQ_DM365_SPINT4_0	21
-#define IRQ_DM365_MBXINT	24
-#define IRQ_DM365_VCINT		24
-#define IRQ_DM365_MBRINT	25
-#define IRQ_DM365_TINT9		28
-#define IRQ_DM365_TINT4_TINT34	28
-#define IRQ_DM365_DDRINT	29
-#define IRQ_DM365_RTCINT	29
-#define IRQ_DM365_AEMIFINT	30
-#define IRQ_DM365_HPIINT	30
-#define IRQ_DM365_TINT0		32
-#define IRQ_DM365_TINT0_TINT12	32
-#define IRQ_DM365_TINT1		33
-#define IRQ_DM365_TINT0_TINT34	33
-#define IRQ_DM365_TINT2		34
-#define IRQ_DM365_TINT1_TINT12	34
-#define IRQ_DM365_TINT3		35
-#define IRQ_DM365_TINT1_TINT34	35
-#define IRQ_DM365_PWMINT2	38
-#define IRQ_DM365_TINT8		38
-#define IRQ_DM365_TINT4_TINT12	38
-#define IRQ_DM365_IICINT	39
-#define IRQ_DM365_SPINT3_0	43
-#define IRQ_DM365_EMAC_RXTHRESH	52
-#define IRQ_DM365_EMAC_RXPULSE	53
-#define IRQ_DM365_GPIO10	54
-#define IRQ_DM365_EMAC_TXPULSE	54
-#define IRQ_DM365_GPIO11	55
+#define IRQ_DM365_INSFINT   7
+#define IRQ_DM365_IMXINT1   8
+#define IRQ_DM365_IMXINT0   10
+#define IRQ_DM365_KLD_ARMINT    10
+#define IRQ_DM365_CCERRINT  17
+#define IRQ_DM365_TCERRINT0 18
+#define IRQ_DM365_SPINT2_0  19
+#define IRQ_DM365_PSCINT    20
+#define IRQ_DM365_TVINT     20
+#define IRQ_DM365_SPINT4_0  21
+#define IRQ_DM365_MBXINT    24
+#define IRQ_DM365_VCINT     24
+#define IRQ_DM365_MBRINT    25
+#define IRQ_DM365_TINT9     28
+#define IRQ_DM365_TINT4_TINT34  28
+#define IRQ_DM365_DDRINT    29
+#define IRQ_DM365_RTCINT    29
+#define IRQ_DM365_AEMIFINT  30
+#define IRQ_DM365_HPIINT    30
+#define IRQ_DM365_TINT0     32
+#define IRQ_DM365_TINT0_TINT12  32
+#define IRQ_DM365_TINT1     33
+#define IRQ_DM365_TINT0_TINT34  33
+#define IRQ_DM365_TINT2     34
+#define IRQ_DM365_TINT1_TINT12  34
+#define IRQ_DM365_TINT3     35
+#define IRQ_DM365_TINT1_TINT34  35
+#define IRQ_DM365_PWMINT2   38
+#define IRQ_DM365_TINT8     38
+#define IRQ_DM365_TINT4_TINT12  38
+#define IRQ_DM365_IICINT    39
+#define IRQ_DM365_SPINT3_0  43
+#define IRQ_DM365_EMAC_RXTHRESH 52
+#define IRQ_DM365_EMAC_RXPULSE  53
+#define IRQ_DM365_GPIO10    54
+#define IRQ_DM365_EMAC_TXPULSE  54
+#define IRQ_DM365_GPIO11    55
 #define IRQ_DM365_EMAC_MISCPULSE 55
-#define IRQ_DM365_GPIO12	56
-#define IRQ_DM365_PWRGIO0	56
-#define IRQ_DM365_GPIO13	57
-#define IRQ_DM365_PWRGIO1	57
-#define IRQ_DM365_GPIO14	58
-#define IRQ_DM365_PWRGIO2	58
-#define IRQ_DM365_GPIO15	59
-#define IRQ_DM365_ADCINT	59
-#define IRQ_DM365_KEYINT	60
-#define IRQ_DM365_COMMTX	61
-#define IRQ_DM365_TCERRINT2	61
-#define IRQ_DM365_COMMRX	62
-#define IRQ_DM365_TCERRINT3	62
+#define IRQ_DM365_GPIO12    56
+#define IRQ_DM365_PWRGIO0   56
+#define IRQ_DM365_GPIO13    57
+#define IRQ_DM365_PWRGIO1   57
+#define IRQ_DM365_GPIO14    58
+#define IRQ_DM365_PWRGIO2   58
+#define IRQ_DM365_GPIO15    59
+#define IRQ_DM365_ADCINT    59
+#define IRQ_DM365_KEYINT    60
+#define IRQ_DM365_COMMTX    61
+#define IRQ_DM365_TCERRINT2 61
+#define IRQ_DM365_COMMRX    62
+#define IRQ_DM365_TCERRINT3 62
 
 
 #ifdef __cplusplus
diff --git a/bsp/dm365/platform/psc.c b/bsp/dm365/platform/psc.c
index 52cab1f276..b2e0a90197 100644
--- a/bsp/dm365/platform/psc.c
+++ b/bsp/dm365/platform/psc.c
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 #include "dm36x.h"
@@ -19,13 +19,13 @@
  * ------------------------------------------------------------------------ */
 void psc_change_state(int id, int state)
 {
-	rt_uint32_t mdstat, mdctl;
+    rt_uint32_t mdstat, mdctl;
 
-	if (id > DAVINCI_DM365_LPSC_KALEIDO)
-		return;
+    if (id > DAVINCI_DM365_LPSC_KALEIDO)
+        return;
 
-	mdstat = PSC_MDSTAT_BASE + (id * 4);
-	mdctl = PSC_MDCTL_BASE + (id * 4);
+    mdstat = PSC_MDSTAT_BASE + (id * 4);
+    mdctl = PSC_MDCTL_BASE + (id * 4);
 
     /*
      *  Step 0 - Ignore request if the state is already set as is
diff --git a/bsp/dm365/platform/psc.h b/bsp/dm365/platform/psc.h
index d918b488a0..116b7b2dd7 100644
--- a/bsp/dm365/platform/psc.h
+++ b/bsp/dm365/platform/psc.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 #ifndef __DM36X_PSC_H
@@ -17,69 +17,69 @@ extern "C" {
 
 
 /* PSC register offsets */
-#define EPCPR		0x070
-#define PTCMD		0x120
-#define PTSTAT		0x128
-#define PDSTAT		0x200
-#define PDCTL1		0x304
-#define MDSTAT(n)	(0x800 + (n) * 4)
-#define MDCTL(n)	(0xA00 + (n) * 4)
+#define EPCPR       0x070
+#define PTCMD       0x120
+#define PTSTAT      0x128
+#define PDSTAT      0x200
+#define PDCTL1      0x304
+#define MDSTAT(n)   (0x800 + (n) * 4)
+#define MDCTL(n)    (0xA00 + (n) * 4)
 
 /* Power and Sleep Controller (PSC) Domains */
-#define DAVINCI_GPSC_ARMDOMAIN		0
-#define DAVINCI_GPSC_DSPDOMAIN		1
+#define DAVINCI_GPSC_ARMDOMAIN      0
+#define DAVINCI_GPSC_DSPDOMAIN      1
 
 
-#define DAVINCI_DM365_LPSC_TPCC		0
-#define DAVINCI_DM365_LPSC_TPTC0	1
-#define DAVINCI_DM365_LPSC_TPTC1	2
-#define DAVINCI_DM365_LPSC_TPTC2	3
-#define DAVINCI_DM365_LPSC_TPTC3	4
-#define DAVINCI_DM365_LPSC_TIMER3	5
-#define DAVINCI_DM365_LPSC_SPI1		6
-#define DAVINCI_DM365_LPSC_MMC_SD1	7
-#define DAVINCI_DM365_LPSC_McBSP	8
-#define DAVINCI_DM365_LPSC_USB		9
-#define DAVINCI_DM365_LPSC_PWM3		10
-#define DAVINCI_DM365_LPSC_SPI2		11
-#define DAVINCI_DM365_LPSC_RTO		12
-#define DAVINCI_DM365_LPSC_DDR_EMIF	13
-#define DAVINCI_DM365_LPSC_AEMIF	14
-#define DAVINCI_DM365_LPSC_MMC_SD	15
-#define DAVINCI_DM365_LPSC_MMC_SD0	15
-#define DAVINCI_DM365_LPSC_MEMSTICK	16
-#define DAVINCI_DM365_LPSC_TIMER4	17
-#define DAVINCI_DM365_LPSC_I2C		18
-#define DAVINCI_DM365_LPSC_UART0	19
-#define DAVINCI_DM365_LPSC_UART1	20
-#define DAVINCI_DM365_LPSC_UHPI		21
-#define DAVINCI_DM365_LPSC_SPI0		22
-#define DAVINCI_DM365_LPSC_PWM0		23
-#define DAVINCI_DM365_LPSC_PWM1		24
-#define DAVINCI_DM365_LPSC_PWM2		25
-#define DAVINCI_DM365_LPSC_GPIO		26
-#define DAVINCI_DM365_LPSC_TIMER0	27
-#define DAVINCI_DM365_LPSC_TIMER1	28
-#define DAVINCI_DM365_LPSC_TIMER2	29
+#define DAVINCI_DM365_LPSC_TPCC     0
+#define DAVINCI_DM365_LPSC_TPTC0    1
+#define DAVINCI_DM365_LPSC_TPTC1    2
+#define DAVINCI_DM365_LPSC_TPTC2    3
+#define DAVINCI_DM365_LPSC_TPTC3    4
+#define DAVINCI_DM365_LPSC_TIMER3   5
+#define DAVINCI_DM365_LPSC_SPI1     6
+#define DAVINCI_DM365_LPSC_MMC_SD1  7
+#define DAVINCI_DM365_LPSC_McBSP    8
+#define DAVINCI_DM365_LPSC_USB      9
+#define DAVINCI_DM365_LPSC_PWM3     10
+#define DAVINCI_DM365_LPSC_SPI2     11
+#define DAVINCI_DM365_LPSC_RTO      12
+#define DAVINCI_DM365_LPSC_DDR_EMIF 13
+#define DAVINCI_DM365_LPSC_AEMIF    14
+#define DAVINCI_DM365_LPSC_MMC_SD   15
+#define DAVINCI_DM365_LPSC_MMC_SD0  15
+#define DAVINCI_DM365_LPSC_MEMSTICK 16
+#define DAVINCI_DM365_LPSC_TIMER4   17
+#define DAVINCI_DM365_LPSC_I2C      18
+#define DAVINCI_DM365_LPSC_UART0    19
+#define DAVINCI_DM365_LPSC_UART1    20
+#define DAVINCI_DM365_LPSC_UHPI     21
+#define DAVINCI_DM365_LPSC_SPI0     22
+#define DAVINCI_DM365_LPSC_PWM0     23
+#define DAVINCI_DM365_LPSC_PWM1     24
+#define DAVINCI_DM365_LPSC_PWM2     25
+#define DAVINCI_DM365_LPSC_GPIO     26
+#define DAVINCI_DM365_LPSC_TIMER0   27
+#define DAVINCI_DM365_LPSC_TIMER1   28
+#define DAVINCI_DM365_LPSC_TIMER2   29
 #define DAVINCI_DM365_LPSC_SYSTEM_SUBSYS 30
-#define DAVINCI_DM365_LPSC_ARM		31
-#define DAVINCI_DM365_LPSC_SCR0		33
-#define DAVINCI_DM365_LPSC_SCR1		34
-#define DAVINCI_DM365_LPSC_EMU		35
-#define DAVINCI_DM365_LPSC_CHIPDFT	36
-#define DAVINCI_DM365_LPSC_PBIST	37
-#define DAVINCI_DM365_LPSC_SPI3		38
-#define DAVINCI_DM365_LPSC_SPI4		39
-#define DAVINCI_DM365_LPSC_CPGMAC	40
-#define DAVINCI_DM365_LPSC_RTC		41
-#define DAVINCI_DM365_LPSC_KEYSCAN	42
-#define DAVINCI_DM365_LPSC_ADCIF	43
-#define DAVINCI_DM365_LPSC_VOICE_CODEC	44
-#define DAVINCI_DM365_LPSC_DAC_CLKRES	45
-#define DAVINCI_DM365_LPSC_DAC_CLK	46
-#define DAVINCI_DM365_LPSC_VPSSMSTR	47
-#define DAVINCI_DM365_LPSC_IMCOP	50
-#define DAVINCI_DM365_LPSC_KALEIDO	51
+#define DAVINCI_DM365_LPSC_ARM      31
+#define DAVINCI_DM365_LPSC_SCR0     33
+#define DAVINCI_DM365_LPSC_SCR1     34
+#define DAVINCI_DM365_LPSC_EMU      35
+#define DAVINCI_DM365_LPSC_CHIPDFT  36
+#define DAVINCI_DM365_LPSC_PBIST    37
+#define DAVINCI_DM365_LPSC_SPI3     38
+#define DAVINCI_DM365_LPSC_SPI4     39
+#define DAVINCI_DM365_LPSC_CPGMAC   40
+#define DAVINCI_DM365_LPSC_RTC      41
+#define DAVINCI_DM365_LPSC_KEYSCAN  42
+#define DAVINCI_DM365_LPSC_ADCIF    43
+#define DAVINCI_DM365_LPSC_VOICE_CODEC  44
+#define DAVINCI_DM365_LPSC_DAC_CLKRES   45
+#define DAVINCI_DM365_LPSC_DAC_CLK  46
+#define DAVINCI_DM365_LPSC_VPSSMSTR 47
+#define DAVINCI_DM365_LPSC_IMCOP    50
+#define DAVINCI_DM365_LPSC_KALEIDO  51
 
 #define PSC_ENABLE     3
 #define PSC_DISABLE    2
diff --git a/bsp/dm365/platform/reset.c b/bsp/dm365/platform/reset.c
index 02ec9db4ae..dc80fac76e 100644
--- a/bsp/dm365/platform/reset.c
+++ b/bsp/dm365/platform/reset.c
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 
@@ -24,7 +24,7 @@
  */
 void machine_reset()
 {
-	reset_system();
+    reset_system();
 }
 
 /**
@@ -44,14 +44,14 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system);
 #ifdef FINSH_USING_MSH
 int cmd_reset(int argc, char** argv)
 {
-	rt_hw_cpu_reset();
-	return 0;
+    rt_hw_cpu_reset();
+    return 0;
 }
 
 int cmd_shutdown(int argc, char** argv)
 {
-	rt_hw_cpu_shutdown();
-	return 0;
+    rt_hw_cpu_shutdown();
+    return 0;
 }
 
 FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.);
diff --git a/bsp/dm365/platform/system_clock.c b/bsp/dm365/platform/system_clock.c
index 5d8bea4442..7d4c58874f 100644
--- a/bsp/dm365/platform/system_clock.c
+++ b/bsp/dm365/platform/system_clock.c
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 
@@ -19,6 +19,6 @@ extern int davinci_clk_init(void);
  */
 void rt_hw_clock_init(void)
 {
-	davinci_clk_init();
+    davinci_clk_init();
 }
 
diff --git a/bsp/dm365/platform/trap.c b/bsp/dm365/platform/trap.c
index 8c067f9f3b..5c5f0272b3 100644
--- a/bsp/dm365/platform/trap.c
+++ b/bsp/dm365/platform/trap.c
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 
@@ -32,13 +32,13 @@ extern long list_thread(void);
 
 void rt_hw_show_register (struct rt_hw_register *regs)
 {
-	rt_kprintf("Execption:\n");
-	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
-	rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
-	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-	rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
 }
 
 /**
@@ -51,15 +51,15 @@ void rt_hw_show_register (struct rt_hw_register *regs)
  */
 void rt_hw_trap_udef(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("undefined instruction\n");
-	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+    rt_kprintf("undefined instruction\n");
+    rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -73,10 +73,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
  */
 void rt_hw_trap_swi(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("software interrupt\n");
-	rt_hw_cpu_shutdown();
+    rt_kprintf("software interrupt\n");
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -89,15 +89,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
  */
 void rt_hw_trap_pabt(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("prefetch abort\n");
-	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+    rt_kprintf("prefetch abort\n");
+    rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -110,30 +110,30 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
  */
 void rt_hw_trap_dabt(struct rt_hw_register *regs)
 {
-	rt_uint32_t fault_addr;
-	rt_uint32_t fault_status;
-	asm  volatile ("mrc p15, 0, %0, c6, c0, 0"
-			:
-			:"r"(fault_addr)
-			:"cc");
-	rt_kprintf("unhandler access to 0x%08x\n", fault_addr);
+    rt_uint32_t fault_addr;
+    rt_uint32_t fault_status;
+    asm  volatile ("mrc p15, 0, %0, c6, c0, 0"
+            :
+            :"r"(fault_addr)
+            :"cc");
+    rt_kprintf("unhandler access to 0x%08x\n", fault_addr);
 
-	/* read DFSR */
-	asm volatile ("MRC p15, 0, %0, c5, c0, 0"
-			:
-			:"r"(fault_status)
-			:"cc");
-	rt_kprintf("fault status 0x%08x\n", fault_status);
+    /* read DFSR */
+    asm volatile ("MRC p15, 0, %0, c5, c0, 0"
+            :
+            :"r"(fault_status)
+            :"cc");
+    rt_kprintf("fault status 0x%08x\n", fault_status);
 
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("data abort\n");
-	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+    rt_kprintf("data abort\n");
+    rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -145,9 +145,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
  */
 void rt_hw_trap_resv(struct rt_hw_register *regs)
 {
-	rt_kprintf("not used\n");
-	rt_hw_show_register(regs);
-	rt_hw_cpu_shutdown();
+    rt_kprintf("not used\n");
+    rt_hw_show_register(regs);
+    rt_hw_cpu_shutdown();
 }
 
 extern struct rt_irq_desc irq_desc[];
@@ -155,32 +155,32 @@ extern struct rt_irq_desc irq_desc[];
 
 void rt_hw_trap_irq()
 {
-	rt_isr_handler_t isr_func;
-	rt_uint32_t val, irq, mask;
-	void *param;
+    rt_isr_handler_t isr_func;
+    rt_uint32_t val, irq, mask;
+    void *param;
 
-	/* get irq number */
-	val = readl(DAVINCI_ARM_INTC_BASE+0x14) - readl(DAVINCI_ARM_INTC_BASE+0x24);
-	irq = (val >> 2) - 1;
-	/* clear pending register */
-	mask = 1 << (irq & 0x1f);
-	if (irq > 31)
-		writel(mask, DAVINCI_ARM_INTC_BASE+0x0c); //IRQ1
-	else
-		writel(mask, DAVINCI_ARM_INTC_BASE+0x08); //IRQ0
-	
-	/* get interrupt service routine */
-	isr_func = irq_desc[irq].handler;
-	param = irq_desc[irq].param;
+    /* get irq number */
+    val = readl(DAVINCI_ARM_INTC_BASE+0x14) - readl(DAVINCI_ARM_INTC_BASE+0x24);
+    irq = (val >> 2) - 1;
+    /* clear pending register */
+    mask = 1 << (irq & 0x1f);
+    if (irq > 31)
+        writel(mask, DAVINCI_ARM_INTC_BASE+0x0c); //IRQ1
+    else
+        writel(mask, DAVINCI_ARM_INTC_BASE+0x08); //IRQ0
 
-	/* turn to interrupt service routine */
-	isr_func(irq, param);
-	irq_desc[irq].counter++;
+    /* get interrupt service routine */
+    isr_func = irq_desc[irq].handler;
+    param = irq_desc[irq].param;
+
+    /* turn to interrupt service routine */
+    isr_func(irq, param);
+    irq_desc[irq].counter++;
 }
 
 void rt_hw_trap_fiq()
 {
-	rt_kprintf("fast interrupt request\n");
+    rt_kprintf("fast interrupt request\n");
 }
 
 /*@}*/