diff options
| author | Bernard Xiong <[email protected]> | 2021-05-28 16:20:08 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2021-05-28 16:20:08 +0800 |
| commit | 92beddf3bccf6346e26aa097f82464456fb8e6bd (patch) | |
| tree | 197e4a108118dda016ea02274172f0c40e7ee8ed /bsp/m16c62p/drivers/bsp.c | |
| parent | b18a99b44240ec3152011e159cc24a5af8dff0ce (diff) | |
| parent | 03f4d40e30f3c94e1db0b3a65b3610dee695694a (diff) | |
Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5
[lts 3.1.x] format codes
Diffstat (limited to 'bsp/m16c62p/drivers/bsp.c')
| -rw-r--r-- | bsp/m16c62p/drivers/bsp.c | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/bsp/m16c62p/drivers/bsp.c b/bsp/m16c62p/drivers/bsp.c index df80d0936b..29732cb636 100644 --- a/bsp/m16c62p/drivers/bsp.c +++ b/bsp/m16c62p/drivers/bsp.c @@ -35,31 +35,31 @@ void led_off(void) static void mcu_init(void) { - volatile rt_uint32_t count; - /* Configure clock for divide by 1 mode */ - PRCR.BYTE |= 0x01; /* Enable access to clock registers PRCR.PRC0 = 1 */ - CM1.BYTE = 0x20; /* Set CM16, CM17 divide ratio to 1: */ - /* ... main clock on in high drive no PLL */ - CM0.BYTE &= ~0x40; /* Set divide ratio to 1 CM0.CM06 = 0 */ + volatile rt_uint32_t count; + /* Configure clock for divide by 1 mode */ + PRCR.BYTE |= 0x01; /* Enable access to clock registers PRCR.PRC0 = 1 */ + CM1.BYTE = 0x20; /* Set CM16, CM17 divide ratio to 1: */ + /* ... main clock on in high drive no PLL */ + CM0.BYTE &= ~0x40; /* Set divide ratio to 1 CM0.CM06 = 0 */ /* Configure main PLL */ - PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */ - PM2.BYTE |= 0x01; /* Set SFR access to 2 wait, which is required for */ - /* ... operation greater than 16 MHz PM2.PM20 = 1 */ - PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */ - PLC0.BYTE = 0x91; /* Enable and turn on PLL */ + PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */ + PM2.BYTE |= 0x01; /* Set SFR access to 2 wait, which is required for */ + /* ... operation greater than 16 MHz PM2.PM20 = 1 */ + PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */ + PLC0.BYTE = 0x91; /* Enable and turn on PLL */ count = 20000; /* Delay while PLL stabilizes */ - while (count > 0) { + while (count > 0) { count--; } CM1.BYTE |= 0x02; /* Switch to PLL CM1.CM11 = 1 */ PRCR.BYTE &= ~0x01; /* Protect clock control register PRCR.PRC0 = 0 */ - - PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */ - PM1.BYTE |= 0x01; /* Enable data flash area PM1.PM10 = 1 */ - PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */ + + PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */ + PM1.BYTE |= 0x01; /* Enable data flash area PM1.PM10 = 1 */ + PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */ } /* @@ -85,15 +85,15 @@ static void mcu_init(void) static void timer_tick_init(void) { - /* Set timer to timer mode */ + /* Set timer to timer mode */ /* Set count source as PLL clock / 8 (f8) */ - TB0MR.BYTE = 0x40; + TB0MR.BYTE = 0x40; /* Assign timer value and reload value */ - TB0 = (CPU_CLK_FREQ / 8) / RT_TICK_PER_SECOND; - /* Set timer B channel 0 interrupt level = 7 */ - /* Clear interrupt request */ + TB0 = (CPU_CLK_FREQ / 8) / RT_TICK_PER_SECOND; + /* Set timer B channel 0 interrupt level = 7 */ + /* Clear interrupt request */ TB0IC.BYTE = 0x07; - TABSR.BYTE |= 0x20; /* Start timer */ + TABSR.BYTE |= 0x20; /* Start timer */ } void system_init(void) |