Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5

[lts 3.1.x] format codes

6 files changed, 197 insertions, 197 deletions

diff --git a/bsp/m16c62p/applications/application.c b/bsp/m16c62p/applications/application.c
index 7693ef8862..35eb423193 100644
--- a/bsp/m16c62p/applications/application.c
+++ b/bsp/m16c62p/applications/application.c
@@ -44,7 +44,7 @@ int rt_application_init(void)
                             sizeof(led_stack),
                             RT_THREAD_PRIORITY_MAX / 2,
                             32);
-    
+
     if (result == RT_EOK)
         rt_thread_startup(&led);
 
diff --git a/bsp/m16c62p/applications/startup.c b/bsp/m16c62p/applications/startup.c
index 322476b60d..a3c9448201 100644
--- a/bsp/m16c62p/applications/startup.c
+++ b/bsp/m16c62p/applications/startup.c
@@ -36,67 +36,67 @@ extern unsigned char user_ram_end;
  */
 void rtthread_startup(void)
 {
-	/* init hardware interrupt */
-	rt_hw_interrupt_init();
-        
-	/* init board */
-	rt_hw_board_init();
+    /* init hardware interrupt */
+    rt_hw_interrupt_init();
 
-	/* show version */
-	rt_show_version();
+    /* init board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+
+    /* init tick */
+    rt_system_tick_init();
+
+    /* init kernel object */
+    rt_system_object_init();
+
+    /* init timer system */
+    rt_system_timer_init();
 
-	/* init tick */
-	rt_system_tick_init();
-    
-	/* init kernel object */
-	rt_system_object_init();
-    
-	/* init timer system */
-	rt_system_timer_init();
-    
 #ifdef RT_USING_HEAP
 #ifdef __ICCM16C__
-	rt_system_heap_init(__segment_begin("DATA16_HEAP"), __segment_end("DATA16_HEAP"));
+    rt_system_heap_init(__segment_begin("DATA16_HEAP"), __segment_end("DATA16_HEAP"));
 #elif (defined (__GNUC__))
-	rt_system_heap_init((void*)&user_ram_end, (void*)M16C62P_SRAM_END);
+    rt_system_heap_init((void*)&user_ram_end, (void*)M16C62P_SRAM_END);
 #endif
 #endif
 
-	/* init scheduler system */
-	rt_system_scheduler_init();
+    /* init scheduler system */
+    rt_system_scheduler_init();
 
-	/* init application */
-	rt_application_init();
+    /* init application */
+    rt_application_init();
 
 #ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-	finsh_set_device("uart0");
+    /* init finsh */
+    finsh_system_init();
+    finsh_set_device("uart0");
 #endif
 
-	/* init timer thread */
-	rt_system_timer_thread_init();
+    /* init timer thread */
+    rt_system_timer_thread_init();
 
-	/* init idle thread */
-	rt_thread_idle_init();
-    
-	/* start scheduler */
-	rt_system_scheduler_start();
-    
-	/* never reach here */
-	return ;
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
 }
 
 int main(void)
 {
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* init system setting */
+    system_init();
 
-	/* init system setting */
-	system_init();
-    
-	/* startup RT-Thread RTOS */
-	rtthread_startup();
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
 
-	return 0;
+    return 0;
 }
diff --git a/bsp/m16c62p/drivers/board.c b/bsp/m16c62p/drivers/board.c
index bf37fae8cb..9771e97fed 100644
--- a/bsp/m16c62p/drivers/board.c
+++ b/bsp/m16c62p/drivers/board.c
@@ -23,8 +23,8 @@
 void rt_hw_board_init(void)
 {
 #ifdef RT_USING_UART0
-	rt_hw_uart_init();
-	rt_console_set_device("uart0");
+    rt_hw_uart_init();
+    rt_console_set_device("uart0");
 #endif
 
     rt_kprintf("\r\n\r\nSystemInit......\r\n");
diff --git a/bsp/m16c62p/drivers/bsp.c b/bsp/m16c62p/drivers/bsp.c
index df80d0936b..29732cb636 100644
--- a/bsp/m16c62p/drivers/bsp.c
+++ b/bsp/m16c62p/drivers/bsp.c
@@ -35,31 +35,31 @@ void led_off(void)
 
 static void mcu_init(void)
 {
-	volatile  rt_uint32_t  count;
-	                                                            /* Configure clock for divide by 1 mode                     */
-	PRCR.BYTE      |= 0x01;                                     /* Enable access to clock registers           PRCR.PRC0 = 1 */
-	CM1.BYTE             = 0x20;                                     /* Set CM16, CM17 divide ratio to 1:                        */
-									                            /*  ... main clock on in high drive no PLL                  */
-	CM0.BYTE            &= ~0x40;                                    /* Set divide ratio to 1                      CM0.CM06  = 0 */			
+    volatile  rt_uint32_t  count;
+                                                                /* Configure clock for divide by 1 mode                     */
+    PRCR.BYTE      |= 0x01;                                     /* Enable access to clock registers           PRCR.PRC0 = 1 */
+    CM1.BYTE             = 0x20;                                     /* Set CM16, CM17 divide ratio to 1:                        */
+                                                                /*  ... main clock on in high drive no PLL                  */
+    CM0.BYTE            &= ~0x40;                                    /* Set divide ratio to 1                      CM0.CM06  = 0 */
 
                                                                 /* Configure main PLL                                       */
-	PRCR.BYTE           |= 0x02;                                     /* Allow writing to processor mode register   PRCR.PRC0 = 1 */
-	PM2.BYTE            |= 0x01;                                     /* Set SFR access to 2 wait, which is required for          */
-   									                            /*  ... operation greater than 16 MHz         PM2.PM20  = 1 */
-	PRCR.BYTE           &= ~0x02;                                    /* Protect processor mode register            PRCR.PRC0 = 0 */
-	PLC0.BYTE            = 0x91;                                     /* Enable and turn on PLL                                   */
+    PRCR.BYTE           |= 0x02;                                     /* Allow writing to processor mode register   PRCR.PRC0 = 1 */
+    PM2.BYTE            |= 0x01;                                     /* Set SFR access to 2 wait, which is required for          */
+                                                                /*  ... operation greater than 16 MHz         PM2.PM20  = 1 */
+    PRCR.BYTE           &= ~0x02;                                    /* Protect processor mode register            PRCR.PRC0 = 0 */
+    PLC0.BYTE            = 0x91;                                     /* Enable and turn on PLL                                   */
 
     count           = 20000;                                    /* Delay while PLL stabilizes                               */
-	while (count > 0) {
+    while (count > 0) {
         count--;
     }
 
     CM1.BYTE            |= 0x02;                                     /* Switch to PLL                              CM1.CM11  = 1 */
     PRCR.BYTE           &= ~0x01;                                    /* Protect clock control register             PRCR.PRC0 = 0 */
-	
-	PRCR.BYTE           |= 0x02;                                     /* Allow writing to processor mode register   PRCR.PRC0 = 1 */
-	PM1.BYTE            |= 0x01;                                     /* Enable data flash area                     PM1.PM10  = 1 */
-	PRCR.BYTE           &= ~0x02;                                    /* Protect processor mode register            PRCR.PRC0 = 0 */
+
+    PRCR.BYTE           |= 0x02;                                     /* Allow writing to processor mode register   PRCR.PRC0 = 1 */
+    PM1.BYTE            |= 0x01;                                     /* Enable data flash area                     PM1.PM10  = 1 */
+    PRCR.BYTE           &= ~0x02;                                    /* Protect processor mode register            PRCR.PRC0 = 0 */
 }
 
 /*
@@ -85,15 +85,15 @@ static void mcu_init(void)
 
 static void timer_tick_init(void)
 {
-	                                                            /* Set timer to timer mode                                  */
+                                                                /* Set timer to timer mode                                  */
                                                                 /* Set count source as PLL clock / 8 (f8)                   */
-	TB0MR.BYTE = 0x40;
+    TB0MR.BYTE = 0x40;
                                                                 /* Assign timer value and reload value                      */
-	TB0        = (CPU_CLK_FREQ / 8) / RT_TICK_PER_SECOND;
-	                                                            /* Set timer B channel 0 interrupt level = 7                */
-	                                                            /* Clear interrupt request                                  */
+    TB0        = (CPU_CLK_FREQ / 8) / RT_TICK_PER_SECOND;
+                                                                /* Set timer B channel 0 interrupt level = 7                */
+                                                                /* Clear interrupt request                                  */
     TB0IC.BYTE = 0x07;
-	TABSR.BYTE |= 0x20;                             /* Start timer                                              */
+    TABSR.BYTE |= 0x20;                             /* Start timer                                              */
 }
 
 void system_init(void)
diff --git a/bsp/m16c62p/drivers/uart.c b/bsp/m16c62p/drivers/uart.c
index 62e2a6b885..67f56b98a3 100644
--- a/bsp/m16c62p/drivers/uart.c
+++ b/bsp/m16c62p/drivers/uart.c
@@ -19,44 +19,44 @@
 
 struct rt_uart_m16c
 {
-	struct rt_device parent;
+    struct rt_device parent;
 
-	/* buffer for reception */
-	rt_uint8_t read_index, save_index;
-	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
+    /* buffer for reception */
+    rt_uint8_t read_index, save_index;
+    rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
 }uart_device;
 
 void u0rec_handler(void)
 {
-	rt_ubase_t level;
-	rt_uint8_t c;
+    rt_ubase_t level;
+    rt_uint8_t c;
 
-	struct rt_uart_m16c *uart = &uart_device;
+    struct rt_uart_m16c *uart = &uart_device;
 
-	while (U0C1.BIT.RI == 0)
-		;
-	c = U0RB.BYTE.U0RBL;
+    while (U0C1.BIT.RI == 0)
+        ;
+    c = U0RB.BYTE.U0RBL;
 
-	/* Receive Data Available */
+    /* Receive Data Available */
     uart->rx_buffer[uart->save_index] = c;
 
     level = rt_hw_interrupt_disable();
-	uart->save_index ++;
+    uart->save_index ++;
     if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
         uart->save_index = 0;
     rt_hw_interrupt_enable(level);
 
-	/* invoke callback */
-	if (uart->parent.rx_indicate != RT_NULL)
-	{
-	    rt_size_t length;
-	    if (uart->read_index > uart->save_index)
+    /* invoke callback */
+    if (uart->parent.rx_indicate != RT_NULL)
+    {
+        rt_size_t length;
+        if (uart->read_index > uart->save_index)
             length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
         else
             length = uart->save_index - uart->read_index;
 
         uart->parent.rx_indicate(&uart->parent, length);
-	}
+    }
 }
 
 static rt_err_t rt_uart_init (rt_device_t dev)
@@ -65,7 +65,7 @@ static rt_err_t rt_uart_init (rt_device_t dev)
     /* set UART0 bit rate generator bit rate can be calculated by:
           bit rate = ((BRG count source / 16)/baud rate) - 1
           Baud rate is based on main crystal or PLL not CPU core clock */
-	//pclk1 = 1;   /// seleck F1SIO
+    //pclk1 = 1;   /// seleck F1SIO
     U0BRG = (unsigned char)(((CPU_CLK_FREQ/16)/BAUD_RATE)-1);   //(N+1)
 
     /* UART Transmit/Receive Control Register 2 */
@@ -139,144 +139,144 @@ static rt_err_t rt_uart_init (rt_device_t dev)
         b6      UOLCH       Data logic select bit
         b7      UOERE       Error signal output enable bit */
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	RT_ASSERT(dev != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Enable the UART Interrupt */
-	}
+    RT_ASSERT(dev != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* Enable the UART Interrupt */
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_uart_close(rt_device_t dev)
 {
-	RT_ASSERT(dev != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Disable the UART Interrupt */
-	}
+    RT_ASSERT(dev != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* Disable the UART Interrupt */
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_uint8_t *ptr;
-	struct rt_uart_m16c *uart = (struct rt_uart_m16c *)dev;
-	RT_ASSERT(uart != RT_NULL);
+    rt_uint8_t *ptr;
+    struct rt_uart_m16c *uart = (struct rt_uart_m16c *)dev;
+    RT_ASSERT(uart != RT_NULL);
 
-	/* point to buffer */
-	ptr = (rt_uint8_t *)buffer;
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
+    /* point to buffer */
+    ptr = (rt_uint8_t *)buffer;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        while (size)
+        {
+            /* interrupt receive */
+            rt_base_t level;
 
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (uart->read_index != uart->save_index)
-			{
-				*ptr = uart->rx_buffer[uart->read_index];
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
+            if (uart->read_index != uart->save_index)
+            {
+                *ptr = uart->rx_buffer[uart->read_index];
 
-				uart->read_index ++;
-				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
-					uart->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
+                uart->read_index ++;
+                if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    uart->read_index = 0;
+            }
+            else
+            {
+                /* no data in rx buffer */
 
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+                break;
+            }
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
 
-			ptr ++;
-			size --;
-		}
+            ptr ++;
+            size --;
+        }
 
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
+        return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    }
 
-	return 0;
+    return 0;
 }
 
 static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
 {
-	char *ptr;
-	ptr = (char *)buffer;
+    char *ptr;
+    ptr = (char *)buffer;
 
-	if (dev->flag & RT_DEVICE_FLAG_STREAM)
-	{
-		/* stream mode */
-		while (size)
-		{
-			if (*ptr == '\n')
-			{
-				while (U0C1.BIT.TI == 0)
-					;
-				U0TB.BYTE.U0TBL = '\r';
-			}
+    if (dev->flag & RT_DEVICE_FLAG_STREAM)
+    {
+        /* stream mode */
+        while (size)
+        {
+            if (*ptr == '\n')
+            {
+                while (U0C1.BIT.TI == 0)
+                    ;
+                U0TB.BYTE.U0TBL = '\r';
+            }
 
-			/* THRE status, contain valid data */
-			while (U0C1.BIT.TI == 0)
-				;
-			U0TB.BYTE.U0TBL = *ptr;
-  
-			ptr ++;
-			size --;
-		}
-	}
-	else
-	{
-		while (size != 0)
-		{
-			/* THRE status, contain valid data */
-			while (U0C1.BIT.TI == 0)
-				;
-			U0TB.BYTE.U0TBL = *ptr;
-	
-			ptr ++;
-			size --;
-		}
-	}
+            /* THRE status, contain valid data */
+            while (U0C1.BIT.TI == 0)
+                ;
+            U0TB.BYTE.U0TBL = *ptr;
 
-	return (rt_size_t)ptr - (rt_size_t)buffer;
+            ptr ++;
+            size --;
+        }
+    }
+    else
+    {
+        while (size != 0)
+        {
+            /* THRE status, contain valid data */
+            while (U0C1.BIT.TI == 0)
+                ;
+            U0TB.BYTE.U0TBL = *ptr;
+
+            ptr ++;
+            size --;
+        }
+    }
+
+    return (rt_size_t)ptr - (rt_size_t)buffer;
 }
 
 void rt_hw_uart_init(void)
 {
-	struct rt_uart_m16c *uart;
+    struct rt_uart_m16c *uart;
 
-	/* get uart device */
-	uart = &uart_device;
+    /* get uart device */
+    uart = &uart_device;
 
-	/* device initialization */
-	uart->parent.type = RT_Device_Class_Char;
-	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
-	uart->read_index = uart->save_index = 0;
+    /* device initialization */
+    uart->parent.type = RT_Device_Class_Char;
+    rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
+    uart->read_index = uart->save_index = 0;
 
-	/* device interface */
-	uart->parent.init 	    = rt_uart_init;
-	uart->parent.open 	    = rt_uart_open;
-	uart->parent.close      = rt_uart_close;
-	uart->parent.read 	    = rt_uart_read;
-	uart->parent.write      = rt_uart_write;
-	uart->parent.control    = RT_NULL;
-	uart->parent.user_data  = RT_NULL;
+    /* device interface */
+    uart->parent.init       = rt_uart_init;
+    uart->parent.open       = rt_uart_open;
+    uart->parent.close      = rt_uart_close;
+    uart->parent.read       = rt_uart_read;
+    uart->parent.write      = rt_uart_write;
+    uart->parent.control    = RT_NULL;
+    uart->parent.user_data  = RT_NULL;
 
-	rt_device_register(&uart->parent,
-		"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
+    rt_device_register(&uart->parent,
+        "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
 }
 #endif /* end of UART */
 
diff --git a/bsp/m16c62p/rtconfig.h b/bsp/m16c62p/rtconfig.h
index adcf67e748..1b3d1cda12 100644
--- a/bsp/m16c62p/rtconfig.h
+++ b/bsp/m16c62p/rtconfig.h
@@ -3,16 +3,16 @@
 #define __RTTHREAD_CFG_H__
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX	8
+#define RT_NAME_MAX 8
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 
 /* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX  32
 
 /* Tick per Second */
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 
 /* SECTION: RT_DEBUG */
 /* Thread Debug */
@@ -27,9 +27,9 @@
 
 /* Using Software Timer */
 /* #define RT_USING_TIMER_SOFT */
-#define RT_TIMER_THREAD_PRIO		4
-#define RT_TIMER_THREAD_STACK_SIZE	512
-#define RT_TIMER_TICK_PER_SECOND	10
+#define RT_TIMER_THREAD_PRIO        4
+#define RT_TIMER_THREAD_STACK_SIZE  512
+#define RT_TIMER_TICK_PER_SECOND    10
 
 /* SECTION: IPC */
 /* Using Semaphore */
@@ -62,12 +62,12 @@
 #define RT_USING_DEVICE
 /* RT_USING_UART */
 #define RT_USING_UART0
-#define RT_UART_RX_BUFFER_SIZE	64
+#define RT_UART_RX_BUFFER_SIZE  64
 
 /* SECTION: Console options */
 #define RT_USING_CONSOLE
 /* the buffer size of console */
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 
 /* SECTION: finsh, a C-Express shell */
 /* Using FinSH as Shell*/