Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5

[lts 3.1.x] format codes

7 files changed, 311 insertions, 311 deletions

diff --git a/libcpu/mips/loongson_1b/cache.c b/libcpu/mips/loongson_1b/cache.c
index 842f392cb7..ccfdda95d3 100644
--- a/libcpu/mips/loongson_1b/cache.c
+++ b/libcpu/mips/loongson_1b/cache.c
@@ -12,12 +12,12 @@
  * 2010-07-09     Bernard      first version
  * 2011-08-08     lgnq         modified for LS1B
  */
- 
+
 #include <rtthread.h>
 #include "../common/mipsregs.h"
 
-#define K0BASE			0x80000000
-#define PRID_LS1B		0x4220
+#define K0BASE          0x80000000
+#define PRID_LS1B       0x4220
 
 extern void Clear_TagLo (void);
 extern void Invalidate_Icache_Ls1b(unsigned int);
@@ -26,21 +26,21 @@ extern void Invalidate_Dcache_Fill_Ls1b(unsigned int);
 extern void Writeback_Invalidate_Dcache(unsigned int);
 extern void enable_cpu_cache(void);
 
-typedef struct cacheinfo_t 
+typedef struct cacheinfo_t
 {
-	unsigned int	icache_size;
-	unsigned int	dcache_size;
-	unsigned int	icacheline_size;
-	unsigned int	dcacheline_size;
+    unsigned int    icache_size;
+    unsigned int    dcache_size;
+    unsigned int    icacheline_size;
+    unsigned int    dcacheline_size;
 } cacheinfo_t ;
 
-typedef struct cacheop_t 
+typedef struct cacheop_t
 {
-	void (*Clear_TagLo) (void);
-	void (*Invalidate_Icache) (unsigned int);
-	void (*Invalidate_Dcache_Fill) (unsigned int);
-	void (*Invalidate_Dcache_ClearTag) (unsigned int);
-	void (*Init_Cache)(void);
+    void (*Clear_TagLo) (void);
+    void (*Invalidate_Icache) (unsigned int);
+    void (*Invalidate_Dcache_Fill) (unsigned int);
+    void (*Invalidate_Dcache_ClearTag) (unsigned int);
+    void (*Init_Cache)(void);
 } cacheop_t ;
 
 static cacheop_t cacheop, *pcacheop;
@@ -53,24 +53,24 @@ int identify_cpu(void)
     pcacheop = &cacheop;
     pcacheinfo = &cacheinfo;
 
-	rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
+    rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
     cpu_id = read_c0_prid();
     switch (cpu_id)
-	{
-	case PRID_LS1B:       
-	    rt_kprintf("CPU:LS1B\n");
-	    pcacheop->Clear_TagLo = Clear_TagLo;
-	    pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b;
-	    pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b;
-	    pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b;
-	    break;
-	default:
-	    rt_kprintf("Unknown CPU type, system halted!\n");
-	    while (1) 
-	    {
-	    	;
-	    }
-	    break;
+    {
+    case PRID_LS1B:
+        rt_kprintf("CPU:LS1B\n");
+        pcacheop->Clear_TagLo = Clear_TagLo;
+        pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b;
+        pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b;
+        pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b;
+        break;
+    default:
+        rt_kprintf("Unknown CPU type, system halted!\n");
+        while (1)
+        {
+            ;
+        }
+        break;
     }
 
     return 0;
@@ -89,7 +89,7 @@ void probe_cache(void)
     icache_sets = 64 << ((config1 >> 22) & 7);
     icache_ways = 1 + ((config1 >> 16) & 7);
     icache_size = icache_sets * icache_ways * icache_line_size;
-    
+
     if ((dcache_line_size = ((config1 >> 10) & 7)))
         dcache_line_size = 2 << dcache_line_size;
     else
@@ -97,7 +97,7 @@ void probe_cache(void)
     dcache_sets = 64 << ((config1 >> 13) & 7);
     dcache_ways = 1 + ((config1 >> 7) & 7);
     dcache_size = dcache_sets * dcache_ways * dcache_line_size;
-    
+
     rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
     rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
 
@@ -111,120 +111,120 @@ void probe_cache(void)
 
 void invalidate_writeback_dcache_all(void)
 {
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->dcache_size);
+    unsigned int start = K0BASE;
+    unsigned int end = (start + pcacheinfo->dcache_size);
 
-	while (start < end) 
-	{
-		Writeback_Invalidate_Dcache(start);  //hit writeback invalidate 
-		start += pcacheinfo->dcacheline_size;
-	}
+    while (start < end)
+    {
+        Writeback_Invalidate_Dcache(start);  //hit writeback invalidate
+        start += pcacheinfo->dcacheline_size;
+    }
 }
 
 void invalidate_writeback_dcache(unsigned long addr, int size)
 {
-	unsigned long start, end;
-			
-	start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
-	end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
-	
-	while (start <end)
-	{
-		Writeback_Invalidate_Dcache(start);
-		start += pcacheinfo->dcacheline_size;
-	}		
+    unsigned long start, end;
+
+    start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
+    end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
+
+    while (start <end)
+    {
+        Writeback_Invalidate_Dcache(start);
+        start += pcacheinfo->dcacheline_size;
+    }
 }
 
 void invalidate_icache_all(void)
 {
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->icache_size);
+    unsigned int start = K0BASE;
+    unsigned int end = (start + pcacheinfo->icache_size);
 
-	while (start < end) 
-	{
-		pcacheop->Invalidate_Icache(start); 
-		start += pcacheinfo->icacheline_size;
-	}
+    while (start < end)
+    {
+        pcacheop->Invalidate_Icache(start);
+        start += pcacheinfo->icacheline_size;
+    }
 }
 
 void invalidate_dcache_all(void)
-{ 
-	unsigned int start = K0BASE;
-	unsigned int end  = (start + pcacheinfo->dcache_size);
-	while (start <end)
-	{
-		Invalidate_Dcache_Fill_Ls1b(start);
-		start += pcacheinfo->icacheline_size;
-	}
+{
+    unsigned int start = K0BASE;
+    unsigned int end  = (start + pcacheinfo->dcache_size);
+    while (start <end)
+    {
+        Invalidate_Dcache_Fill_Ls1b(start);
+        start += pcacheinfo->icacheline_size;
+    }
 }
 
 //with cache disabled
 void init_dcache(void)
 {
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->dcache_size);
+    unsigned int start = K0BASE;
+    unsigned int end = (start + pcacheinfo->dcache_size);
 
-	while (start < end)
-	{
-		pcacheop->Invalidate_Dcache_ClearTag(start);
-		start += pcacheinfo->dcacheline_size;
-	}
+    while (start < end)
+    {
+        pcacheop->Invalidate_Dcache_ClearTag(start);
+        start += pcacheinfo->dcacheline_size;
+    }
 
 }
 
 void rt_hw_cache_init(void)
 {
     unsigned int start, end;
-	
-	/* 1. identify cpu and probe cache */
-	identify_cpu();
-	probe_cache();
 
-	start = K0BASE;
-	end = (start + pcacheinfo->icache_size);
+    /* 1. identify cpu and probe cache */
+    identify_cpu();
+    probe_cache();
+
+    start = K0BASE;
+    end = (start + pcacheinfo->icache_size);
 
     /*
-     *	2. clear CP0 taglo/taghi register;
+     *  2. clear CP0 taglo/taghi register;
      */
     pcacheop->Clear_TagLo();
 
-	/*
-     *	3. invalidate instruction cache;
+    /*
+     *  3. invalidate instruction cache;
      */
-    while (start < end) 
+    while (start < end)
     {
-		pcacheop->Invalidate_Icache(start); //index invalidate icache 
-		start += pcacheinfo->icacheline_size;
+        pcacheop->Invalidate_Icache(start); //index invalidate icache
+        start += pcacheinfo->icacheline_size;
     }
 
     /*
-     *	4. invalidate data cache;
+     *  4. invalidate data cache;
      */
     start = K0BASE;
     end = (start + pcacheinfo->dcache_size);
-    while(start < end) 
+    while(start < end)
     {
-		pcacheop->Invalidate_Dcache_ClearTag(start); 
-		start += pcacheinfo->dcacheline_size;
+        pcacheop->Invalidate_Dcache_ClearTag(start);
+        start += pcacheinfo->dcacheline_size;
     }
 
     start = K0BASE;
-    while(start < end) 
+    while(start < end)
     {
-		pcacheop->Invalidate_Dcache_Fill(start);  //index invalidate dcache
-		start += pcacheinfo->dcacheline_size;
+        pcacheop->Invalidate_Dcache_Fill(start);  //index invalidate dcache
+        start += pcacheinfo->dcacheline_size;
     }
 
     start = K0BASE;
-    while(start < end) 
+    while(start < end)
     {
-		pcacheop->Invalidate_Dcache_ClearTag(start); 
-		start += pcacheinfo->dcacheline_size;
+        pcacheop->Invalidate_Dcache_ClearTag(start);
+        start += pcacheinfo->dcacheline_size;
     }
 
-	/* enable cache */
-	enable_cpu_cache();
-	rt_kprintf("enable cpu cache done\n");
+    /* enable cache */
+    enable_cpu_cache();
+    rt_kprintf("enable cpu cache done\n");
 
-	return ;
+    return ;
 }
diff --git a/libcpu/mips/loongson_1b/cache.h b/libcpu/mips/loongson_1b/cache.h
index b5c2d4501e..8ca015ef4f 100644
--- a/libcpu/mips/loongson_1b/cache.h
+++ b/libcpu/mips/loongson_1b/cache.h
@@ -12,8 +12,8 @@
  * 2010-07-09     Bernard      first version
  * 2011-08-08     lgnq         modified for LS1B
  */
-#ifndef	__CACHE_H__
-#define	__CACHE_H__
+#ifndef __CACHE_H__
+#define __CACHE_H__
 
 /*
  * Cache Operations
@@ -22,31 +22,31 @@
 #define Index_Writeback_Inv_D   0x01
 #define Index_Invalidate_SI     0x02
 #define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_I		0x04
-#define Index_Load_Tag_D		0x05
-#define Index_Load_Tag_SI		0x06
-#define Index_Load_Tag_SD		0x07
-#define Index_Store_Tag_I		0x08
-#define Index_Store_Tag_D		0x09
-#define Index_Store_Tag_SI		0x0A
-#define Index_Store_Tag_SD		0x0B
-#define Create_Dirty_Excl_D		0x0d
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_I		0x10
-#define Hit_Invalidate_D		0x11
-#define Hit_Invalidate_SI		0x12
-#define Hit_Invalidate_SD		0x13
-#define Fill					0x14
-#define Hit_Writeback_Inv_D		0x15
+#define Index_Load_Tag_I        0x04
+#define Index_Load_Tag_D        0x05
+#define Index_Load_Tag_SI       0x06
+#define Index_Load_Tag_SD       0x07
+#define Index_Store_Tag_I       0x08
+#define Index_Store_Tag_D       0x09
+#define Index_Store_Tag_SI      0x0A
+#define Index_Store_Tag_SD      0x0B
+#define Create_Dirty_Excl_D     0x0d
+#define Create_Dirty_Excl_SD    0x0f
+#define Hit_Invalidate_I        0x10
+#define Hit_Invalidate_D        0x11
+#define Hit_Invalidate_SI       0x12
+#define Hit_Invalidate_SD       0x13
+#define Fill                    0x14
+#define Hit_Writeback_Inv_D     0x15
 /* 0x16 is unused */
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_I			0x18
-#define Hit_Writeback_D			0x19
+#define Hit_Writeback_Inv_SD    0x17
+#define Hit_Writeback_I         0x18
+#define Hit_Writeback_D         0x19
 /* 0x1a is unused */
-#define Hit_Writeback_SD		0x1b
+#define Hit_Writeback_SD        0x1b
 /* 0x1c is unused */
 /* 0x1e is unused */
-#define Hit_Set_Virtual_SI		0x1e
-#define Hit_Set_Virtual_SD		0x1f
+#define Hit_Set_Virtual_SI      0x1e
+#define Hit_Set_Virtual_SD      0x1f
 
 #endif
diff --git a/libcpu/mips/loongson_1b/cpuport.c b/libcpu/mips/loongson_1b/cpuport.c
index c095c04814..23399800f5 100644
--- a/libcpu/mips/loongson_1b/cpuport.c
+++ b/libcpu/mips/loongson_1b/cpuport.c
@@ -28,13 +28,13 @@
  */
 void rt_hw_cpu_reset(void)
 {
-	/* open the watch-dog */
-	WDT_EN = 0x01; 		/* watch dog enable */
-	WDT_TIMER = 0x01;	/* watch dog will be timeout after 1 tick */
-	WDT_SET = 0x01;		/* watch dog start */
+    /* open the watch-dog */
+    WDT_EN = 0x01;      /* watch dog enable */
+    WDT_TIMER = 0x01;   /* watch dog will be timeout after 1 tick */
+    WDT_SET = 0x01;     /* watch dog start */
 
-	rt_kprintf("reboot system...\n");
-	while (1);
+    rt_kprintf("reboot system...\n");
+    while (1);
 }
 
 /**
@@ -43,9 +43,9 @@ void rt_hw_cpu_reset(void)
  */
 void rt_hw_cpu_shutdown(void)
 {
-	rt_kprintf("shutdown...\n");
+    rt_kprintf("shutdown...\n");
 
-	while (1);
+    while (1);
 }
 
 extern rt_uint32_t cp0_get_cause(void);
@@ -65,59 +65,59 @@ extern rt_uint32_t cp0_get_lo(void);
  */
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
 {
-	rt_uint32_t *stk;
+    rt_uint32_t *stk;
     static rt_uint32_t g_sr = 0;
 
     if (g_sr == 0)
     {
-    	g_sr = cp0_get_status();
-    	g_sr &= 0xfffffffe;
-    	g_sr |= 0x8401;
+        g_sr = cp0_get_status();
+        g_sr &= 0xfffffffe;
+        g_sr |= 0x8401;
     }
 
     /** Start at stack top */
     stk = (rt_uint32_t *)stack_addr;
-	*(stk)   = (rt_uint32_t) tentry;        /* pc: Entry Point */
-	*(--stk) = (rt_uint32_t) 0xeeee; 		/* c0_cause */
-	*(--stk) = (rt_uint32_t) 0xffff;		/* c0_badvaddr */
-	*(--stk) = (rt_uint32_t) cp0_get_lo();	/* lo */
-	*(--stk) = (rt_uint32_t) cp0_get_hi();	/* hi */
-	*(--stk) = (rt_uint32_t) g_sr; 			/* C0_SR: HW2 = En, IE = En */
-	*(--stk) = (rt_uint32_t) texit;	        /* ra */
-	*(--stk) = (rt_uint32_t) 0x0000001e;	/* s8 */
-	*(--stk) = (rt_uint32_t) stack_addr;	/* sp */
-	*(--stk) = (rt_uint32_t) 0x0000001c;	/* gp */
-	*(--stk) = (rt_uint32_t) 0x0000001b;	/* k1 */
-	*(--stk) = (rt_uint32_t) 0x0000001a;	/* k0 */
-	*(--stk) = (rt_uint32_t) 0x00000019;	/* t9 */
-	*(--stk) = (rt_uint32_t) 0x00000018;	/* t8 */
-	*(--stk) = (rt_uint32_t) 0x00000017;	/* s7 */
-	*(--stk) = (rt_uint32_t) 0x00000016;	/* s6 */
-	*(--stk) = (rt_uint32_t) 0x00000015;	/* s5 */
-	*(--stk) = (rt_uint32_t) 0x00000014;	/* s4 */
-	*(--stk) = (rt_uint32_t) 0x00000013;	/* s3 */
-	*(--stk) = (rt_uint32_t) 0x00000012;	/* s2 */
-	*(--stk) = (rt_uint32_t) 0x00000011;	/* s1 */
-	*(--stk) = (rt_uint32_t) 0x00000010;	/* s0 */
-	*(--stk) = (rt_uint32_t) 0x0000000f;	/* t7 */
-	*(--stk) = (rt_uint32_t) 0x0000000e;	/* t6 */
-	*(--stk) = (rt_uint32_t) 0x0000000d;	/* t5 */
-	*(--stk) = (rt_uint32_t) 0x0000000c;	/* t4 */
-	*(--stk) = (rt_uint32_t) 0x0000000b;	/* t3 */
-	*(--stk) = (rt_uint32_t) 0x0000000a; 	/* t2 */
-	*(--stk) = (rt_uint32_t) 0x00000009;	/* t1 */
-	*(--stk) = (rt_uint32_t) 0x00000008;	/* t0 */
-	*(--stk) = (rt_uint32_t) 0x00000007;	/* a3 */
-	*(--stk) = (rt_uint32_t) 0x00000006;	/* a2 */
-	*(--stk) = (rt_uint32_t) 0x00000005;	/* a1 */
-	*(--stk) = (rt_uint32_t) parameter;	    /* a0 */
-	*(--stk) = (rt_uint32_t) 0x00000003;	/* v1 */
-	*(--stk) = (rt_uint32_t) 0x00000002;	/* v0 */
-	*(--stk) = (rt_uint32_t) 0x00000001;	/* at */
-	*(--stk) = (rt_uint32_t) 0x00000000;	/* zero */
+    *(stk)   = (rt_uint32_t) tentry;        /* pc: Entry Point */
+    *(--stk) = (rt_uint32_t) 0xeeee;        /* c0_cause */
+    *(--stk) = (rt_uint32_t) 0xffff;        /* c0_badvaddr */
+    *(--stk) = (rt_uint32_t) cp0_get_lo();  /* lo */
+    *(--stk) = (rt_uint32_t) cp0_get_hi();  /* hi */
+    *(--stk) = (rt_uint32_t) g_sr;          /* C0_SR: HW2 = En, IE = En */
+    *(--stk) = (rt_uint32_t) texit;         /* ra */
+    *(--stk) = (rt_uint32_t) 0x0000001e;    /* s8 */
+    *(--stk) = (rt_uint32_t) stack_addr;    /* sp */
+    *(--stk) = (rt_uint32_t) 0x0000001c;    /* gp */
+    *(--stk) = (rt_uint32_t) 0x0000001b;    /* k1 */
+    *(--stk) = (rt_uint32_t) 0x0000001a;    /* k0 */
+    *(--stk) = (rt_uint32_t) 0x00000019;    /* t9 */
+    *(--stk) = (rt_uint32_t) 0x00000018;    /* t8 */
+    *(--stk) = (rt_uint32_t) 0x00000017;    /* s7 */
+    *(--stk) = (rt_uint32_t) 0x00000016;    /* s6 */
+    *(--stk) = (rt_uint32_t) 0x00000015;    /* s5 */
+    *(--stk) = (rt_uint32_t) 0x00000014;    /* s4 */
+    *(--stk) = (rt_uint32_t) 0x00000013;    /* s3 */
+    *(--stk) = (rt_uint32_t) 0x00000012;    /* s2 */
+    *(--stk) = (rt_uint32_t) 0x00000011;    /* s1 */
+    *(--stk) = (rt_uint32_t) 0x00000010;    /* s0 */
+    *(--stk) = (rt_uint32_t) 0x0000000f;    /* t7 */
+    *(--stk) = (rt_uint32_t) 0x0000000e;    /* t6 */
+    *(--stk) = (rt_uint32_t) 0x0000000d;    /* t5 */
+    *(--stk) = (rt_uint32_t) 0x0000000c;    /* t4 */
+    *(--stk) = (rt_uint32_t) 0x0000000b;    /* t3 */
+    *(--stk) = (rt_uint32_t) 0x0000000a;    /* t2 */
+    *(--stk) = (rt_uint32_t) 0x00000009;    /* t1 */
+    *(--stk) = (rt_uint32_t) 0x00000008;    /* t0 */
+    *(--stk) = (rt_uint32_t) 0x00000007;    /* a3 */
+    *(--stk) = (rt_uint32_t) 0x00000006;    /* a2 */
+    *(--stk) = (rt_uint32_t) 0x00000005;    /* a1 */
+    *(--stk) = (rt_uint32_t) parameter;     /* a0 */
+    *(--stk) = (rt_uint32_t) 0x00000003;    /* v1 */
+    *(--stk) = (rt_uint32_t) 0x00000002;    /* v0 */
+    *(--stk) = (rt_uint32_t) 0x00000001;    /* at */
+    *(--stk) = (rt_uint32_t) 0x00000000;    /* zero */
 
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
 }
 
 /*@}*/
diff --git a/libcpu/mips/loongson_1b/exception.c b/libcpu/mips/loongson_1b/exception.c
index 4a3745cbc5..dbcec42ab6 100644
--- a/libcpu/mips/loongson_1b/exception.c
+++ b/libcpu/mips/loongson_1b/exception.c
@@ -25,7 +25,7 @@
 /**
  * exception handle table
  */
-#define RT_EXCEPTION_MAX	8
+#define RT_EXCEPTION_MAX    8
 exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
 
 /**
@@ -47,45 +47,45 @@ exception_func_t rt_set_except_vector(int n, exception_func_t func)
 
 void tlb_refill_handler(void)
 {
-	rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
+    rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
+    rt_hw_cpu_shutdown();
 }
 
 void cache_error_handler(void)
 {
-	rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
+    rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
+    rt_hw_cpu_shutdown();
 }
 
 static void unhandled_exception_handle(pt_regs_t *regs)
 {
-	rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
+    rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
 }
 
 void install_default_execpt_handle(void)
 {
-	rt_int32_t i;
+    rt_int32_t i;
 
-	for (i=0; i<RT_EXCEPTION_MAX; i++)
-		sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
+    for (i=0; i<RT_EXCEPTION_MAX; i++)
+        sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
 }
 
 void exception_handler(pt_regs_t *regs)
 {
-	rt_uint32_t cause;
-	rt_uint32_t index;
+    rt_uint32_t cause;
+    rt_uint32_t index;
 
-	cause = (read_c0_cause() & read_c0_config());
-	cause = (cause & 0xfc00) >> 8;
+    cause = (read_c0_cause() & read_c0_config());
+    cause = (cause & 0xfc00) >> 8;
 
-	for (index = RT_EXCEPTION_MAX; index > 0; index --)
-	{
-		if (cause & (1 << index))
-		{
-			sys_exception_handlers[index](regs);
-			cause &= ~(1 << index);
-		}
-	}
+    for (index = RT_EXCEPTION_MAX; index > 0; index --)
+    {
+        if (cause & (1 << index))
+        {
+            sys_exception_handlers[index](regs);
+            cause &= ~(1 << index);
+        }
+    }
 }
 
 /*@}*/
diff --git a/libcpu/mips/loongson_1b/interrupt.c b/libcpu/mips/loongson_1b/interrupt.c
index 998d1e4918..4af9319c55 100644
--- a/libcpu/mips/loongson_1b/interrupt.c
+++ b/libcpu/mips/loongson_1b/interrupt.c
@@ -51,7 +51,7 @@ void rt_hw_interrupt_init(void)
     rt_int32_t idx;
 
     /* pci active low */
-    ls1b_hw0_icregs->int_pol = -1;	   //must be done here 20110802 lgnq
+    ls1b_hw0_icregs->int_pol = -1;     //must be done here 20110802 lgnq
     /* make all interrupts level triggered */
     (ls1b_hw0_icregs+0)->int_edge = 0x0000e000;
     /* mask all interrupts */
diff --git a/libcpu/mips/loongson_1b/ls1b.h b/libcpu/mips/loongson_1b/ls1b.h
index 34393a3448..3dab7f9da2 100644
--- a/libcpu/mips/loongson_1b/ls1b.h
+++ b/libcpu/mips/loongson_1b/ls1b.h
@@ -1,7 +1,7 @@
 /*
  * File      : ls1b.h
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
+ * COPYRIGHT (C) 2006-2021, RT-Thread Develop Team
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
@@ -17,35 +17,35 @@
 
 #include "../common/mipsregs.h"
 
-#define LS1B_ACPI_IRQ	0
-#define LS1B_HPET_IRQ	1
-#define LS1B_UART0_IRQ	2
-#define LS1B_UART1_IRQ	3
-#define LS1B_UART2_IRQ	4
-#define LS1B_UART3_IRQ	5
-#define LS1B_CAN0_IRQ	6
-#define LS1B_CAN1_IRQ	7
-#define LS1B_SPI0_IRQ	8
-#define LS1B_SPI1_IRQ	9
-#define LS1B_AC97_IRQ	10
-#define LS1B_MS_IRQ		11
-#define LS1B_KB_IRQ		12
-#define LS1B_DMA0_IRQ	13
-#define LS1B_DMA1_IRQ	14
-#define LS1B_NAND_IRQ	15
-#define LS1B_I2C0_IRQ	16
-#define LS1B_I2C1_IRQ	17
-#define LS1B_PWM0_IRQ	18
-#define LS1B_PWM1_IRQ	19
-#define LS1B_PWM2_IRQ	20
-#define LS1B_PWM3_IRQ	21
-#define LS1B_LPC_IRQ	22
-#define LS1B_EHCI_IRQ	32
-#define LS1B_OHCI_IRQ	33
-#define LS1B_GMAC1_IRQ	34
-#define LS1B_GMAC2_IRQ	35
-#define LS1B_SATA_IRQ	36
-#define LS1B_GPU_IRQ	37
+#define LS1B_ACPI_IRQ   0
+#define LS1B_HPET_IRQ   1
+#define LS1B_UART0_IRQ  2
+#define LS1B_UART1_IRQ  3
+#define LS1B_UART2_IRQ  4
+#define LS1B_UART3_IRQ  5
+#define LS1B_CAN0_IRQ   6
+#define LS1B_CAN1_IRQ   7
+#define LS1B_SPI0_IRQ   8
+#define LS1B_SPI1_IRQ   9
+#define LS1B_AC97_IRQ   10
+#define LS1B_MS_IRQ     11
+#define LS1B_KB_IRQ     12
+#define LS1B_DMA0_IRQ   13
+#define LS1B_DMA1_IRQ   14
+#define LS1B_NAND_IRQ   15
+#define LS1B_I2C0_IRQ   16
+#define LS1B_I2C1_IRQ   17
+#define LS1B_PWM0_IRQ   18
+#define LS1B_PWM1_IRQ   19
+#define LS1B_PWM2_IRQ   20
+#define LS1B_PWM3_IRQ   21
+#define LS1B_LPC_IRQ    22
+#define LS1B_EHCI_IRQ   32
+#define LS1B_OHCI_IRQ   33
+#define LS1B_GMAC1_IRQ  34
+#define LS1B_GMAC2_IRQ  35
+#define LS1B_SATA_IRQ   36
+#define LS1B_GPU_IRQ    37
 #define LS1B_PCI_INTA_IRQ 38
 #define LS1B_PCI_INTB_IRQ 39
 #define LS1B_PCI_INTC_IRQ 40
@@ -56,13 +56,13 @@
 #define LS1B_GPIO_IRQ_COUNT 96
 #define LS1B_GPIO_LAST_IRQ  (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1)
 
-#define INT_PCI_INTA	(1<<6)
-#define INT_PCI_INTB	(1<<7)
-#define INT_PCI_INTC	(1<<8)
-#define INT_PCI_INTD	(1<<9)
+#define INT_PCI_INTA    (1<<6)
+#define INT_PCI_INTB    (1<<7)
+#define INT_PCI_INTC    (1<<8)
+#define INT_PCI_INTD    (1<<9)
 
 #define LS1B_LAST_IRQ 159
-#define MIPS_CPU_TIMER_IRQ	167
+#define MIPS_CPU_TIMER_IRQ  167
 #define LS1B_INTREG_BASE 0xbfd01040
 
 #define LS1B_DMA_IRQ_BASE 168
@@ -70,71 +70,71 @@
 
 struct ls1b_intc_regs
 {
-	volatile unsigned int int_isr;
-	volatile unsigned int int_en;
-	volatile unsigned int int_set;
-	volatile unsigned int int_clr;		/* offset 0x10*/
-	volatile unsigned int int_pol;
-   	volatile unsigned int int_edge;		/* offset 0 */
-}; 
+    volatile unsigned int int_isr;
+    volatile unsigned int int_en;
+    volatile unsigned int int_set;
+    volatile unsigned int int_clr;      /* offset 0x10*/
+    volatile unsigned int int_pol;
+    volatile unsigned int int_edge;     /* offset 0 */
+};
 
 struct ls1b_cop_global_regs
 {
-	volatile unsigned int control;
-	volatile unsigned int rd_inten;
-	volatile unsigned int wr_inten;
-	volatile unsigned int rd_intisr;		/* offset 0x10*/
-	volatile unsigned int wr_intisr;
-	unsigned int unused[11];
-} ; 
+    volatile unsigned int control;
+    volatile unsigned int rd_inten;
+    volatile unsigned int wr_inten;
+    volatile unsigned int rd_intisr;        /* offset 0x10*/
+    volatile unsigned int wr_intisr;
+    unsigned int unused[11];
+} ;
 
 struct ls1b_cop_channel_regs
 {
-	volatile unsigned int rd_control;
-	volatile unsigned int rd_src;
-	volatile unsigned int rd_cnt;
-	volatile unsigned int rd_status;		/* offset 0x10*/
-	volatile unsigned int wr_control;
-	volatile unsigned int wr_src;
-	volatile unsigned int wr_cnt;
-	volatile unsigned int wr_status;		/* offset 0x10*/
-} ; 
+    volatile unsigned int rd_control;
+    volatile unsigned int rd_src;
+    volatile unsigned int rd_cnt;
+    volatile unsigned int rd_status;        /* offset 0x10*/
+    volatile unsigned int wr_control;
+    volatile unsigned int wr_src;
+    volatile unsigned int wr_cnt;
+    volatile unsigned int wr_status;        /* offset 0x10*/
+} ;
 
 struct ls1b_cop_regs
 {
-	struct ls1b_cop_global_regs global;
-	struct ls1b_cop_channel_regs chan[8][2];
+    struct ls1b_cop_global_regs global;
+    struct ls1b_cop_channel_regs chan[8][2];
 } ;
 
-#define __REG8(addr)		*((volatile unsigned char *)(addr))
-#define __REG16(addr)		*((volatile unsigned short *)(addr))
-#define __REG32(addr)		*((volatile unsigned int *)(addr))
+#define __REG8(addr)        *((volatile unsigned char *)(addr))
+#define __REG16(addr)       *((volatile unsigned short *)(addr))
+#define __REG32(addr)       *((volatile unsigned int *)(addr))
 
-#define GMAC0_BASE			0xBFE10000
-#define GMAC0_DMA_BASE		0xBFE11000
-#define GMAC1_BASE			0xBFE20000
-#define GMAC1_DMA_BASE		0xBFE21000
-#define I2C0_BASE			0xBFE58000
-#define PWM0_BASE			0xBFE5C000
-#define PWM1_BASE			0xBFE5C010
-#define PWM2_BASE			0xBFE5C020
-#define PWM3_BASE			0xBFE5C030
-#define WDT_BASE			0xBFE5C060
-#define RTC_BASE			0xBFE64000
-#define I2C1_BASE			0xBFE68000
-#define I2C2_BASE			0xBFE70000
-#define AC97_BASE			0xBFE74000
-#define NAND_BASE			0xBFE78000
-#define SPI_BASE			0xBFE80000
-#define CAN1_BASE			0xBF004300
-#define CAN0_BASE			0xBF004400
+#define GMAC0_BASE          0xBFE10000
+#define GMAC0_DMA_BASE      0xBFE11000
+#define GMAC1_BASE          0xBFE20000
+#define GMAC1_DMA_BASE      0xBFE21000
+#define I2C0_BASE           0xBFE58000
+#define PWM0_BASE           0xBFE5C000
+#define PWM1_BASE           0xBFE5C010
+#define PWM2_BASE           0xBFE5C020
+#define PWM3_BASE           0xBFE5C030
+#define WDT_BASE            0xBFE5C060
+#define RTC_BASE            0xBFE64000
+#define I2C1_BASE           0xBFE68000
+#define I2C2_BASE           0xBFE70000
+#define AC97_BASE           0xBFE74000
+#define NAND_BASE           0xBFE78000
+#define SPI_BASE            0xBFE80000
+#define CAN1_BASE           0xBF004300
+#define CAN0_BASE           0xBF004400
 
 /* Watch Dog registers */
-#define WDT_EN				__REG32(WDT_BASE + 0x00)
-#define WDT_SET				__REG32(WDT_BASE + 0x04)
-#define WDT_TIMER			__REG32(WDT_BASE + 0x08)
+#define WDT_EN              __REG32(WDT_BASE + 0x00)
+#define WDT_SET             __REG32(WDT_BASE + 0x04)
+#define WDT_TIMER           __REG32(WDT_BASE + 0x08)
 
-#define PLL_FREQ 				__REG32(0xbfe78030)
-#define PLL_DIV_PARAM 			__REG32(0xbfe78034)
+#define PLL_FREQ                __REG32(0xbfe78030)
+#define PLL_DIV_PARAM           __REG32(0xbfe78034)
 
 #endif
diff --git a/libcpu/mips/loongson_1b/mipscfg.c b/libcpu/mips/loongson_1b/mipscfg.c
index 10dd3fee9e..73e9efd965 100644
--- a/libcpu/mips/loongson_1b/mipscfg.c
+++ b/libcpu/mips/loongson_1b/mipscfg.c
@@ -17,18 +17,18 @@
 
 mips32_core_cfg_t g_mips_core =
 {
-	16,		/* icache_line_size */
-	256,	/* icache_lines_per_way */
-	4,		/* icache_ways */
-	16,		/* dcache_line_size */
-	256,	/* dcache_lines_per_way */
-	4,		/* dcache_ways */
-	16,		/* max_tlb_entries */
+    16,     /* icache_line_size */
+    256,    /* icache_lines_per_way */
+    4,      /* icache_ways */
+    16,     /* dcache_line_size */
+    256,    /* dcache_lines_per_way */
+    4,      /* dcache_ways */
+    16,     /* max_tlb_entries */
 };
 
 static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
 {
-	rt_uint16_t rets = 1;
+    rt_uint16_t rets = 1;
 
     while (n--)
         rets *= b;
@@ -38,7 +38,7 @@ static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
 
 static rt_uint16_t m_log2(rt_uint16_t b)
 {
-	rt_uint16_t rets = 0;
+    rt_uint16_t rets = 0;
 
     while (b != 1)
     {
@@ -54,29 +54,29 @@ static rt_uint16_t m_log2(rt_uint16_t b)
  */
 void mips32_cfg_init(void)
 {
-	rt_uint16_t val;
-	rt_uint32_t cp0_config1;
+    rt_uint16_t val;
+    rt_uint32_t cp0_config1;
 
-	cp0_config1 = read_c0_config();
-	if (cp0_config1 & 0x80000000)
-	{
-		cp0_config1 = read_c0_config1();
+    cp0_config1 = read_c0_config();
+    if (cp0_config1 & 0x80000000)
+    {
+        cp0_config1 = read_c0_config1();
 
-		val = (cp0_config1 & (7<<22))>>22;
-		g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<19))>>19;
-		g_mips_core.icache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<16))>>16;
-		g_mips_core.icache_ways = val + 1;
+        val = (cp0_config1 & (7<<22))>>22;
+        g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
+        val = (cp0_config1 & (7<<19))>>19;
+        g_mips_core.icache_line_size = 2 * m_pow(2, val);
+        val = (cp0_config1 & (7<<16))>>16;
+        g_mips_core.icache_ways = val + 1;
 
-		val = (cp0_config1 & (7<<13))>>13;
-		g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<10))>>10;
-		g_mips_core.dcache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<7))>>7;
-		g_mips_core.dcache_ways = val + 1;
+        val = (cp0_config1 & (7<<13))>>13;
+        g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
+        val = (cp0_config1 & (7<<10))>>10;
+        g_mips_core.dcache_line_size = 2 * m_pow(2, val);
+        val = (cp0_config1 & (7<<7))>>7;
+        g_mips_core.dcache_ways = val + 1;
 
-		val = (cp0_config1 & (0x3F<<25))>>25;
-		g_mips_core.max_tlb_entries = val + 1;
-	}
+        val = (cp0_config1 & (0x3F<<25))>>25;
+        g_mips_core.max_tlb_entries = val + 1;
+    }
 }