diff options
Diffstat (limited to 'libcpu/mips/loongson_1b/mipscfg.c')
| -rw-r--r-- | libcpu/mips/loongson_1b/mipscfg.c | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/libcpu/mips/loongson_1b/mipscfg.c b/libcpu/mips/loongson_1b/mipscfg.c index 10dd3fee9e..73e9efd965 100644 --- a/libcpu/mips/loongson_1b/mipscfg.c +++ b/libcpu/mips/loongson_1b/mipscfg.c @@ -17,18 +17,18 @@ mips32_core_cfg_t g_mips_core = { - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ }; static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) { - rt_uint16_t rets = 1; + rt_uint16_t rets = 1; while (n--) rets *= b; @@ -38,7 +38,7 @@ static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) static rt_uint16_t m_log2(rt_uint16_t b) { - rt_uint16_t rets = 0; + rt_uint16_t rets = 0; while (b != 1) { @@ -54,29 +54,29 @@ static rt_uint16_t m_log2(rt_uint16_t b) */ void mips32_cfg_init(void) { - rt_uint16_t val; - rt_uint32_t cp0_config1; + rt_uint16_t val; + rt_uint32_t cp0_config1; - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } } |