Merge branch 'master' of https://github.com/rt-thread/rt-thread into rtt_issues

35 files changed, 1568 insertions, 378 deletions

diff --git a/libcpu/aarch64/SConscript b/libcpu/aarch64/SConscript
index 453afe4b3e..5fca2b473b 100644
--- a/libcpu/aarch64/SConscript
+++ b/libcpu/aarch64/SConscript
@@ -9,6 +9,9 @@ cwd   = GetCurrentDir()
 group = []
 list  = os.listdir(cwd)
 
+# add common code files
+group = group + SConscript(os.path.join('common', 'SConscript'))
+
 # cpu porting code files
 if rtconfig.CPU != 'common':
     group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
diff --git a/libcpu/aarch64/common/SConscript b/libcpu/aarch64/common/SConscript
new file mode 100644
index 0000000000..72fb8e26c3
--- /dev/null
+++ b/libcpu/aarch64/common/SConscript
@@ -0,0 +1,24 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
+
+# build for sub-directory
+list = os.listdir(cwd)
+objs = []
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+group = group + objs
+
+
+Return('group')
diff --git a/libcpu/aarch64/cortex-a53/armv8.h b/libcpu/aarch64/common/armv8.h
index 4350890544..4350890544 100644
--- a/libcpu/aarch64/cortex-a53/armv8.h
+++ b/libcpu/aarch64/common/armv8.h
diff --git a/libcpu/aarch64/cortex-a53/cache.S b/libcpu/aarch64/common/cache.S
index 7f295a2b02..7f295a2b02 100644
--- a/libcpu/aarch64/cortex-a53/cache.S
+++ b/libcpu/aarch64/common/cache.S
diff --git a/libcpu/aarch64/cortex-a53/context_gcc.S b/libcpu/aarch64/common/context_gcc.S
index 934db7ed84..934db7ed84 100644
--- a/libcpu/aarch64/cortex-a53/context_gcc.S
+++ b/libcpu/aarch64/common/context_gcc.S
diff --git a/libcpu/aarch64/cortex-a53/cp15.h b/libcpu/aarch64/common/cp15.h
index f3ffd6f857..f3ffd6f857 100644
--- a/libcpu/aarch64/cortex-a53/cp15.h
+++ b/libcpu/aarch64/common/cp15.h
diff --git a/libcpu/aarch64/cortex-a53/cpu.c b/libcpu/aarch64/common/cpu.c
index 962a53a071..962a53a071 100644
--- a/libcpu/aarch64/cortex-a53/cpu.c
+++ b/libcpu/aarch64/common/cpu.c
diff --git a/libcpu/aarch64/cortex-a53/cpu_gcc.S b/libcpu/aarch64/common/cpu_gcc.S
index b8c8b8768c..b8c8b8768c 100644
--- a/libcpu/aarch64/cortex-a53/cpu_gcc.S
+++ b/libcpu/aarch64/common/cpu_gcc.S
diff --git a/libcpu/aarch64/common/gic/SConscript b/libcpu/aarch64/common/gic/SConscript
new file mode 100644
index 0000000000..b114ba7678
--- /dev/null
+++ b/libcpu/aarch64/common/gic/SConscript
@@ -0,0 +1,24 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+CPPPATH = [cwd]
+
+gic400_group = Split('''
+gic_pl400.c
+''')
+
+gic500_group = Split('''
+gic_pl500.c
+''')
+
+src = ()
+if GetDepend('BSP_USING_GIC400'):
+	src = gic400_group
+if GetDepend('BSP_USING_GIC500'):
+	src = gic500_group
+
+group = DefineGroup('gic', src, depend = ['BSP_USING_GIC'], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c
new file mode 100644
index 0000000000..4d003a9dcd
--- /dev/null
+++ b/libcpu/aarch64/common/gic/gic_pl400.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ * 2014-04-03     Grissiom     many enhancements
+ * 2018-11-22     Jesven       add rt_hw_ipi_send()
+ *                             add rt_hw_ipi_handler_install()
+ */
+#include <rtthread.h>
+
+#include "gic_pl400.h"
+#include "cp15.h"
+#include "iomap.h"
+
+#define ARM_GIC_MAX_NR 1
+struct arm_gic
+{
+    rt_uint32_t offset;         /* the first interrupt index in the vector table */
+
+    rt_uint32_t dist_hw_base;   /* the base address of the gic distributor */
+    rt_uint32_t cpu_hw_base;    /* the base addrees of the gic cpu interface */
+};
+
+/* 'ARM_GIC_MAX_NR' is the number of cores */
+static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
+
+static unsigned int _gic_max_irq;
+
+int arm_gic_get_active_irq(rt_uint32_t index)
+{
+    int irq;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
+    irq += _gic_table[index].offset;
+    return irq;
+}
+
+void arm_gic_ack(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_mask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_clear_pending(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_clear_active(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+/* Set up the cpu mask for the specific interrupt */
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
+{
+    rt_uint32_t old_tgt;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
+
+    old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
+    old_tgt |=   cpumask << ((irq % 4)*8);
+
+    GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
+}
+
+void arm_gic_umask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_dump_type(rt_uint32_t index)
+{
+    unsigned int gic_type;
+
+    gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
+    rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
+               (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
+               _gic_table[index].dist_hw_base,
+               _gic_max_irq,
+               gic_type & (1 << 10) ? "has" : "no",
+               gic_type);
+}
+
+void arm_gic_dump(rt_uint32_t index)
+{
+    unsigned int i, k;
+
+    k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
+    rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
+    rt_kprintf("--- hw mask ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32));
+    }
+    rt_kprintf("\n--- hw pending ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
+                                        i * 32));
+    }
+    rt_kprintf("\n--- hw active ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32));
+    }
+    rt_kprintf("\n");
+}
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status);
+#endif
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
+{
+    unsigned int gic_type, i;
+    rt_uint32_t cpumask = 1 << 0;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].dist_hw_base = dist_base;
+    _gic_table[index].offset = irq_start;
+
+    /* Find out how many interrupts are supported. */
+    gic_type = GIC_DIST_TYPE(dist_base);
+    _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
+
+    /*
+     * The GIC only supports up to 1020 interrupt sources.
+     * Limit this to either the architected maximum, or the
+     * platform maximum.
+     */
+    if (_gic_max_irq > 1020)
+        _gic_max_irq = 1020;
+    if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */
+        _gic_max_irq = ARM_GIC_NR_IRQS;
+
+    cpumask |= cpumask << 8;
+    cpumask |= cpumask << 16;
+    cpumask |= cpumask << 24;
+
+    GIC_DIST_CTRL(dist_base) = 0x0;
+
+    /* Set all global interrupts to be level triggered, active low. */
+    for (i = 32; i < _gic_max_irq; i += 16)
+        GIC_DIST_CONFIG(dist_base, i) = 0x0;
+
+    /* Set all global interrupts to this CPU only. */
+    for (i = 32; i < _gic_max_irq; i += 4)
+        GIC_DIST_TARGET(dist_base, i) = cpumask;
+
+    /* Set priority on all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 4)
+        GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
+
+    /* Disable all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
+
+#if 0
+    /* All interrupts defaults to IGROUP1(IRQ). */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_IGROUP(dist_base, i) = 0xffffffff;
+#endif
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_IGROUP(dist_base, i) = 0;
+
+    /* Enable group0 and group1 interrupt forwarding. */
+    GIC_DIST_CTRL(dist_base) = 0x01;
+
+    return 0;
+}
+
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].cpu_hw_base = cpu_base;
+
+    GIC_CPU_PRIMASK(cpu_base) = 0xf0;
+    GIC_CPU_BINPOINT(cpu_base) = 0x7;
+    /* Enable CPU interrupt */
+    GIC_CPU_CTRL(cpu_base) = 0x01;
+
+    return 0;
+}
+
+void arm_gic_set_group(rt_uint32_t index, int vector, int group)
+{
+    /* As for GICv2, there are only group0 and group1. */
+    RT_ASSERT(group <= 1);
+    RT_ASSERT(vector < _gic_max_irq);
+
+    if (group == 0)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) &= ~(1 << (vector % 32));
+    }
+    else if (group == 1)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) |=  (1 << (vector % 32));
+    }
+}
+
diff --git a/libcpu/aarch64/common/gic/gic_pl400.h b/libcpu/aarch64/common/gic/gic_pl400.h
new file mode 100644
index 0000000000..fa20846ea2
--- /dev/null
+++ b/libcpu/aarch64/common/gic/gic_pl400.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ */
+
+#ifndef __GIC_PL400_H__
+#define __GIC_PL400_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define __REG32(x) (*((volatile unsigned int*)((rt_uint64_t)x)))
+
+#define GIC_CPU_CTRL(hw_base)               __REG32((hw_base) + 0x00)
+#define GIC_CPU_PRIMASK(hw_base)            __REG32((hw_base) + 0x04)
+#define GIC_CPU_BINPOINT(hw_base)           __REG32((hw_base) + 0x08)
+#define GIC_CPU_INTACK(hw_base)             __REG32((hw_base) + 0x0c)
+#define GIC_CPU_EOI(hw_base)                __REG32((hw_base) + 0x10)
+#define GIC_CPU_RUNNINGPRI(hw_base)         __REG32((hw_base) + 0x14)
+#define GIC_CPU_HIGHPRI(hw_base)            __REG32((hw_base) + 0x18)
+
+#define GIC_DIST_CTRL(hw_base)              __REG32((hw_base) + 0x000)
+#define GIC_DIST_TYPE(hw_base)              __REG32((hw_base) + 0x004)
+#define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080 + ((n)/32) * 4)
+#define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + ((n)/32) * 4)
+#define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + ((n)/32) * 4)
+#define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200 + ((n)/32) * 4)
+#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280 + ((n)/32) * 4)
+#define GIC_DIST_ACTIVE_SET(hw_base, n)     __REG32((hw_base) + 0x300 + ((n)/32) * 4)
+#define GIC_DIST_ACTIVE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x380 + ((n)/32) * 4)
+#define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400 +  ((n)/4) * 4)
+#define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800 +  ((n)/4) * 4)
+#define GIC_DIST_CONFIG(hw_base, n)         __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
+#define GIC_DIST_SOFTINT(hw_base)           __REG32((hw_base) + 0xf00)
+#define GIC_DIST_CPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf10 + ((n)/4) * 4)
+#define GIC_DIST_ICPIDR2(hw_base)           __REG32((hw_base) + 0xfe8)
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
+
+void arm_gic_mask(rt_uint32_t index, int irq);
+void arm_gic_umask(rt_uint32_t index, int irq);
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
+void arm_gic_set_group(rt_uint32_t index, int vector, int group);
+
+int arm_gic_get_active_irq(rt_uint32_t index);
+void arm_gic_ack(rt_uint32_t index, int irq);
+
+void arm_gic_clear_active(rt_uint32_t index, int irq);
+void arm_gic_clear_pending(rt_uint32_t index, int irq);
+
+void arm_gic_dump_type(rt_uint32_t index);
+void arm_gic_dump(rt_uint32_t index);
+
+#endif
+
diff --git a/libcpu/aarch64/cortex-a53/mmu.c b/libcpu/aarch64/common/mmu.c
index b799143084..b799143084 100644
--- a/libcpu/aarch64/cortex-a53/mmu.c
+++ b/libcpu/aarch64/common/mmu.c
diff --git a/libcpu/aarch64/cortex-a53/mmu.h b/libcpu/aarch64/common/mmu.h
index 6a66472c79..6a66472c79 100644
--- a/libcpu/aarch64/cortex-a53/mmu.h
+++ b/libcpu/aarch64/common/mmu.h
diff --git a/libcpu/aarch64/cortex-a53/startup_gcc.S b/libcpu/aarch64/common/startup_gcc.S
index ea4268148c..ea4268148c 100644
--- a/libcpu/aarch64/cortex-a53/startup_gcc.S
+++ b/libcpu/aarch64/common/startup_gcc.S
diff --git a/libcpu/aarch64/cortex-a53/vector_gcc.S b/libcpu/aarch64/common/vector_gcc.S
index fc88cce7f8..fc88cce7f8 100644
--- a/libcpu/aarch64/cortex-a53/vector_gcc.S
+++ b/libcpu/aarch64/common/vector_gcc.S
diff --git a/libcpu/aarch64/cortex-a53/SConscript b/libcpu/aarch64/cortex-a53/SConscript
index 75e170a0cf..c6a4817802 100644
--- a/libcpu/aarch64/cortex-a53/SConscript
+++ b/libcpu/aarch64/cortex-a53/SConscript
@@ -1,16 +1,13 @@
+# RT-Thread building script for component
+
 from building import *
 
+Import('rtconfig')
+
 cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp')
-asm_src = Split('''
-context_gcc.S
-vector_gcc.S
-entry_point.S
-cpu_gcc.S
-cache.S
-''')
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
 CPPPATH = [cwd]
 
-group = DefineGroup('cpu', src + asm_src, depend = [''], CPPPATH = CPPPATH)
+group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/libcpu/aarch64/cortex-a53/interrupt.h b/libcpu/aarch64/cortex-a53/interrupt.h
index 3533d3818c..8e741ed4e6 100644
--- a/libcpu/aarch64/cortex-a53/interrupt.h
+++ b/libcpu/aarch64/cortex-a53/interrupt.h
@@ -1,11 +1,11 @@
-
 /*
  * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       Notes
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
  */
 
 #ifndef __INTERRUPT_H__
@@ -19,8 +19,6 @@
 #define INT_IRQ     0x00
 #define INT_FIQ     0x01
 
-//void rt_hw_vector_init(void);
-
 void rt_hw_interrupt_init(void);
 void rt_hw_interrupt_mask(int vector);
 void rt_hw_interrupt_umask(int vector);
diff --git a/libcpu/aarch64/cortex-a72/SConscript b/libcpu/aarch64/cortex-a72/SConscript
new file mode 100644
index 0000000000..c6a4817802
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/SConscript
@@ -0,0 +1,13 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/aarch64/cortex-a72/entry_point.S b/libcpu/aarch64/cortex-a72/entry_point.S
new file mode 100644
index 0000000000..6d2c69226b
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/entry_point.S
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Date           Author       Notes
+ * 2020-01-15     bigmagic    the first version
+ */
+
+.section ".text.entrypoint"
+
+.set EL1_stack,         __el1_stack
+
+.global _start
+
+// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware
+// loads 'kernel8.img' file in.
+_start:
+    // read cpu id, stop slave cores
+    mrs     x1, mpidr_el1            // MPIDR_EL1: Multi-Processor Affinity Register
+    and     x1, x1, #3
+    cbz     x1, .L__cpu_0             // .L prefix is the local label in ELF 
+
+    // cpu id > 0, stop
+    // cpu id == 0 will also goto here after returned from entry() if possible
+.L__current_cpu_idle:
+    wfe
+    b       .L__current_cpu_idle
+
+.L__cpu_0:  // cpu id == 0
+
+    // set stack before our code
+
+	/* Define stack pointer for current exception level */
+	// ldr	x2, =EL1_stack
+	// mov	sp, x2
+
+    ldr     x1, =_start
+
+    // set up EL1
+    mrs     x0, CurrentEL           // CurrentEL Register. bit 2, 3. Others reserved
+    and     x0, x0, #12             // clear reserved bits
+
+    // running at EL3?
+    cmp     x0, #12                // 1100b. So, EL3
+    bne     .L__not_in_el3         // 11?  !EL3 -> 5:
+
+    // should never be executed, just for completeness. (EL3)
+    mov     x2, #0x5b1
+    msr     scr_el3, x2            // SCR_ELn  Secure Configuration Register
+    mov     x2, #0x3c9
+    msr     spsr_el3, x2           // SPSR_ELn. Saved Program Status Register. 1111001001
+    adr     x2, .L__not_in_el3   
+    msr     elr_el3, x2
+    eret                           // Exception Return: from EL3, continue from .L__not_in_el3
+
+    // running at EL2 or EL1
+.L__not_in_el3:    
+    cmp     x0, #4                 // 0x04  0100 EL1
+    beq     .L__in_el1             // EL1 -> 5:
+
+    // in EL2
+    msr     sp_el1, x1             // Set sp of EL1 to _start
+
+    // enable CNTP for EL1
+    mrs     x0, cnthctl_el2         // Counter-timer Hypervisor Control register
+    orr     x0, x0, #3
+    msr     cnthctl_el2, x0
+    msr     cntvoff_el2, xzr
+
+    // enable AArch64 in EL1
+    mov     x0, #(1 << 31)          // AArch64
+    orr     x0, x0, #(1 << 1)       // SWIO hardwired on Pi3
+    msr     hcr_el2, x0
+    mrs     x0, hcr_el2
+
+    // change execution level to EL1
+    mov     x2, #0x3c4
+    msr     spsr_el2, x2        // 1111000100
+    adr     x2, .L__in_el1
+    msr     elr_el2, x2
+    eret                        // exception return. from EL2. continue from .L__in_el1
+
+.L__in_el1:
+    mov     sp, x1             // in EL1. Set sp to _start
+
+    // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction
+    mov     x1, #0x00300000       // Don't trap any SIMD/FP instructions in both EL0 and EL1
+    msr     cpacr_el1, x1
+
+    mrs x1, sctlr_el1
+    orr x1, x1, #(1 << 12)
+    bic x1, x1, #(3 << 3)
+    bic x1, x1, #(1 << 1)
+    msr sctlr_el1, x1
+
+    // clear bss
+    ldr     x1, =__bss_start
+    ldr     w2, =__bss_size
+
+.L__clean_bss_loop:
+    cbz     w2, .L__jump_to_entry
+    str     xzr, [x1], #8
+    sub     w2, w2, #1
+    cbnz    w2, .L__clean_bss_loop
+
+    // jump to C code, should not return
+.L__jump_to_entry:
+    bl      entry
+    // for failsafe, halt this core too
+    b       .L__current_cpu_idle
diff --git a/libcpu/aarch64/cortex-a72/interrupt.c b/libcpu/aarch64/cortex-a72/interrupt.c
new file mode 100644
index 0000000000..6fec968dc2
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/interrupt.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <gic_pl400.h>
+#include <board.h>
+#include <armv8.h>
+#include "iomap.h"
+
+#define MAX_HANDLERS                256
+#define GIC_ACK_INTID_MASK          0x000003ff
+
+#ifdef RT_USING_SMP
+#define rt_interrupt_nest rt_cpu_self()->irq_nest
+#else
+extern volatile rt_uint8_t rt_interrupt_nest;
+#endif
+
+extern int system_vectors;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+rt_ubase_t rt_interrupt_from_thread;
+rt_ubase_t rt_interrupt_to_thread;
+rt_ubase_t rt_thread_switch_interrupt_flag;
+
+void rt_hw_vector_init(void)
+{
+    rt_hw_set_current_vbar((rt_ubase_t)&system_vectors);  // cpu_gcc.S
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+
+    rt_uint32_t gic_cpu_base = 0;
+    rt_uint32_t gic_dist_base = 0;
+
+    /* initialize ARM GIC */
+    gic_dist_base = GIC_PL400_DISTRIBUTOR_PPTR;
+    gic_cpu_base = GIC_PL400_CONTROLLER_PPTR;
+    arm_gic_dist_init(0, gic_dist_base, 0);
+    arm_gic_cpu_init(0, gic_cpu_base);
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    arm_gic_mask(0, vector);
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    arm_gic_umask(0, vector);
+}
+
+/**
+ * This function returns the active interrupt number.
+ * @param none
+ */
+int rt_hw_interrupt_get_irq(void)
+{
+    return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK;
+}
+
+/**
+ * This function acknowledges the interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_ack(int vector)
+{
+    arm_gic_ack(0, vector);
+}
diff --git a/libcpu/aarch64/cortex-a72/interrupt.h b/libcpu/aarch64/cortex-a72/interrupt.h
new file mode 100644
index 0000000000..0d2d4867c7
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/interrupt.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define INT_IRQ     0x00
+#define INT_FIQ     0x01
+
+void rt_hw_interrupt_init(void);
+void rt_hw_interrupt_mask(int vector);
+void rt_hw_interrupt_umask(int vector);
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name);
+
+#endif
diff --git a/libcpu/aarch64/cortex-a72/stack.c b/libcpu/aarch64/cortex-a72/stack.c
new file mode 100644
index 0000000000..68222c2c67
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/stack.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ */
+#include <rtthread.h>
+#include <board.h>
+
+#include <armv8.h>
+
+#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0)
+#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0)
+#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0)
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry 
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	rt_ubase_t *stk;
+	rt_ubase_t current_el;
+
+	stk 	 = (rt_ubase_t*)stack_addr;
+
+	*(--stk) = ( rt_ubase_t ) 11;			/* X1 */
+	*(--stk) = ( rt_ubase_t ) parameter; 	/* X0 */
+	*(--stk) = ( rt_ubase_t ) 33;			/* X3 */
+	*(--stk) = ( rt_ubase_t ) 22;			/* X2 */
+	*(--stk) = ( rt_ubase_t ) 55;			/* X5 */
+	*(--stk) = ( rt_ubase_t ) 44;			/* X4 */
+	*(--stk) = ( rt_ubase_t ) 77;			/* X7 */
+	*(--stk) = ( rt_ubase_t ) 66;			/* X6 */
+	*(--stk) = ( rt_ubase_t ) 99;			/* X9 */
+	*(--stk) = ( rt_ubase_t ) 88;			/* X8 */
+	*(--stk) = ( rt_ubase_t ) 11;			/* X11 */
+	*(--stk) = ( rt_ubase_t ) 10;			/* X10 */
+	*(--stk) = ( rt_ubase_t ) 13;			/* X13 */
+	*(--stk) = ( rt_ubase_t ) 12;			/* X12 */
+	*(--stk) = ( rt_ubase_t ) 15;			/* X15 */
+	*(--stk) = ( rt_ubase_t ) 14;			/* X14 */
+	*(--stk) = ( rt_ubase_t ) 17;			/* X17 */
+	*(--stk) = ( rt_ubase_t ) 16;			/* X16 */
+	*(--stk) = ( rt_ubase_t ) 19;			/* X19 */
+	*(--stk) = ( rt_ubase_t ) 18;			/* X18 */
+	*(--stk) = ( rt_ubase_t ) 21;			/* X21 */
+	*(--stk) = ( rt_ubase_t ) 20;			/* X20 */
+	*(--stk) = ( rt_ubase_t ) 23;			/* X23 */
+	*(--stk) = ( rt_ubase_t ) 22;			/* X22 */
+	*(--stk) = ( rt_ubase_t ) 25;			/* X25 */
+	*(--stk) = ( rt_ubase_t ) 24;			/* X24 */
+	*(--stk) = ( rt_ubase_t ) 27;			/* X27 */
+	*(--stk) = ( rt_ubase_t ) 26;			/* X26 */
+	*(--stk) = ( rt_ubase_t ) 29;			/* X29 */
+	*(--stk) = ( rt_ubase_t ) 28;			/* X28 */
+	*(--stk) = ( rt_ubase_t ) 0;			/* XZR - has no effect, used so there are an even number of registers. */
+	*(--stk) = ( rt_ubase_t ) texit;		/* X30 - procedure call link register. */
+
+	current_el = rt_hw_get_current_el();
+
+	if(current_el == 3)
+	{
+		*(--stk) = INITIAL_SPSR_EL3;
+	}
+	else if(current_el == 2)
+	{
+		*(--stk) = INITIAL_SPSR_EL2;
+	}
+	else
+	{
+		*(--stk) = INITIAL_SPSR_EL1;
+	}
+
+	*(--stk) = ( rt_ubase_t ) tentry; 		/* Exception return address. */
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
diff --git a/libcpu/aarch64/cortex-a72/trap.c b/libcpu/aarch64/cortex-a72/trap.c
new file mode 100644
index 0000000000..d93aa18fd6
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/trap.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * 
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "interrupt.h"
+#include "armv8.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
+    rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
+	rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
+	rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
+	rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
+	rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
+    rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
+	rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
+	rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
+	rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
+}
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("error exception:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+#define GIC_ACK_INTID_MASK              0x000003ff
+
+int rt_hw_interrupt_get_irq(void);
+void rt_hw_interrupt_ack(int fiq_irq);
+
+void rt_hw_trap_irq(void)
+{
+    void *param;
+    int ir; 
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    ir = rt_hw_interrupt_get_irq();
+    if (ir == 1023)
+    {
+        /* Spurious interrupt */
+        return;
+    }
+
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+    isr_table[ir].counter++;
+#endif
+    if (isr_func)
+    {
+        /* Interrupt for myself. */
+        param = isr_table[ir].param;
+        /* turn to interrupt service routine */
+        isr_func(ir, param);
+    }
+
+    /* end of interrupt */
+    rt_hw_interrupt_ack(ir);
+
+}
+
+void rt_hw_trap_fiq(void)
+{
+}
diff --git a/libcpu/arm/s3c24x0/serial.c b/libcpu/arm/s3c24x0/serial.c
deleted file mode 100644
index 1eca1b1110..0000000000
--- a/libcpu/arm/s3c24x0/serial.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-03-13     Bernard      first version
- * 2009-04-20     yi.qiu      modified according bernard's stm32 version
- */
-
-#include <rtthread.h>
-
-#include "serial.h"
-
-/**
- * @addtogroup S3C24X0
- */
-/*@{*/
-
-/* RT-Thread Device Interface */
-/**
- * This function initializes serial
- */
-static rt_err_t rt_serial_init(rt_device_t dev)
-{
-    struct serial_device* uart = (struct serial_device*) dev->user_data;
-
-    if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
-    {
-
-        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-        {
-            rt_memset(uart->int_rx->rx_buffer, 0,
-                      sizeof(uart->int_rx->rx_buffer));
-            uart->int_rx->read_index = uart->int_rx->save_index = 0;
-        }
-
-        if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-        {
-            rt_memset(uart->int_tx->tx_buffer, 0,
-                      sizeof(uart->int_tx->tx_buffer));
-            uart->int_tx->write_index = uart->int_tx->save_index = 0;
-        }
-
-        dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
-    }
-
-    return RT_EOK;
-}
-
-/* save a char to serial buffer */
-static void rt_serial_savechar(struct serial_device* uart, char ch)
-{
-    rt_base_t level;
-
-    /* disable interrupt */
-    level = rt_hw_interrupt_disable();
-
-    uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
-    uart->int_rx->save_index ++;
-    if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
-        uart->int_rx->save_index = 0;
-
-    /* if the next position is read index, discard this 'read char' */
-    if (uart->int_rx->save_index == uart->int_rx->read_index)
-    {
-        uart->int_rx->read_index ++;
-        if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
-            uart->int_rx->read_index = 0;
-    }
-
-    /* enable interrupt */
-    rt_hw_interrupt_enable(level);
-}
-
-static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
-{
-    RT_ASSERT(dev != RT_NULL);
-
-    return RT_EOK;
-}
-
-static rt_err_t rt_serial_close(rt_device_t dev)
-{
-    RT_ASSERT(dev != RT_NULL);
-
-    return RT_EOK;
-}
-
-static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
-    rt_uint8_t* ptr;
-    rt_err_t err_code;
-    struct serial_device* uart;
-
-    ptr = buffer;
-    err_code = RT_EOK;
-    uart = (struct serial_device*)dev->user_data;
-
-    if (ptr == RT_NULL)
-    {
-        err_code = -RT_ENOMEM;
-        rt_set_errno(err_code);
-        return -RT_ENOMEM;
-    }
-    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-    {
-        rt_base_t level;
-
-        /* interrupt mode Rx */
-        while (size)
-        {
-            if (uart->int_rx->read_index != uart->int_rx->save_index)
-            {
-                *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
-                size --;
-
-                /* disable interrupt */
-                level = rt_hw_interrupt_disable();
-
-                uart->int_rx->read_index ++;
-                if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
-                    uart->int_rx->read_index = 0;
-
-                /* enable interrupt */
-                rt_hw_interrupt_enable(level);
-            }
-            else
-            {
-                /* set error code */
-                err_code = -RT_EEMPTY;
-                break;
-            }
-        }
-    }
-    else
-    {
-        /* polling mode */
-        while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
-        {
-            while (uart->uart_device->ustat & USTAT_RCV_READY)
-            {
-                *ptr = uart->uart_device->urxh & 0xff;
-                ptr ++;
-            }
-        }
-    }
-
-    /* set error code */
-    rt_set_errno(err_code);
-    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-}
-
-static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
-    rt_uint8_t* ptr;
-    rt_err_t err_code;
-    struct serial_device* uart;
-
-    err_code = RT_EOK;
-    ptr = (rt_uint8_t*)buffer;
-    uart = (struct serial_device*)dev->user_data;
-
-    if (ptr == RT_NULL)
-    {
-        err_code = -RT_ENOMEM;
-        rt_set_errno(err_code);
-        return -RT_ENOMEM;
-    }
-    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-    {
-        /* interrupt mode Tx */
-        while (uart->int_tx->save_index != uart->int_tx->write_index)
-        {
-            /* save on tx buffer */
-            uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
-
-            -- size;
-
-            /* move to next position */
-            uart->int_tx->save_index ++;
-
-            /* wrap save index */
-            if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
-                uart->int_tx->save_index = 0;
-        }
-
-        /* set error code */
-        if (size > 0)
-            err_code = -RT_EFULL;
-    }
-    else
-    {
-        /* polling mode */
-        while (size)
-        {
-            /*
-             * to be polite with serial console add a line feed
-             * to the carriage return character
-             */
-            if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
-            {
-                while (!(uart->uart_device->ustat & USTAT_TXB_EMPTY));
-                uart->uart_device->utxh = '\r';
-            }
-
-            while (!(uart->uart_device->ustat & USTAT_TXB_EMPTY));
-            uart->uart_device->utxh = (*ptr & 0xFF);
-
-            ++ptr;
-            --size;
-        }
-    }
-
-    /* set error code */
-    rt_set_errno(err_code);
-    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-}
-
-static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
-{
-    RT_ASSERT(dev != RT_NULL);
-
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_SUSPEND:
-        /* suspend device */
-        dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
-        break;
-
-    case RT_DEVICE_CTRL_RESUME:
-        /* resume device */
-        dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
-        break;
-    }
-
-    return RT_EOK;
-}
-
-/*
- * serial register
- */
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial)
-{
-    RT_ASSERT(device != RT_NULL);
-
-    device->type        = RT_Device_Class_Char;
-    device->rx_indicate = RT_NULL;
-    device->tx_complete = RT_NULL;
-    device->init        = rt_serial_init;
-    device->open        = rt_serial_open;
-    device->close       = rt_serial_close;
-    device->read        = rt_serial_read;
-    device->write       = rt_serial_write;
-    device->control     = rt_serial_control;
-    device->user_data   = serial;
-
-    /* register a character device */
-    return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
-}
-
-/* ISR for serial interrupt */
-void rt_hw_serial_isr(rt_device_t device)
-{
-    struct serial_device* uart = (struct serial_device*) device->user_data;
-
-    /* interrupt mode receive */
-    RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
-
-    /* save on rx buffer */
-    while (uart->uart_device->ustat & USTAT_RCV_READY)
-    {
-        rt_serial_savechar(uart, uart->uart_device->urxh & 0xff);
-    }
-
-    /* invoke callback */
-    if (device->rx_indicate != RT_NULL)
-    {
-        rt_size_t rx_length;
-
-        /* get rx length */
-        rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
-                    UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
-                    uart->int_rx->save_index - uart->int_rx->read_index;
-
-        device->rx_indicate(device, rx_length);
-    }
-}
-
-/*@}*/
diff --git a/libcpu/arm/s3c24x0/serial.h b/libcpu/arm/s3c24x0/serial.h
deleted file mode 100644
index 8a647ef35f..0000000000
--- a/libcpu/arm/s3c24x0/serial.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-#ifndef __RT_HW_SERIAL_H__
-#define __RT_HW_SERIAL_H__
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "s3c24x0.h"
-
-#define	USTAT_RCV_READY		0x01   	/* receive data ready */ 
-#define	USTAT_TXB_EMPTY		0x02   	/* tx buffer empty */
-#define BPS					115200	/* serial baudrate */
-
-#define UART_RX_BUFFER_SIZE		64
-#define UART_TX_BUFFER_SIZE		64
-
-struct serial_int_rx
-{
-	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
-	rt_uint32_t read_index, save_index;
-};
-
-struct serial_int_tx
-{
-	rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
-	rt_uint32_t write_index, save_index;
-};
-
-typedef struct uartport
-{
-	volatile rt_uint32_t ulcon;
-	volatile rt_uint32_t ucon;
-	volatile rt_uint32_t ufcon;
-	volatile rt_uint32_t umcon;
-	volatile rt_uint32_t ustat;
-	volatile rt_uint32_t urxb;
-	volatile rt_uint32_t ufstat;
-	volatile rt_uint32_t umstat;
-	volatile rt_uint32_t utxh;	
-	volatile rt_uint32_t urxh;	
-	volatile rt_uint32_t ubrd;
-}uartport;
-
-struct serial_device
-{
-	uartport* uart_device;
-	
-	/* rx structure */
-	struct serial_int_rx* int_rx;
-
-	/* tx structure */
-	struct serial_int_tx* int_tx;
-};
-
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
-
-void rt_hw_serial_isr(rt_device_t device);
-
-#endif
diff --git a/libcpu/arm/s3c24x0/start_gcc.S b/libcpu/arm/s3c24x0/start_gcc.S
index 4adc458094..cc2b2f6310 100644
--- a/libcpu/arm/s3c24x0/start_gcc.S
+++ b/libcpu/arm/s3c24x0/start_gcc.S
@@ -191,7 +191,7 @@ reset:
 copy_loop:
 	ldmia	r0!, {r3-r10}			/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}			/* copy to   target address [r1]    */
-	cmp		r0, r2					/* until source end addreee [r2]    */
+	cmp		r0, r2			/* until source end address [r2]    */
 	ble		copy_loop
 
 	/* setup stack */
diff --git a/libcpu/arm/s3c44b0/start_gcc.S b/libcpu/arm/s3c44b0/start_gcc.S
index 65b3d422dd..4c448a344f 100644
--- a/libcpu/arm/s3c44b0/start_gcc.S
+++ b/libcpu/arm/s3c44b0/start_gcc.S
@@ -107,7 +107,7 @@ reset:
 copy_loop:
 	ldmia	r0!, {r3-r10}	/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}	/* copy to   target address [r1]    */
-	cmp	r0, r2				/* until source end addreee [r2]    */
+	cmp	r0, r2		/* until source end address [r2]    */
 	ble	copy_loop
 #endif
 	
diff --git a/libcpu/mips/common/mips_fpu.h b/libcpu/mips/common/mips_fpu.h
index d6351f7655..50df3746a5 100644
--- a/libcpu/mips/common/mips_fpu.h
+++ b/libcpu/mips/common/mips_fpu.h
@@ -18,7 +18,7 @@
  * init hardware FPU
  */
 #ifdef RT_USING_FPU
-inline void rt_hw_fpu_init(void)
+rt_inline void rt_hw_fpu_init(void)
 {
     rt_uint32_t c0_status = 0;
     rt_uint32_t c1_status = 0;
@@ -38,7 +38,7 @@ inline void rt_hw_fpu_init(void)
     return ;
 }
 #else
-    inline void rt_hw_fpu_init(void){} /* Do nothing */
+    rt_inline void rt_hw_fpu_init(void){} /* Do nothing */
 #endif
 
 #endif
diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h
index c5dd727e23..a13e24b539 100644
--- a/libcpu/mips/common/mips_regs.h
+++ b/libcpu/mips/common/mips_regs.h
@@ -999,7 +999,7 @@ do {									\
 
 #define write_32bit_cp0_set1_register(register,value)           \
         __asm__ __volatile__(                                   \
-        "ctc0\t%0,"STR(register)"\n\t"				\
+        "ctc0\t%0,$"STR(register)"\n\t"				\
     "nop"							\
         : : "r" (value));
 
@@ -1037,14 +1037,14 @@ do {									\
     __asm__ __volatile__(                                   \
     ".set\tpush\n\t"					\
     ".set\treorder\n\t"					\
-        "cfc1\t%0,"STR(source)"\n\t"                            \
+        "cfc1\t%0,$"STR(source)"\n\t"                            \
     ".set\tpop"						\
         : "=r" (__res));                                        \
         __res;})
 
 #define write_32bit_cp1_register(register,value)                \
         __asm__ __volatile__(                                   \
-        "ctc1\t%0,"STR(register)"\n\t"				\
+        "ctc1\t%0,$"STR(register)"\n\t"				\
     "nop"							\
         : : "r" (value));
 
diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript
index 640e46a4fb..024cc5ba44 100644
--- a/libcpu/risc-v/SConscript
+++ b/libcpu/risc-v/SConscript
@@ -10,7 +10,8 @@ group = []
 list  = os.listdir(cwd)
 
 # add common code files
-group = group + SConscript(os.path.join('common', 'SConscript'))
+if rtconfig.CPU != "nuclei":
+    group = group + SConscript(os.path.join('common', 'SConscript'))
 
 # cpu porting code files
 group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
diff --git a/libcpu/risc-v/nuclei/SConscript b/libcpu/risc-v/nuclei/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/risc-v/nuclei/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/risc-v/nuclei/context_gcc.S b/libcpu/risc-v/nuclei/context_gcc.S
new file mode 100644
index 0000000000..fda453940d
--- /dev/null
+++ b/libcpu/risc-v/nuclei/context_gcc.S
@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/03/26     Huaqi        First Nuclei RISC-V porting implementation
+ */
+
+#include "riscv_encoding.h"
+
+#ifndef __riscv_32e
+#define RT_SAVED_REGNUM         30
+#else
+#define RT_SAVED_REGNUM         14
+#endif
+
+#define RT_CONTEXT_SIZE         (RT_SAVED_REGNUM * REGBYTES)
+
+    .extern rt_interrupt_from_thread
+    .extern rt_interrupt_to_thread
+
+
+.section    .text
+
+
+/*
+ * void rt_hw_context_switch_to(rt_ubase_t to);
+ * a0 --> to_thread
+ */
+    .globl rt_hw_context_switch_to
+
+/* Start the first task.  This also clears the bit that indicates the FPU is
+	in use in case the FPU was used before the scheduler was started - which
+	would otherwise result in the unnecessary leaving of space in the stack
+	for lazy saving of FPU registers. */
+.align 3
+rt_hw_context_switch_to:
+    /* Setup Interrupt Stack using
+       The stack that was used by main()
+       before the scheduler is started is
+       no longer required after the scheduler is started.
+       Interrupt stack pointer is stored in CSR_MSCRATCH */
+    la t0, _sp
+    csrw CSR_MSCRATCH, t0
+    LOAD sp, 0x0(a0)                /* Read sp from first TCB member(a0) */
+
+    /* Pop PC from stack and set MEPC */
+    LOAD t0,  0  * REGBYTES(sp)
+    csrw CSR_MEPC, t0
+    /* Pop mstatus from stack and set it */
+    LOAD t0,  (RT_SAVED_REGNUM - 1)  * REGBYTES(sp)
+    csrw CSR_MSTATUS, t0
+    /* Interrupt still disable here */
+    /* Restore Registers from Stack */
+    LOAD x1,  1  * REGBYTES(sp)    /* RA */
+    LOAD x5,  2  * REGBYTES(sp)
+    LOAD x6,  3  * REGBYTES(sp)
+    LOAD x7,  4  * REGBYTES(sp)
+    LOAD x8,  5  * REGBYTES(sp)
+    LOAD x9,  6  * REGBYTES(sp)
+    LOAD x10, 7  * REGBYTES(sp)
+    LOAD x11, 8  * REGBYTES(sp)
+    LOAD x12, 9  * REGBYTES(sp)
+    LOAD x13, 10 * REGBYTES(sp)
+    LOAD x14, 11 * REGBYTES(sp)
+    LOAD x15, 12 * REGBYTES(sp)
+#ifndef __riscv_32e
+    LOAD x16, 13 * REGBYTES(sp)
+    LOAD x17, 14 * REGBYTES(sp)
+    LOAD x18, 15 * REGBYTES(sp)
+    LOAD x19, 16 * REGBYTES(sp)
+    LOAD x20, 17 * REGBYTES(sp)
+    LOAD x21, 18 * REGBYTES(sp)
+    LOAD x22, 19 * REGBYTES(sp)
+    LOAD x23, 20 * REGBYTES(sp)
+    LOAD x24, 21 * REGBYTES(sp)
+    LOAD x25, 22 * REGBYTES(sp)
+    LOAD x26, 23 * REGBYTES(sp)
+    LOAD x27, 24 * REGBYTES(sp)
+    LOAD x28, 25 * REGBYTES(sp)
+    LOAD x29, 26 * REGBYTES(sp)
+    LOAD x30, 27 * REGBYTES(sp)
+    LOAD x31, 28 * REGBYTES(sp)
+#endif
+
+    addi sp, sp, RT_CONTEXT_SIZE
+
+    mret
+
+.align 2
+.global eclic_msip_handler
+eclic_msip_handler:
+    addi sp, sp, -RT_CONTEXT_SIZE
+    STORE x1,  1  * REGBYTES(sp)    /* RA */
+    STORE x5,  2  * REGBYTES(sp)
+    STORE x6,  3  * REGBYTES(sp)
+    STORE x7,  4  * REGBYTES(sp)
+    STORE x8,  5  * REGBYTES(sp)
+    STORE x9,  6  * REGBYTES(sp)
+    STORE x10, 7  * REGBYTES(sp)
+    STORE x11, 8  * REGBYTES(sp)
+    STORE x12, 9  * REGBYTES(sp)
+    STORE x13, 10 * REGBYTES(sp)
+    STORE x14, 11 * REGBYTES(sp)
+    STORE x15, 12 * REGBYTES(sp)
+#ifndef __riscv_32e
+    STORE x16, 13 * REGBYTES(sp)
+    STORE x17, 14 * REGBYTES(sp)
+    STORE x18, 15 * REGBYTES(sp)
+    STORE x19, 16 * REGBYTES(sp)
+    STORE x20, 17 * REGBYTES(sp)
+    STORE x21, 18 * REGBYTES(sp)
+    STORE x22, 19 * REGBYTES(sp)
+    STORE x23, 20 * REGBYTES(sp)
+    STORE x24, 21 * REGBYTES(sp)
+    STORE x25, 22 * REGBYTES(sp)
+    STORE x26, 23 * REGBYTES(sp)
+    STORE x27, 24 * REGBYTES(sp)
+    STORE x28, 25 * REGBYTES(sp)
+    STORE x29, 26 * REGBYTES(sp)
+    STORE x30, 27 * REGBYTES(sp)
+    STORE x31, 28 * REGBYTES(sp)
+#endif
+    /* Push mstatus to stack */
+    csrr t0, CSR_MSTATUS
+    STORE t0,  (RT_SAVED_REGNUM - 1)  * REGBYTES(sp)
+
+    /* Push additional registers */
+
+    /* Store sp to task stack */
+    LOAD t0, rt_interrupt_from_thread
+    STORE sp, 0(t0)
+
+    csrr t0, CSR_MEPC
+    STORE t0, 0(sp)
+
+    jal rt_hw_taskswitch
+
+    /* Switch task context */
+    LOAD t0, rt_interrupt_to_thread
+    LOAD sp, 0x0(t0)
+
+    /* Pop PC from stack and set MEPC */
+    LOAD t0,  0  * REGBYTES(sp)
+    csrw CSR_MEPC, t0
+
+    /* Pop additional registers */
+
+    /* Pop mstatus from stack and set it */
+    LOAD t0,  (RT_SAVED_REGNUM - 1)  * REGBYTES(sp)
+    csrw CSR_MSTATUS, t0
+    /* Interrupt still disable here */
+    /* Restore Registers from Stack */
+    LOAD x1,  1  * REGBYTES(sp)    /* RA */
+    LOAD x5,  2  * REGBYTES(sp)
+    LOAD x6,  3  * REGBYTES(sp)
+    LOAD x7,  4  * REGBYTES(sp)
+    LOAD x8,  5  * REGBYTES(sp)
+    LOAD x9,  6  * REGBYTES(sp)
+    LOAD x10, 7  * REGBYTES(sp)
+    LOAD x11, 8  * REGBYTES(sp)
+    LOAD x12, 9  * REGBYTES(sp)
+    LOAD x13, 10 * REGBYTES(sp)
+    LOAD x14, 11 * REGBYTES(sp)
+    LOAD x15, 12 * REGBYTES(sp)
+#ifndef __riscv_32e
+    LOAD x16, 13 * REGBYTES(sp)
+    LOAD x17, 14 * REGBYTES(sp)
+    LOAD x18, 15 * REGBYTES(sp)
+    LOAD x19, 16 * REGBYTES(sp)
+    LOAD x20, 17 * REGBYTES(sp)
+    LOAD x21, 18 * REGBYTES(sp)
+    LOAD x22, 19 * REGBYTES(sp)
+    LOAD x23, 20 * REGBYTES(sp)
+    LOAD x24, 21 * REGBYTES(sp)
+    LOAD x25, 22 * REGBYTES(sp)
+    LOAD x26, 23 * REGBYTES(sp)
+    LOAD x27, 24 * REGBYTES(sp)
+    LOAD x28, 25 * REGBYTES(sp)
+    LOAD x29, 26 * REGBYTES(sp)
+    LOAD x30, 27 * REGBYTES(sp)
+    LOAD x31, 28 * REGBYTES(sp)
+#endif
+
+    addi sp, sp, RT_CONTEXT_SIZE
+    mret
diff --git a/libcpu/risc-v/nuclei/cpuport.c b/libcpu/risc-v/nuclei/cpuport.c
new file mode 100644
index 0000000000..fad9afdf4c
--- /dev/null
+++ b/libcpu/risc-v/nuclei/cpuport.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/03/26     Huaqi        Nuclei RISC-V Core porting code.
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "cpuport.h"
+
+#define SYSTICK_TICK_CONST                      (SOC_TIMER_FREQ / RT_TICK_PER_SECOND)
+
+/* Interrupt level for kernel systimer interrupt and software timer interrupt */
+#define RT_KERNEL_INTERRUPT_LEVEL               1
+
+/* Initial CSR MSTATUS value when thread created */
+#define RT_INITIAL_MSTATUS                      (MSTATUS_MPP | MSTATUS_MPIE | MSTATUS_FS_INITIAL)
+
+/**
+ * @brief from thread used interrupt context switch
+ * 
+ */
+volatile rt_ubase_t  rt_interrupt_from_thread = 0;
+/**
+ * @brief to thread used interrupt context switch
+ * 
+ */
+volatile rt_ubase_t  rt_interrupt_to_thread   = 0;
+/**
+ * @brief flag to indicate context switch in interrupt or not
+ * 
+ */
+volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
+
+/**
+ * @brief thread stack frame of saved context
+ * 
+ */
+struct rt_hw_stack_frame
+{
+    rt_ubase_t epc;        /*!< epc - epc    - program counter                     */
+    rt_ubase_t ra;         /*!< x1  - ra     - return address for jumps            */
+    rt_ubase_t t0;         /*!< x5  - t0     - temporary register 0                */
+    rt_ubase_t t1;         /*!< x6  - t1     - temporary register 1                */
+    rt_ubase_t t2;         /*!< x7  - t2     - temporary register 2                */
+    rt_ubase_t s0_fp;      /*!< x8  - s0/fp  - saved register 0 or frame pointer   */
+    rt_ubase_t s1;         /*!< x9  - s1     - saved register 1                    */
+    rt_ubase_t a0;         /*!< x10 - a0     - return value or function argument 0 */
+    rt_ubase_t a1;         /*!< x11 - a1     - return value or function argument 1 */
+    rt_ubase_t a2;         /*!< x12 - a2     - function argument 2                 */
+    rt_ubase_t a3;         /*!< x13 - a3     - function argument 3                 */
+    rt_ubase_t a4;         /*!< x14 - a4     - function argument 4                 */
+    rt_ubase_t a5;         /*!< x15 - a5     - function argument 5                 */
+#ifndef __riscv_32e
+    rt_ubase_t a6;         /*!< x16 - a6     - function argument 6                 */
+    rt_ubase_t a7;         /*!< x17 - s7     - function argument 7                 */
+    rt_ubase_t s2;         /*!< x18 - s2     - saved register 2                    */
+    rt_ubase_t s3;         /*!< x19 - s3     - saved register 3                    */
+    rt_ubase_t s4;         /*!< x20 - s4     - saved register 4                    */
+    rt_ubase_t s5;         /*!< x21 - s5     - saved register 5                    */
+    rt_ubase_t s6;         /*!< x22 - s6     - saved register 6                    */
+    rt_ubase_t s7;         /*!< x23 - s7     - saved register 7                    */
+    rt_ubase_t s8;         /*!< x24 - s8     - saved register 8                    */
+    rt_ubase_t s9;         /*!< x25 - s9     - saved register 9                    */
+    rt_ubase_t s10;        /*!< x26 - s10    - saved register 10                   */
+    rt_ubase_t s11;        /*!< x27 - s11    - saved register 11                   */
+    rt_ubase_t t3;         /*!< x28 - t3     - temporary register 3                */
+    rt_ubase_t t4;         /*!< x29 - t4     - temporary register 4                */
+    rt_ubase_t t5;         /*!< x30 - t5     - temporary register 5                */
+    rt_ubase_t t6;         /*!< x31 - t6     - temporary register 6                */
+#endif
+    rt_ubase_t mstatus;    /*!<              - machine status register             */
+};
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void       *tentry,
+                             void       *parameter,
+                             rt_uint8_t *stack_addr,
+                             void       *texit)
+{
+    struct rt_hw_stack_frame *frame;
+    rt_uint8_t         *stk;
+    int                i;
+
+    stk  = stack_addr + sizeof(rt_ubase_t);
+    stk  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
+    stk -= sizeof(struct rt_hw_stack_frame);
+
+    frame = (struct rt_hw_stack_frame *)stk;
+
+    for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
+    {
+        ((rt_ubase_t *)frame)[i] = 0xdeadbeef;
+    }
+
+    frame->ra      = (rt_ubase_t)texit;
+    frame->a0      = (rt_ubase_t)parameter;
+    frame->epc     = (rt_ubase_t)tentry;
+
+    frame->mstatus = RT_INITIAL_MSTATUS;
+
+    return stk;
+}
+
+/**
+ * @brief Do rt-thread context switch in interrupt context
+ * 
+ * @param from thread sp of from thread
+ * @param to thread sp of to thread
+ */
+void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
+{
+    if (rt_thread_switch_interrupt_flag == 0)
+        rt_interrupt_from_thread = from;
+
+    rt_interrupt_to_thread = to;
+    rt_thread_switch_interrupt_flag = 1;
+    RT_YIELD();
+}
+
+/**
+ * @brief Do rt-thread context switch in task context
+ * 
+ * @param from thread sp of from thread
+ * @param to thread sp of to thread
+ */
+void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to)
+{
+    rt_interrupt_from_thread = from;
+    rt_interrupt_to_thread = to;
+    RT_YIELD();
+}
+
+/**
+ * @brief shutdown CPU
+ * 
+ */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
+
+/**
+ * @brief Do extra task switch code
+ * 
+ * @details
+ * 
+ * - Clear software timer interrupt request flag
+ * - clear rt_thread_switch_interrupt_flag to 0
+ */
+void rt_hw_taskswitch(void)
+{
+    /* Clear Software IRQ, A MUST */
+    SysTimer_ClearSWIRQ();
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * @brief Setup systimer and software timer interrupt
+ * 
+ * @details 
+ * 
+ * - Set Systimer interrupt as NON-VECTOR interrupt with lowest interrupt level
+ * - Set software timer interrupt as VECTOR interrupt with lowest interrupt level
+ * - Enable these two interrupts
+ */
+void rt_hw_ticksetup(void)
+{
+    uint64_t ticks = SYSTICK_TICK_CONST;
+
+    /* Make SWI and SysTick the lowest priority interrupts. */
+    /* Stop and clear the SysTimer. SysTimer as Non-Vector Interrupt */
+    SysTick_Config(ticks);
+    ECLIC_DisableIRQ(SysTimer_IRQn);
+    ECLIC_SetLevelIRQ(SysTimer_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
+    ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT);
+    ECLIC_EnableIRQ(SysTimer_IRQn);
+
+    /* Set SWI interrupt level to lowest level/priority, SysTimerSW as Vector Interrupt */
+    ECLIC_SetShvIRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT);
+    ECLIC_SetLevelIRQ(SysTimerSW_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
+    ECLIC_EnableIRQ(SysTimerSW_IRQn);
+}
+
+/**
+ * systimer interrupt handler eclic_mtip_handler
+ * is hard coded in startup_<Device>.S
+ * We define SysTick_Handler as eclic_mtip_handler
+ * for easy understanding
+ */
+#define SysTick_Handler     eclic_mtip_handler
+
+/**
+ * @brief This is the timer interrupt service routine.
+ * 
+ */
+void SysTick_Handler(void)
+{
+    /* Reload systimer */
+    SysTick_Reload(SYSTICK_TICK_CONST);
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    /* tick increase */
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief Disable cpu interrupt
+ * 
+ * @details
+ * 
+ * - Disable cpu interrupt by clear MIE bit in MSTATUS
+ * - Return the previous value in MSTATUS before clear MIE bit
+ * 
+ * @return the previous value in MSTATUS before clear MIE bit 
+ */
+rt_base_t rt_hw_interrupt_disable(void)
+{
+    return __RV_CSR_READ_CLEAR(CSR_MSTATUS, MSTATUS_MIE);
+}
+
+/**
+ * @brief Restore previous saved interrupt status
+ * 
+ * @param level previous saved MSTATUS value
+ */
+void rt_hw_interrupt_enable(rt_base_t level)
+{
+    __RV_CSR_WRITE(CSR_MSTATUS, level);
+}
diff --git a/libcpu/risc-v/nuclei/cpuport.h b/libcpu/risc-v/nuclei/cpuport.h
new file mode 100644
index 0000000000..3736f0078a
--- /dev/null
+++ b/libcpu/risc-v/nuclei/cpuport.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/03/26     hqfang       Nuclei RISC-V Core porting code.
+ */
+
+#ifndef __CPUPORT_H__
+#define __CPUPORT_H__
+
+#include <rtconfig.h>
+#include <nuclei_sdk_soc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Scheduler utilities. */
+#define RT_YIELD()                                                              \
+{                                                                               \
+    /* Set a software interrupt(SWI) request to request a context switch. */    \
+    SysTimer_SetSWIRQ();                                                        \
+    /* Barriers are normally not required but do ensure the code is completely  \
+    within the specified behaviour for the architecture. */                     \
+    __RWMB();                                                                   \
+    __FENCE_I();                                                                \
+}
+
+extern void rt_hw_ticksetup(void);
+extern void rt_hw_taskswitch(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libcpu/risc-v/nuclei/interrupt_gcc.S b/libcpu/risc-v/nuclei/interrupt_gcc.S
new file mode 100644
index 0000000000..02a3e3e760
--- /dev/null
+++ b/libcpu/risc-v/nuclei/interrupt_gcc.S
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/03/26     hqfang       First Nuclei RISC-V porting implementation
+ */
+
+#include "riscv_encoding.h"
+
+.section    .text.entry
+.align 8
+
+/**
+ * \brief  Global interrupt disabled
+ * \details
+ *  This function disable global interrupt.
+ * \remarks
+ *  - All the interrupt requests will be ignored by CPU.
+ */
+.macro DISABLE_MIE
+    csrc CSR_MSTATUS, MSTATUS_MIE
+.endm
+
+/**
+ * \brief  Macro for context save
+ * \details
+ * This macro save ABI defined caller saved registers in the stack.
+ * \remarks
+ * - This Macro could use to save context when you enter to interrupt
+ * or exception
+*/
+/* Save caller registers */
+.macro SAVE_CONTEXT
+    csrrw sp, CSR_MSCRATCHCSWL, sp
+    /* Allocate stack space for context saving */
+#ifndef __riscv_32e
+    addi sp, sp, -20*REGBYTES
+#else
+    addi sp, sp, -14*REGBYTES
+#endif /* __riscv_32e */
+
+    STORE x1, 0*REGBYTES(sp)
+    STORE x4, 1*REGBYTES(sp)
+    STORE x5, 2*REGBYTES(sp)
+    STORE x6, 3*REGBYTES(sp)
+    STORE x7, 4*REGBYTES(sp)
+    STORE x10, 5*REGBYTES(sp)
+    STORE x11, 6*REGBYTES(sp)
+    STORE x12, 7*REGBYTES(sp)
+    STORE x13, 8*REGBYTES(sp)
+    STORE x14, 9*REGBYTES(sp)
+    STORE x15, 10*REGBYTES(sp)
+#ifndef __riscv_32e
+    STORE x16, 14*REGBYTES(sp)
+    STORE x17, 15*REGBYTES(sp)
+    STORE x28, 16*REGBYTES(sp)
+    STORE x29, 17*REGBYTES(sp)
+    STORE x30, 18*REGBYTES(sp)
+    STORE x31, 19*REGBYTES(sp)
+#endif /* __riscv_32e */
+.endm
+
+/**
+ * \brief  Macro for restore caller registers
+ * \details
+ * This macro restore ABI defined caller saved registers from stack.
+ * \remarks
+ * - You could use this macro to restore context before you want return
+ * from interrupt or exeception
+ */
+/* Restore caller registers */
+.macro RESTORE_CONTEXT
+    LOAD x1, 0*REGBYTES(sp)
+    LOAD x4, 1*REGBYTES(sp)
+    LOAD x5, 2*REGBYTES(sp)
+    LOAD x6, 3*REGBYTES(sp)
+    LOAD x7, 4*REGBYTES(sp)
+    LOAD x10, 5*REGBYTES(sp)
+    LOAD x11, 6*REGBYTES(sp)
+    LOAD x12, 7*REGBYTES(sp)
+    LOAD x13, 8*REGBYTES(sp)
+    LOAD x14, 9*REGBYTES(sp)
+    LOAD x15, 10*REGBYTES(sp)
+#ifndef __riscv_32e
+    LOAD x16, 14*REGBYTES(sp)
+    LOAD x17, 15*REGBYTES(sp)
+    LOAD x28, 16*REGBYTES(sp)
+    LOAD x29, 17*REGBYTES(sp)
+    LOAD x30, 18*REGBYTES(sp)
+    LOAD x31, 19*REGBYTES(sp)
+
+    /* De-allocate the stack space */
+    addi sp, sp, 20*REGBYTES
+#else
+    /* De-allocate the stack space */
+    addi sp, sp, 14*REGBYTES
+#endif /* __riscv_32e */
+    csrrw sp, CSR_MSCRATCHCSWL, sp
+.endm
+
+/**
+ * \brief  Macro for save necessary CSRs to stack
+ * \details
+ * This macro store MCAUSE, MEPC, MSUBM to stack.
+ */
+.macro SAVE_CSR_CONTEXT
+    /* Store CSR mcause to stack using pushmcause */
+    csrrwi  x0, CSR_PUSHMCAUSE, 11
+    /* Store CSR mepc to stack using pushmepc */
+    csrrwi  x0, CSR_PUSHMEPC, 12
+    /* Store CSR msub to stack using pushmsub */
+    csrrwi  x0, CSR_PUSHMSUBM, 13
+.endm
+
+/**
+ * \brief  Macro for restore necessary CSRs from stack
+ * \details
+ * This macro restore MSUBM, MEPC, MCAUSE from stack.
+ */
+.macro RESTORE_CSR_CONTEXT
+    LOAD x5,  13*REGBYTES(sp)
+    csrw CSR_MSUBM, x5
+    LOAD x5,  12*REGBYTES(sp)
+    csrw CSR_MEPC, x5
+    LOAD x5,  11*REGBYTES(sp)
+    csrw CSR_MCAUSE, x5
+.endm
+
+/**
+ * \brief  Exception/NMI Entry
+ * \details
+ * This function provide common entry functions for exception/nmi.
+ * \remarks
+ * This function provide a default exception/nmi entry.
+ * ABI defined caller save register and some CSR registers
+ * to be saved before enter interrupt handler and be restored before return.
+ */
+.section .text.trap
+/* In CLIC mode, the exeception entry must be 64bytes aligned */
+.align 6
+.global exc_entry
+exc_entry:
+    /* Save the caller saving registers (context) */
+    SAVE_CONTEXT
+    /* Save the necessary CSR registers */
+    SAVE_CSR_CONTEXT
+
+    /*
+     * Set the exception handler function arguments
+     * argument 1: mcause value
+     * argument 2: current stack point(SP) value
+     */
+    csrr a0, mcause
+    mv a1, sp
+    /*
+     * TODO: Call the exception handler function
+     * By default, the function template is provided in
+     * system_Device.c, you can adjust it as you want
+     */
+    call core_exception_handler
+
+    /* Restore the necessary CSR registers */
+    RESTORE_CSR_CONTEXT
+    /* Restore the caller saving registers (context) */
+    RESTORE_CONTEXT
+
+    /* Return to regular code */
+    mret
+
+/**
+ * \brief  Non-Vector Interrupt Entry
+ * \details
+ * This function provide common entry functions for handling
+ * non-vector interrupts
+ * \remarks
+ * This function provide a default non-vector interrupt entry.
+ * ABI defined caller save register and some CSR registers need
+ * to be saved before enter interrupt handler and be restored before return.
+ */
+.section      .text.irq
+/* In CLIC mode, the interrupt entry must be 4bytes aligned */
+.align 2
+.global irq_entry
+/* This label will be set to MTVT2 register */
+irq_entry:
+    /* Save the caller saving registers (context) */
+    SAVE_CONTEXT
+    /* Save the necessary CSR registers */
+    SAVE_CSR_CONTEXT
+
+    /* This special CSR read/write operation, which is actually
+     * claim the CLIC to find its pending highest ID, if the ID
+     * is not 0, then automatically enable the mstatus.MIE, and
+     * jump to its vector-entry-label, and update the link register
+     */
+    csrrw ra, CSR_JALMNXTI, ra
+
+    /* Critical section with interrupts disabled */
+    DISABLE_MIE
+
+    /* Restore the necessary CSR registers */
+    RESTORE_CSR_CONTEXT
+    /* Restore the caller saving registers (context) */
+    RESTORE_CONTEXT
+
+    /* Return to regular code */
+    mret
+
+/* Default Handler for Exceptions / Interrupts */
+.global default_intexc_handler
+Undef_Handler:
+default_intexc_handler:
+1:
+	j 1b
+