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path: root/bsp/gd32450z-eval/drivers/drv_spi_flash.c
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Diffstat (limited to 'bsp/gd32450z-eval/drivers/drv_spi_flash.c')
-rw-r--r--bsp/gd32450z-eval/drivers/drv_spi_flash.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/bsp/gd32450z-eval/drivers/drv_spi_flash.c b/bsp/gd32450z-eval/drivers/drv_spi_flash.c
index ec9a3129d4..7f95d59314 100644
--- a/bsp/gd32450z-eval/drivers/drv_spi_flash.c
+++ b/bsp/gd32450z-eval/drivers/drv_spi_flash.c
@@ -28,8 +28,8 @@ static int rt_hw_spi5_init(void)
{
/* register spi bus */
{
- rt_err_t result;
-
+ rt_err_t result;
+
rcu_periph_clock_enable(RCU_GPIOG);
rcu_periph_clock_enable(RCU_SPI5);
@@ -38,36 +38,36 @@ static int rt_hw_spi5_init(void)
gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
- result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME);
+ result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME);
if (result != RT_EOK)
- {
- return result;
- }
+ {
+ return result;
+ }
}
/* attach cs */
{
static struct rt_spi_device spi_device;
static struct gd32_spi_cs spi_cs;
- rt_err_t result;
-
+ rt_err_t result;
+
spi_cs.GPIOx = GPIOG;
spi_cs.GPIO_Pin = GPIO_PIN_9;
-
+
/* SPI5_CS(PG9) GPIO pin configuration */
gpio_mode_set(GPIOG, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_PIN_9);
gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
-
+
gpio_bit_set(GPIOG,GPIO_PIN_9);
result = rt_spi_bus_attach_device(&spi_device, SPI_FLASH_DEVICE_NAME, SPI_BUS_NAME, (void*)&spi_cs);
- if (result != RT_EOK)
- {
- return result;
- }
+ if (result != RT_EOK)
+ {
+ return result;
+ }
}
- return RT_EOK;
+ return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_spi5_init);
@@ -79,7 +79,7 @@ static int rt_hw_spi_flash_with_sfud_init(void)
return RT_ERROR;
};
- return RT_EOK;
+ return RT_EOK;
}
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init)
#endif