summaryrefslogtreecommitdiff
path: root/bsp/gd32450z-eval
diff options
context:
space:
mode:
Diffstat (limited to 'bsp/gd32450z-eval')
-rw-r--r--bsp/gd32450z-eval/drivers/board.h2
-rw-r--r--bsp/gd32450z-eval/drivers/drv_enet.c72
-rw-r--r--bsp/gd32450z-eval/drivers/drv_lcd.c108
-rw-r--r--bsp/gd32450z-eval/drivers/drv_spi.c56
-rw-r--r--bsp/gd32450z-eval/drivers/drv_spi.h4
-rw-r--r--bsp/gd32450z-eval/drivers/drv_spi_flash.c32
-rw-r--r--bsp/gd32450z-eval/drivers/drv_usart.c24
-rw-r--r--bsp/gd32450z-eval/drivers/synopsys_emac.h290
8 files changed, 294 insertions, 294 deletions
diff --git a/bsp/gd32450z-eval/drivers/board.h b/bsp/gd32450z-eval/drivers/board.h
index eae2923bc9..ea7dd83acd 100644
--- a/bsp/gd32450z-eval/drivers/board.h
+++ b/bsp/gd32450z-eval/drivers/board.h
@@ -18,7 +18,7 @@
#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
// <o> Internal SRAM memory size[Kbytes] <8-64>
-// <i>Default: 64
+// <i>Default: 64
#ifdef __ICCARM__
// Use *.icf ram symbal, to avoid hardcode.
extern char __ICFEDIT_region_RAM_end__;
diff --git a/bsp/gd32450z-eval/drivers/drv_enet.c b/bsp/gd32450z-eval/drivers/drv_enet.c
index 452fce1e8a..f461b50fba 100644
--- a/bsp/gd32450z-eval/drivers/drv_enet.c
+++ b/bsp/gd32450z-eval/drivers/drv_enet.c
@@ -31,16 +31,16 @@
//#define EMAC_TX_DUMP
#ifdef EMAC_DEBUG
-#define EMAC_TRACE rt_kprintf
+#define EMAC_TRACE rt_kprintf
#else
#define EMAC_TRACE(...)
#endif
-#define EMAC_RXBUFNB 4
-#define EMAC_TXBUFNB 2
+#define EMAC_RXBUFNB 4
+#define EMAC_TXBUFNB 2
-#define EMAC_PHY_AUTO 0
-#define EMAC_PHY_10MBIT 1
+#define EMAC_PHY_AUTO 0
+#define EMAC_PHY_10MBIT 1
#define EMAC_PHY_100MBIT 2
#define MAX_ADDR_LEN 6
@@ -51,14 +51,14 @@ struct gd32_emac
rt_uint8_t phy_mode;
/* interface address info. */
- rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
+ rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
struct rt_synopsys_eth * ETHERNET_MAC;
IRQn_Type ETHER_MAC_IRQ;
-
+
EMAC_DMADESCTypeDef *DMATxDescToSet;
EMAC_DMADESCTypeDef *DMARxDescToGet;
-
+
#pragma pack(4)
EMAC_DMADESCTypeDef DMARxDscrTab[EMAC_RXBUFNB];
#pragma pack(4)
@@ -67,7 +67,7 @@ struct gd32_emac
rt_uint8_t Rx_Buff[EMAC_RXBUFNB][EMAC_MAX_PACKET_SIZE];
#pragma pack(4)
rt_uint8_t Tx_Buff[EMAC_TXBUFNB][EMAC_MAX_PACKET_SIZE];
-
+
struct rt_semaphore tx_buf_free;
};
@@ -544,14 +544,14 @@ static void enet_gpio_config(void)
rcu_periph_clock_enable(RCU_GPIOG);
rcu_periph_clock_enable(RCU_GPIOH);
rcu_periph_clock_enable(RCU_GPIOI);
-
+
gpio_af_set(GPIOA, GPIO_AF_0, GPIO_PIN_8);
gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_8);
gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_8);
-
+
/* enable SYSCFG clock */
rcu_periph_clock_enable(RCU_SYSCFG);
-
+
/* choose DIV2 to get 50MHz from 200MHz on CKOUT0 pin (PA8) to clock the PHY */
rcu_ckout0_config(RCU_CKOUT0SRC_PLLP, RCU_CKOUT0_DIV4);
syscfg_enet_phy_interface_config(SYSCFG_ENET_PHY_RMII);
@@ -559,31 +559,31 @@ static void enet_gpio_config(void)
/* PA1: ETH_RMII_REF_CLK */
gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1);
gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_1);
-
+
/* PA2: ETH_MDIO */
gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_2);
gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_2);
-
+
/* PA7: ETH_RMII_CRS_DV */
gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_7);
- gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_7);
-
+ gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_7);
+
gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_1);
gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_2);
gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_7);
-
+
/* PB11: ETH_RMII_TX_EN */
gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11);
gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_11);
-
+
/* PB12: ETH_RMII_TXD0 */
gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12);
gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_12);
-
+
/* PB13: ETH_RMII_TXD1 */
gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13);
- gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_13);
-
+ gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_13);
+
gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_11);
gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_12);
gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_13);
@@ -595,11 +595,11 @@ static void enet_gpio_config(void)
/* PC4: ETH_RMII_RXD0 */
gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4);
gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_4);
-
+
/* PC5: ETH_RMII_RXD1 */
gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5);
- gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_5);
-
+ gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_5);
+
gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_1);
gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_4);
gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_5);
@@ -609,17 +609,17 @@ static void enet_gpio_config(void)
int rt_hw_gd32_eth_init(void)
{
rt_kprintf("rt_gd32_eth_init...\n");
-
+
/* enable ethernet clock */
rcu_periph_clock_enable(RCU_ENET);
rcu_periph_clock_enable(RCU_ENETTX);
rcu_periph_clock_enable(RCU_ENETRX);
-
+
nvic_configuration();
-
+
/* configure the GPIO ports for ethernet pins */
enet_gpio_config();
-
+
/* set autonegotiation mode */
gd32_emac_device0.phy_mode = EMAC_PHY_AUTO;
gd32_emac_device0.ETHERNET_MAC = ETHERNET_MAC0;
@@ -634,16 +634,16 @@ int rt_hw_gd32_eth_init(void)
gd32_emac_device0.dev_addr[4] = 0x34;
gd32_emac_device0.dev_addr[5] = 0x56;
- gd32_emac_device0.parent.parent.init = gd32_emac_init;
- gd32_emac_device0.parent.parent.open = gd32_emac_open;
- gd32_emac_device0.parent.parent.close = gd32_emac_close;
- gd32_emac_device0.parent.parent.read = gd32_emac_read;
- gd32_emac_device0.parent.parent.write = gd32_emac_write;
- gd32_emac_device0.parent.parent.control = gd32_emac_control;
+ gd32_emac_device0.parent.parent.init = gd32_emac_init;
+ gd32_emac_device0.parent.parent.open = gd32_emac_open;
+ gd32_emac_device0.parent.parent.close = gd32_emac_close;
+ gd32_emac_device0.parent.parent.read = gd32_emac_read;
+ gd32_emac_device0.parent.parent.write = gd32_emac_write;
+ gd32_emac_device0.parent.parent.control = gd32_emac_control;
gd32_emac_device0.parent.parent.user_data = RT_NULL;
- gd32_emac_device0.parent.eth_rx = gd32_emac_rx;
- gd32_emac_device0.parent.eth_tx = gd32_emac_tx;
+ gd32_emac_device0.parent.eth_rx = gd32_emac_rx;
+ gd32_emac_device0.parent.eth_tx = gd32_emac_tx;
/* init tx buffer free semaphore */
rt_sem_init(&gd32_emac_device0.tx_buf_free, "tx_buf0", EMAC_TXBUFNB, RT_IPC_FLAG_FIFO);
diff --git a/bsp/gd32450z-eval/drivers/drv_lcd.c b/bsp/gd32450z-eval/drivers/drv_lcd.c
index 714be9276c..3cbae2ac84 100644
--- a/bsp/gd32450z-eval/drivers/drv_lcd.c
+++ b/bsp/gd32450z-eval/drivers/drv_lcd.c
@@ -37,7 +37,7 @@ static struct rt_device_graphic_info _lcd_info;
static struct rt_device lcd;
/*!
- \brief configure TLI GPIO
+ \brief configure TLI GPIO
\param[in] none
\param[out] none
\retval none
@@ -53,34 +53,34 @@ static void tli_gpio_config(void)
rcu_periph_clock_enable(RCU_GPIOG);
/* configure HSYNC(PC6), VSYNC(PA4), PCLK(PG7), DE(PF10) */
- /* configure LCD_R7(PG6), LCD_R6(PA8), LCD_R5(PA12), LCD_R4(PA11), LCD_R3(PB0),
+ /* configure LCD_R7(PG6), LCD_R6(PA8), LCD_R5(PA12), LCD_R4(PA11), LCD_R3(PB0),
LCD_G7(PD3), LCD_G6(PC7), LCD_G5(PB11), LCD_G4(PB10), LCD_G3(PG10), LCD_G2(PA6),
LCD_B7(PB9), LCD_B6(PB8), LCD_B5(PA3), LCD_B4(PG12), LCD_B3(PG11) */
- gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_3);
+ gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_3);
gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_4);
- gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_6);
- gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_12);
- gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_11);
- gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_8);
-
- gpio_af_set(GPIOB,GPIO_AF_9,GPIO_PIN_0);
- gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_10);
+ gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_6);
+ gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_12);
+ gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_11);
+ gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_8);
+
+ gpio_af_set(GPIOB,GPIO_AF_9,GPIO_PIN_0);
+ gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_10);
//gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_11);
- gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_8);
+ gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_8);
gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_9);
-
- gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_6);
+
+ gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_6);
gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_7);
-
- gpio_af_set(GPIOD,GPIO_AF_14,GPIO_PIN_3);
- gpio_af_set(GPIOF,GPIO_AF_14,GPIO_PIN_10);
-
- gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_6);
+ gpio_af_set(GPIOD,GPIO_AF_14,GPIO_PIN_3);
+
+ gpio_af_set(GPIOF,GPIO_AF_14,GPIO_PIN_10);
+
+ gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_6);
gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_7);
gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_10);
- gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_11);
- gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_12);
+ gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_11);
+ gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_12);
gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_6
|GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12);
@@ -119,15 +119,15 @@ static void lcd_config(void)
lcd_ctrl_line_config();
lcd_disable();
lcd_enable();
-
+
/* configure the GPIO of TLI */
tli_gpio_config();
/* configure the LCD_SPI */
- lcd_spi_config();
+ lcd_spi_config();
/* power on the LCD */
//lcd_power_on();
- lcd_power_on3(); //New Version 3.5" TFT RGB Hardware needs use this initilize funtion ---By xufei 2016.10.21
+ lcd_power_on3(); //New Version 3.5" TFT RGB Hardware needs use this initilize funtion ---By xufei 2016.10.21
}
/*!
@@ -140,7 +140,7 @@ static void tli_config(void)
{
tli_parameter_struct tli_init_struct;
tli_layer_parameter_struct tli_layer_init_struct;
-
+
rcu_periph_clock_enable(RCU_TLI);
/* configure the PLLSAI clock to generate lcd clock */
@@ -152,52 +152,52 @@ static void tli_config(void)
if(ERROR == rcu_osci_stab_wait(RCU_PLLSAI_CK)){
while(1);
}
-
+
/* TLI initialization */
tli_init_struct.signalpolarity_hs = TLI_HSYN_ACTLIVE_LOW;
tli_init_struct.signalpolarity_vs = TLI_VSYN_ACTLIVE_LOW;
tli_init_struct.signalpolarity_de = TLI_DE_ACTLIVE_LOW;
tli_init_struct.signalpolarity_pixelck = TLI_PIXEL_CLOCK_TLI;
-
+
/* LCD display timing configuration */
tli_init_struct.synpsz_hpsz = LCD_480_320_HSYNC;
tli_init_struct.synpsz_vpsz = LCD_480_320_VSYNC;
- tli_init_struct.backpsz_hbpsz = LCD_480_320_HSYNC + LCD_480_320_HBP;
- tli_init_struct.backpsz_vbpsz = LCD_480_320_VSYNC + LCD_480_320_VBP;
+ tli_init_struct.backpsz_hbpsz = LCD_480_320_HSYNC + LCD_480_320_HBP;
+ tli_init_struct.backpsz_vbpsz = LCD_480_320_VSYNC + LCD_480_320_VBP;
tli_init_struct.activesz_hasz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP;
tli_init_struct.activesz_vasz = RT_HW_LCD_HEIGHT + LCD_480_320_VSYNC + LCD_480_320_VBP;
- tli_init_struct.totalsz_htsz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP + LCD_480_320_HFP;
+ tli_init_struct.totalsz_htsz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP + LCD_480_320_HFP;
tli_init_struct.totalsz_vtsz = RT_HW_LCD_HEIGHT + LCD_480_320_VSYNC + LCD_480_320_VBP + LCD_480_320_VFP;
-
+
/* LCD background color configure*/
tli_init_struct.backcolor_red = 0x00;
tli_init_struct.backcolor_green = 0x00;
- tli_init_struct.backcolor_blue = 0x00;
+ tli_init_struct.backcolor_blue = 0x00;
tli_init(&tli_init_struct);
-
+
lcd_framebuffer = rt_malloc(sizeof(rt_uint16_t) * RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH);
RT_ASSERT(lcd_framebuffer != NULL);
rt_memset(lcd_framebuffer, 0, sizeof(rt_uint16_t) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT);
/* TLI layer0 configuration */
tli_layer_init_struct.layer_window_leftpos = tli_init_struct.backpsz_hbpsz + 1;
- tli_layer_init_struct.layer_window_rightpos = tli_init_struct.backpsz_hbpsz + RT_HW_LCD_WIDTH;
+ tli_layer_init_struct.layer_window_rightpos = tli_init_struct.backpsz_hbpsz + RT_HW_LCD_WIDTH;
tli_layer_init_struct.layer_window_toppos = tli_init_struct.backpsz_vbpsz + 1;
tli_layer_init_struct.layer_window_bottompos = tli_init_struct.backpsz_vbpsz + RT_HW_LCD_HEIGHT;
-
+
tli_layer_init_struct.layer_ppf = LAYER_PPF_RGB565;
tli_layer_init_struct.layer_sa = 0xFF;
- tli_layer_init_struct.layer_default_blue = 0x00;
- tli_layer_init_struct.layer_default_green = 0x00;
- tli_layer_init_struct.layer_default_red = 0x00;
+ tli_layer_init_struct.layer_default_blue = 0x00;
+ tli_layer_init_struct.layer_default_green = 0x00;
+ tli_layer_init_struct.layer_default_red = 0x00;
tli_layer_init_struct.layer_default_alpha = 0x00;
- tli_layer_init_struct.layer_acf1 = LAYER_ACF1_PASA;
+ tli_layer_init_struct.layer_acf1 = LAYER_ACF1_PASA;
tli_layer_init_struct.layer_acf2 = LAYER_ACF2_PASA;
- tli_layer_init_struct.layer_frame_bufaddr = (uint32_t)lcd_framebuffer;
- tli_layer_init_struct.layer_frame_line_length = ((RT_HW_LCD_WIDTH * 2) + 3);
+ tli_layer_init_struct.layer_frame_bufaddr = (uint32_t)lcd_framebuffer;
+ tli_layer_init_struct.layer_frame_line_length = ((RT_HW_LCD_WIDTH * 2) + 3);
tli_layer_init_struct.layer_frame_buf_stride_offset = (RT_HW_LCD_WIDTH * 2);
- tli_layer_init_struct.layer_frame_total_line_number = RT_HW_LCD_HEIGHT;
-
+ tli_layer_init_struct.layer_frame_total_line_number = RT_HW_LCD_HEIGHT;
+
tli_layer_init(LAYER0, &tli_layer_init_struct);
}
@@ -206,21 +206,21 @@ static rt_err_t rt_lcd_control(rt_device_t dev, int cmd, void *args)
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
- {
+ {
memcpy((void *)lcd_framebuffer, _rt_framebuffer, sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH);
}
break;
-
+
case RTGRAPHIC_CTRL_POWERON:
break;
-
+
case RTGRAPHIC_CTRL_POWEROFF:
break;
-
+
case RTGRAPHIC_CTRL_GET_INFO:
memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
-
+
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
@@ -231,21 +231,21 @@ static rt_err_t rt_lcd_control(rt_device_t dev, int cmd, void *args)
int gd32_hw_lcd_init(void)
{
_rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT, 32);
- if (_rt_framebuffer == RT_NULL)
+ if (_rt_framebuffer == RT_NULL)
return -1; /* no memory yet */
-
+
lcd_config();
tli_config();
- tli_layer_enable(LAYER0);
+ tli_layer_enable(LAYER0);
tli_reload_config(TLI_FRAME_BLANK_RELOAD_EN);
tli_enable();
-
+
_lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
_lcd_info.framebuffer = (void *)_rt_framebuffer;
_lcd_info.width = RT_HW_LCD_WIDTH;
_lcd_info.height = RT_HW_LCD_HEIGHT;
-
+
lcd.type = RT_Device_Class_Graphic;
lcd.init = NULL;
lcd.open = NULL;
@@ -254,10 +254,10 @@ int gd32_hw_lcd_init(void)
lcd.write = NULL;
lcd.control = rt_lcd_control;
lcd.user_data = (void *)&_lcd_info;
-
+
/* register lcd device to RT-Thread */
rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR);
-
+
return 0;
}
INIT_DEVICE_EXPORT(gd32_hw_lcd_init);
diff --git a/bsp/gd32450z-eval/drivers/drv_spi.c b/bsp/gd32450z-eval/drivers/drv_spi.c
index cb73a210e0..acd4f7198f 100644
--- a/bsp/gd32450z-eval/drivers/drv_spi.c
+++ b/bsp/gd32450z-eval/drivers/drv_spi.c
@@ -7,7 +7,7 @@
* Date Author Notes
* 2017-06-05 tanek first implementation.
*/
-
+
#include "drv_spi.h"
#include <board.h>
@@ -28,7 +28,7 @@
#ifdef DEBUG
#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
#else
-#define DEBUG_PRINTF(...)
+#define DEBUG_PRINTF(...)
#endif
/* private rt-thread spi ops function */
@@ -44,16 +44,16 @@ static struct rt_spi_ops gd32_spi_ops =
static rt_err_t configure(struct rt_spi_device* device,
struct rt_spi_configuration* configuration)
{
- struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;
+ struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;
struct gd32f4_spi *f4_spi = (struct gd32f4_spi *)spi_bus->parent.user_data;
-
+
spi_parameter_struct spi_init_struct;
uint32_t spi_periph = f4_spi->spi_periph;
- RT_ASSERT(device != RT_NULL);
- RT_ASSERT(configuration != RT_NULL);
+ RT_ASSERT(device != RT_NULL);
+ RT_ASSERT(configuration != RT_NULL);
/* data_width */
if(configuration->data_width <= 8)
@@ -125,7 +125,7 @@ static rt_err_t configure(struct rt_spi_device* device,
spi_init_struct.prescale = SPI_PSC_256;
}
} /* baudrate */
-
+
switch(configuration->mode & RT_SPI_MODE_3)
{
case RT_SPI_MODE_0:
@@ -133,15 +133,15 @@ static rt_err_t configure(struct rt_spi_device* device,
break;
case RT_SPI_MODE_1:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE;
- break;
+ break;
case RT_SPI_MODE_2:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE;
- break;
+ break;
case RT_SPI_MODE_3:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
break;
}
-
+
/* MSB or LSB */
if(configuration->mode & RT_SPI_MSB)
{
@@ -151,18 +151,18 @@ static rt_err_t configure(struct rt_spi_device* device,
{
spi_init_struct.endian = SPI_ENDIAN_LSB;
}
-
+
spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
spi_init_struct.device_mode = SPI_MASTER;
spi_init_struct.nss = SPI_NSS_SOFT;
-
+
spi_crc_off(spi_periph);
/* init SPI */
spi_init(spi_periph, &spi_init_struct);
/* Enable SPI_MASTER */
- spi_enable(spi_periph);
-
+ spi_enable(spi_periph);
+
return RT_EOK;
};
@@ -174,9 +174,9 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
struct gd32_spi_cs * gd32_spi_cs = device->parent.user_data;
uint32_t spi_periph = f4_spi->spi_periph;
- RT_ASSERT(device != NULL);
- RT_ASSERT(message != NULL);
-
+ RT_ASSERT(device != NULL);
+ RT_ASSERT(message != NULL);
+
/* take CS */
if(message->cs_take)
{
@@ -190,7 +190,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
const rt_uint8_t * send_ptr = message->send_buf;
rt_uint8_t * recv_ptr = message->recv_buf;
rt_uint32_t size = message->length;
-
+
DEBUG_PRINTF("spi poll transfer start: %d\n", size);
while(size--)
@@ -201,12 +201,12 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
{
data = *send_ptr++;
}
-
+
// Todo: replace register read/write by gd32f4 lib
//Wait until the transmit buffer is empty
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
// Send the byte
- spi_i2s_data_transmit(spi_periph, data);
+ spi_i2s_data_transmit(spi_periph, data);
//Wait until a data is received
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
@@ -238,7 +238,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
//Wait until the transmit buffer is empty
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
// Send the byte
- spi_i2s_data_transmit(spi_periph, data);
+ spi_i2s_data_transmit(spi_periph, data);
//Wait until a data is received
while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
@@ -256,7 +256,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
/* release CS */
if(message->cs_release)
{
- gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin);
+ gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin);
DEBUG_PRINTF("spi release cs\n");
}
@@ -270,7 +270,7 @@ static const struct gd32f4_spi spis[] = {
#ifdef RT_USING_SPI0
{SPI0, RCU_SPI0, &spi_bus[0]},
#endif
-
+
#ifdef RT_USING_SPI1
{SPI1, RCU_SPI1, &spi_bus[1]},
#endif
@@ -282,11 +282,11 @@ static const struct gd32f4_spi spis[] = {
#ifdef RT_USING_SPI3
{SPI3, RCU_SPI3, &spi_bus[3]},
#endif
-
+
#ifdef RT_USING_SPI4
{SPI4, RCU_SPI4, &spi_bus[4]},
#endif
-
+
#ifdef RT_USING_SPI5
{SPI5, RCU_SPI5, &spi_bus[5]},
#endif
@@ -306,9 +306,9 @@ rt_err_t gd32_spi_bus_register(uint32_t spi_periph,
const char * spi_bus_name)
{
int i;
-
+
RT_ASSERT(spi_bus_name != RT_NULL);
-
+
for (i = 0; i < ARR_LEN(spis); i++)
{
if (spi_periph == spis[i].spi_periph)
@@ -319,7 +319,7 @@ rt_err_t gd32_spi_bus_register(uint32_t spi_periph,
return RT_EOK;
}
}
-
+
return RT_ERROR;
}
#endif
diff --git a/bsp/gd32450z-eval/drivers/drv_spi.h b/bsp/gd32450z-eval/drivers/drv_spi.h
index e9db6df080..51bae441ca 100644
--- a/bsp/gd32450z-eval/drivers/drv_spi.h
+++ b/bsp/gd32450z-eval/drivers/drv_spi.h
@@ -32,7 +32,7 @@ struct gd32_spi_cs
/* public function */
rt_err_t gd32_spi_bus_register(uint32_t spi_periph,
- //struct gd32_spi_bus * gd32_spi,
- const char * spi_bus_name);
+ //struct gd32_spi_bus * gd32_spi,
+ const char * spi_bus_name);
#endif // gd32F20X_40X_SPI_H_INCLUDED
diff --git a/bsp/gd32450z-eval/drivers/drv_spi_flash.c b/bsp/gd32450z-eval/drivers/drv_spi_flash.c
index ec9a3129d4..7f95d59314 100644
--- a/bsp/gd32450z-eval/drivers/drv_spi_flash.c
+++ b/bsp/gd32450z-eval/drivers/drv_spi_flash.c
@@ -28,8 +28,8 @@ static int rt_hw_spi5_init(void)
{
/* register spi bus */
{
- rt_err_t result;
-
+ rt_err_t result;
+
rcu_periph_clock_enable(RCU_GPIOG);
rcu_periph_clock_enable(RCU_SPI5);
@@ -38,36 +38,36 @@ static int rt_hw_spi5_init(void)
gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
- result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME);
+ result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME);
if (result != RT_EOK)
- {
- return result;
- }
+ {
+ return result;
+ }
}
/* attach cs */
{
static struct rt_spi_device spi_device;
static struct gd32_spi_cs spi_cs;
- rt_err_t result;
-
+ rt_err_t result;
+
spi_cs.GPIOx = GPIOG;
spi_cs.GPIO_Pin = GPIO_PIN_9;
-
+
/* SPI5_CS(PG9) GPIO pin configuration */
gpio_mode_set(GPIOG, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_PIN_9);
gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
-
+
gpio_bit_set(GPIOG,GPIO_PIN_9);
result = rt_spi_bus_attach_device(&spi_device, SPI_FLASH_DEVICE_NAME, SPI_BUS_NAME, (void*)&spi_cs);
- if (result != RT_EOK)
- {
- return result;
- }
+ if (result != RT_EOK)
+ {
+ return result;
+ }
}
- return RT_EOK;
+ return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_spi5_init);
@@ -79,7 +79,7 @@ static int rt_hw_spi_flash_with_sfud_init(void)
return RT_ERROR;
};
- return RT_EOK;
+ return RT_EOK;
}
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init)
#endif
diff --git a/bsp/gd32450z-eval/drivers/drv_usart.c b/bsp/gd32450z-eval/drivers/drv_usart.c
index 216b022159..fa691a42b9 100644
--- a/bsp/gd32450z-eval/drivers/drv_usart.c
+++ b/bsp/gd32450z-eval/drivers/drv_usart.c
@@ -33,7 +33,7 @@
struct gd32_uart
{
uint32_t uart_periph; //Todo: 3bits
- IRQn_Type irqn; //Todo: 7bits
+ IRQn_Type irqn; //Todo: 7bits
rcu_periph_enum per_clk; //Todo: 5bits
rcu_periph_enum tx_gpio_clk; //Todo: 5bits
rcu_periph_enum rx_gpio_clk; //Todo: 5bits
@@ -44,7 +44,7 @@ struct gd32_uart
uint16_t rx_af; //Todo: 4bits
uint16_t rx_pin; //Todo: 4bits
- struct rt_serial_device * serial;
+ struct rt_serial_device * serial;
char *device_name;
};
@@ -189,7 +189,7 @@ static const struct gd32_uart uarts[] = {
"uart0",
},
#endif
-
+
#ifdef BSP_USING_UART1
{
USART1, // uart peripheral index
@@ -201,7 +201,7 @@ static const struct gd32_uart uarts[] = {
"uart1",
},
#endif
-
+
#ifdef BSP_USING_UART2
{
USART2, // uart peripheral index
@@ -213,7 +213,7 @@ static const struct gd32_uart uarts[] = {
"uart2",
},
#endif
-
+
#ifdef BSP_USING_UART3
{
UART3, // uart peripheral index
@@ -225,7 +225,7 @@ static const struct gd32_uart uarts[] = {
"uart3",
},
#endif
-
+
#ifdef BSP_USING_UART4
{
UART4, // uart peripheral index
@@ -249,7 +249,7 @@ static const struct gd32_uart uarts[] = {
"uart5",
},
#endif
-
+
#ifdef BSP_USING_UART6
{
UART6, // uart peripheral index
@@ -305,7 +305,7 @@ void gd32_uart_gpio_init(struct gd32_uart *uart)
/* configure USART Rx as alternate function push-pull */
gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->rx_pin);
gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, uart->rx_pin);
-
+
NVIC_SetPriority(uart->irqn, 0);
NVIC_EnableIRQ(uart->irqn);
}
@@ -318,9 +318,9 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_co
RT_ASSERT(cfg != RT_NULL);
uart = (struct gd32_uart *)serial->parent.user_data;
-
+
gd32_uart_gpio_init(uart);
-
+
usart_baudrate_set(uart->uart_periph, cfg->baud_rate);
switch (cfg->data_bits)
@@ -400,7 +400,7 @@ static int gd32_putc(struct rt_serial_device *serial, char ch)
usart_data_transmit(uart->uart_periph, ch);
while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET));
-
+
return 1;
}
@@ -452,7 +452,7 @@ int gd32_hw_usart_init(void)
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
int i;
-
+
for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
{
uarts[i].serial->ops = &gd32_uart_ops;
diff --git a/bsp/gd32450z-eval/drivers/synopsys_emac.h b/bsp/gd32450z-eval/drivers/synopsys_emac.h
index 87e03fa1b4..f6c303ce7f 100644
--- a/bsp/gd32450z-eval/drivers/synopsys_emac.h
+++ b/bsp/gd32450z-eval/drivers/synopsys_emac.h
@@ -8,7 +8,7 @@
#define __SYNOPSYS_EMAC_H__
#include <rtthread.h>
-
+
/******************************************************************************/
/* Ethernet MAC Registers bits definitions */
@@ -34,8 +34,8 @@
#define EMAC_MACCR_RD ((rt_uint32_t)0x00000200) /* Retry disable */
#define EMAC_MACCR_APCS ((rt_uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
#define EMAC_MACCR_BL ((rt_uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
- a transmission attempt during retries after a collision: 0 =< r <2^k */
-#define EMAC_MACCR_BL_10 ((rt_uint32_t)0x00000000) /* k = min (n, 10) */
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define EMAC_MACCR_BL_10 ((rt_uint32_t)0x00000000) /* k = min (n, 10) */
#define EMAC_MACCR_BL_8 ((rt_uint32_t)0x00000020) /* k = min (n, 8) */
#define EMAC_MACCR_BL_4 ((rt_uint32_t)0x00000040) /* k = min (n, 4) */
#define EMAC_MACCR_BL_1 ((rt_uint32_t)0x00000060) /* k = min (n, 1) */
@@ -46,45 +46,45 @@
/* Bit definition for Ethernet MAC Frame Filter Register */
#define EMAC_MACFFR_RA ((rt_uint32_t)0x80000000) /* Receive all */
#define EMAC_MACFFR_HPF ((rt_uint32_t)0x00000400) /* Hash or perfect filter */
-#define EMAC_MACFFR_SAF ((rt_uint32_t)0x00000200) /* Source address filter enable */
+#define EMAC_MACFFR_SAF ((rt_uint32_t)0x00000200) /* Source address filter enable */
#define EMAC_MACFFR_SAIF ((rt_uint32_t)0x00000100) /* SA inverse filtering */
#define EMAC_MACFFR_PCF ((rt_uint32_t)0x000000C0) /* Pass control frames: 3 cases */
#define EMAC_MACFFR_PCF_BlockAll ((rt_uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
#define EMAC_MACFFR_PCF_ForwardAll ((rt_uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
#define EMAC_MACFFR_PCF_ForwardPassedAddrFilter ((rt_uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
#define EMAC_MACFFR_BFD ((rt_uint32_t)0x00000020) /* Broadcast frame disable */
-#define EMAC_MACFFR_PAM ((rt_uint32_t)0x00000010) /* Pass all mutlicast */
+#define EMAC_MACFFR_PAM ((rt_uint32_t)0x00000010) /* Pass all mutlicast */
#define EMAC_MACFFR_DAIF ((rt_uint32_t)0x00000008) /* DA Inverse filtering */
-#define EMAC_MACFFR_HM ((rt_uint32_t)0x00000004) /* Hash multicast */
-#define EMAC_MACFFR_HU ((rt_uint32_t)0x00000002) /* Hash unicast */
-#define EMAC_MACFFR_PM ((rt_uint32_t)0x00000001) /* Promiscuous mode */
+#define EMAC_MACFFR_HM ((rt_uint32_t)0x00000004) /* Hash multicast */
+#define EMAC_MACFFR_HU ((rt_uint32_t)0x00000002) /* Hash unicast */
+#define EMAC_MACFFR_PM ((rt_uint32_t)0x00000001) /* Promiscuous mode */
/* Bit definition for Ethernet MAC Hash Table High Register */
-#define EMAC_MACHTHR_HTH ((rt_uint32_t)0xFFFFFFFF) /* Hash table high */
+#define EMAC_MACHTHR_HTH ((rt_uint32_t)0xFFFFFFFF) /* Hash table high */
/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define EMAC_MACHTLR_HTL ((rt_uint32_t)0xFFFFFFFF) /* Hash table low */
+#define EMAC_MACHTLR_HTL ((rt_uint32_t)0xFFFFFFFF) /* Hash table low */
/* Bit definition for Ethernet MAC MII Address Register */
-#define EMAC_MACMIIAR_PA ((rt_uint32_t)0x0000F800) /* Physical layer address */
-#define EMAC_MACMIIAR_MR ((rt_uint32_t)0x000007C0) /* MII register in the selected PHY */
-#define EMAC_MACMIIAR_CR ((rt_uint32_t)0x0000001C) /* CR clock range: 6 cases */
+#define EMAC_MACMIIAR_PA ((rt_uint32_t)0x0000F800) /* Physical layer address */
+#define EMAC_MACMIIAR_MR ((rt_uint32_t)0x000007C0) /* MII register in the selected PHY */
+#define EMAC_MACMIIAR_CR ((rt_uint32_t)0x0000001C) /* CR clock range: 6 cases */
#define EMAC_MACMIIAR_CR_Div42 ((rt_uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
#define EMAC_MACMIIAR_CR_Div62 ((rt_uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
#define EMAC_MACMIIAR_CR_Div16 ((rt_uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
#define EMAC_MACMIIAR_CR_Div26 ((rt_uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
#define EMAC_MACMIIAR_CR_Div102 ((rt_uint32_t)0x00000010) /* HCLK:150-250 MHz; MDC clock= HCLK/102 */
#define EMAC_MACMIIAR_CR_Div122 ((rt_uint32_t)0x00000014) /* HCLK:250-300 MHz; MDC clock= HCLK/122*/
-#define EMAC_MACMIIAR_MW ((rt_uint32_t)0x00000002) /* MII write */
-#define EMAC_MACMIIAR_MB ((rt_uint32_t)0x00000001) /* MII busy */
+#define EMAC_MACMIIAR_MW ((rt_uint32_t)0x00000002) /* MII write */
+#define EMAC_MACMIIAR_MB ((rt_uint32_t)0x00000001) /* MII busy */
/* Bit definition for Ethernet MAC MII Data Register */
-#define EMAC_MACMIIDR_MD ((rt_uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
+#define EMAC_MACMIIDR_MD ((rt_uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
/* Bit definition for Ethernet MAC Flow Control Register */
-#define EMAC_MACFCR_PT ((rt_uint32_t)0xFFFF0000) /* Pause time */
-#define EMAC_MACFCR_ZQPD ((rt_uint32_t)0x00000080) /* Zero-quanta pause disable */
-#define EMAC_MACFCR_PLT ((rt_uint32_t)0x00000030) /* Pause low threshold: 4 cases */
+#define EMAC_MACFCR_PT ((rt_uint32_t)0xFFFF0000) /* Pause time */
+#define EMAC_MACFCR_ZQPD ((rt_uint32_t)0x00000080) /* Zero-quanta pause disable */
+#define EMAC_MACFCR_PLT ((rt_uint32_t)0x00000030) /* Pause low threshold: 4 cases */
#define EMAC_MACFCR_PLT_Minus4 ((rt_uint32_t)0x00000000) /* Pause time minus 4 slot times */
#define EMAC_MACFCR_PLT_Minus28 ((rt_uint32_t)0x00000010) /* Pause time minus 28 slot times */
#define EMAC_MACFCR_PLT_Minus144 ((rt_uint32_t)0x00000020) /* Pause time minus 144 slot times */
@@ -427,7 +427,7 @@
#define EMAC_DMACHRBAR_HRBAP ((rt_uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
//typedef enum {
-// RESET = 0, SET = !RESET
+// RESET = 0, SET = !RESET
//} FlagStatus, ITStatus;
//typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
@@ -436,165 +436,165 @@
*/
typedef struct
{
- /**
- * MAC
- */
- rt_uint32_t EMAC_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY
- The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
- and the mode (half/full-duplex).
- This parameter can be a value of @ref EMAC_AutoNegotiation */
+ /**
+ * MAC
+ */
+ rt_uint32_t EMAC_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY
+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+ and the mode (half/full-duplex).
+ This parameter can be a value of @ref EMAC_AutoNegotiation */
- rt_uint32_t EMAC_Watchdog; /* Selects or not the Watchdog timer
- When enabled, the MAC allows no more then 2048 bytes to be received.
- When disabled, the MAC can receive up to 16384 bytes.
- This parameter can be a value of @ref EMAC_watchdog */
+ rt_uint32_t EMAC_Watchdog; /* Selects or not the Watchdog timer
+ When enabled, the MAC allows no more then 2048 bytes to be received.
+ When disabled, the MAC can receive up to 16384 bytes.
+ This parameter can be a value of @ref EMAC_watchdog */
- rt_uint32_t EMAC_Jabber; /* Selects or not Jabber timer
- When enabled, the MAC allows no more then 2048 bytes to be sent.
- When disabled, the MAC can send up to 16384 bytes.
- This parameter can be a value of @ref EMAC_Jabber */
+ rt_uint32_t EMAC_Jabber; /* Selects or not Jabber timer
+ When enabled, the MAC allows no more then 2048 bytes to be sent.
+ When disabled, the MAC can send up to 16384 bytes.
+ This parameter can be a value of @ref EMAC_Jabber */
- rt_uint32_t EMAC_InterFrameGap; /* Selects the minimum IFG between frames during transmission
- This parameter can be a value of @ref EMAC_Inter_Frame_Gap */
+ rt_uint32_t EMAC_InterFrameGap; /* Selects the minimum IFG between frames during transmission
+ This parameter can be a value of @ref EMAC_Inter_Frame_Gap */
- rt_uint32_t EMAC_CarrierSense; /* Selects or not the Carrier Sense
- This parameter can be a value of @ref EMAC_Carrier_Sense */
+ rt_uint32_t EMAC_CarrierSense; /* Selects or not the Carrier Sense
+ This parameter can be a value of @ref EMAC_Carrier_Sense */
- rt_uint32_t EMAC_Speed; /* Sets the Ethernet speed: 10/100 Mbps
- This parameter can be a value of @ref EMAC_Speed */
+ rt_uint32_t EMAC_Speed; /* Sets the Ethernet speed: 10/100 Mbps
+ This parameter can be a value of @ref EMAC_Speed */
- rt_uint32_t EMAC_ReceiveOwn; /* Selects or not the ReceiveOwn
- ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
- in Half-Duplex mode
- This parameter can be a value of @ref EMAC_Receive_Own */
+ rt_uint32_t EMAC_ReceiveOwn; /* Selects or not the ReceiveOwn
+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+ in Half-Duplex mode
+ This parameter can be a value of @ref EMAC_Receive_Own */
- rt_uint32_t EMAC_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode
- This parameter can be a value of @ref EMAC_Loop_Back_Mode */
+ rt_uint32_t EMAC_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode
+ This parameter can be a value of @ref EMAC_Loop_Back_Mode */
- rt_uint32_t EMAC_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
- This parameter can be a value of @ref EMAC_Duplex_Mode */
+ rt_uint32_t EMAC_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+ This parameter can be a value of @ref EMAC_Duplex_Mode */
- rt_uint32_t EMAC_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
- This parameter can be a value of @ref EMAC_Checksum_Offload */
+ rt_uint32_t EMAC_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+ This parameter can be a value of @ref EMAC_Checksum_Offload */
- rt_uint32_t EMAC_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL,
- when a colision occurs (Half-Duplex mode)
- This parameter can be a value of @ref EMAC_Retry_Transmission */
+ rt_uint32_t EMAC_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL,
+ when a colision occurs (Half-Duplex mode)
+ This parameter can be a value of @ref EMAC_Retry_Transmission */
- rt_uint32_t EMAC_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping
- This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */
+ rt_uint32_t EMAC_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping
+ This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */
- rt_uint32_t EMAC_BackOffLimit; /* Selects the BackOff limit value
- This parameter can be a value of @ref EMAC_Back_Off_Limit */
+ rt_uint32_t EMAC_BackOffLimit; /* Selects the BackOff limit value
+ This parameter can be a value of @ref EMAC_Back_Off_Limit */
- rt_uint32_t EMAC_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode)
- This parameter can be a value of @ref EMAC_Deferral_Check */
+ rt_uint32_t EMAC_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode)
+ This parameter can be a value of @ref EMAC_Deferral_Check */
- rt_uint32_t EMAC_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering)
- This parameter can be a value of @ref EMAC_Receive_All */
+ rt_uint32_t EMAC_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering)
+ This parameter can be a value of @ref EMAC_Receive_All */
- rt_uint32_t EMAC_SourceAddrFilter; /* Selects the Source Address Filter mode
- This parameter can be a value of @ref EMAC_Source_Addr_Filter */
+ rt_uint32_t EMAC_SourceAddrFilter; /* Selects the Source Address Filter mode
+ This parameter can be a value of @ref EMAC_Source_Addr_Filter */
- rt_uint32_t EMAC_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
- This parameter can be a value of @ref EMAC_Pass_Control_Frames */
+ rt_uint32_t EMAC_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+ This parameter can be a value of @ref EMAC_Pass_Control_Frames */
- rt_uint32_t EMAC_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames
- This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */
+ rt_uint32_t EMAC_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames
+ This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */
- rt_uint32_t EMAC_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames
- This parameter can be a value of @ref EMAC_Destination_Addr_Filter */
+ rt_uint32_t EMAC_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames
+ This parameter can be a value of @ref EMAC_Destination_Addr_Filter */
- rt_uint32_t EMAC_PromiscuousMode; /* Selects or not the Promiscuous Mode
- This parameter can be a value of @ref EMAC_Promiscuous_Mode */
+ rt_uint32_t EMAC_PromiscuousMode; /* Selects or not the Promiscuous Mode
+ This parameter can be a value of @ref EMAC_Promiscuous_Mode */
- rt_uint32_t EMAC_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
- This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */
+ rt_uint32_t EMAC_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
+ This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */
- rt_uint32_t EMAC_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
- This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */
+ rt_uint32_t EMAC_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
+ This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */
- rt_uint32_t EMAC_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */
+ rt_uint32_t EMAC_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */
- rt_uint32_t EMAC_HashTableLow; /* This field holds the lower 32 bits of Hash table. */
+ rt_uint32_t EMAC_HashTableLow; /* This field holds the lower 32 bits of Hash table. */
- rt_uint32_t EMAC_PauseTime; /* This field holds the value to be used in the Pause Time field in the
- transmit control frame */
+ rt_uint32_t EMAC_PauseTime; /* This field holds the value to be used in the Pause Time field in the
+ transmit control frame */
- rt_uint32_t EMAC_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames
- This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */
+ rt_uint32_t EMAC_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames
+ This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */
- rt_uint32_t EMAC_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for
- automatic retransmission of PAUSE Frame
- This parameter can be a value of @ref EMAC_Pause_Low_Threshold */
+ rt_uint32_t EMAC_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for
+ automatic retransmission of PAUSE Frame
+ This parameter can be a value of @ref EMAC_Pause_Low_Threshold */
- rt_uint32_t EMAC_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0
- unicast address and unique multicast address)
- This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */
+ rt_uint32_t EMAC_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0
+ unicast address and unique multicast address)
+ This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */
- rt_uint32_t EMAC_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and
- disable its transmitter for a specified time (Pause Time)
- This parameter can be a value of @ref EMAC_Receive_Flow_Control */
+ rt_uint32_t EMAC_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and
+ disable its transmitter for a specified time (Pause Time)
+ This parameter can be a value of @ref EMAC_Receive_Flow_Control */
- rt_uint32_t EMAC_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
- or the MAC back-pressure operation (Half-Duplex mode)
- This parameter can be a value of @ref EMAC_Transmit_Flow_Control */
+ rt_uint32_t EMAC_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+ or the MAC back-pressure operation (Half-Duplex mode)
+ This parameter can be a value of @ref EMAC_Transmit_Flow_Control */
- rt_uint32_t EMAC_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
- comparison and filtering
- This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */
+ rt_uint32_t EMAC_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+ comparison and filtering
+ This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */
- rt_uint32_t EMAC_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */
+ rt_uint32_t EMAC_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */
- /**
- * DMA
- */
+ /**
+ * DMA
+ */
- rt_uint32_t EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames
- This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */
+ rt_uint32_t EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames
+ This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */
- rt_uint32_t EMAC_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode
- This parameter can be a value of @ref EMAC_Receive_Store_Forward */
+ rt_uint32_t EMAC_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode
+ This parameter can be a value of @ref EMAC_Receive_Store_Forward */
- rt_uint32_t EMAC_FlushReceivedFrame; /* Enables or disables the flushing of received frames
- This parameter can be a value of @ref EMAC_Flush_Received_Frame */
+ rt_uint32_t EMAC_FlushReceivedFrame; /* Enables or disables the flushing of received frames
+ This parameter can be a value of @ref EMAC_Flush_Received_Frame */
- rt_uint32_t EMAC_TransmitStoreForward; /* Enables or disables Transmit store and forward mode
- This parameter can be a value of @ref EMAC_Transmit_Store_Forward */
+ rt_uint32_t EMAC_TransmitStoreForward; /* Enables or disables Transmit store and forward mode
+ This parameter can be a value of @ref EMAC_Transmit_Store_Forward */
- rt_uint32_t EMAC_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control
- This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */
+ rt_uint32_t EMAC_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control
+ This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */
- rt_uint32_t EMAC_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames
- This parameter can be a value of @ref EMAC_Forward_Error_Frames */
+ rt_uint32_t EMAC_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames
+ This parameter can be a value of @ref EMAC_Forward_Error_Frames */
- rt_uint32_t EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
- and length less than 64 bytes) including pad-bytes and CRC)
- This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */
+ rt_uint32_t EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+ and length less than 64 bytes) including pad-bytes and CRC)
+ This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */
- rt_uint32_t EMAC_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO
- This parameter can be a value of @ref EMAC_Receive_Threshold_Control */
+ rt_uint32_t EMAC_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO
+ This parameter can be a value of @ref EMAC_Receive_Threshold_Control */
- rt_uint32_t EMAC_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second
- frame of Transmit data even before obtaining the status for the first frame.
- This parameter can be a value of @ref EMAC_Second_Frame_Operate */
+ rt_uint32_t EMAC_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second
+ frame of Transmit data even before obtaining the status for the first frame.
+ This parameter can be a value of @ref EMAC_Second_Frame_Operate */
- rt_uint32_t EMAC_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats
- This parameter can be a value of @ref EMAC_Address_Aligned_Beats */
+ rt_uint32_t EMAC_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats
+ This parameter can be a value of @ref EMAC_Address_Aligned_Beats */
- rt_uint32_t EMAC_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers
- This parameter can be a value of @ref EMAC_Fixed_Burst */
+ rt_uint32_t EMAC_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers
+ This parameter can be a value of @ref EMAC_Fixed_Burst */
- rt_uint32_t EMAC_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction
- This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */
+ rt_uint32_t EMAC_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction
+ This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */
- rt_uint32_t EMAC_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
- This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */
+ rt_uint32_t EMAC_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
+ This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */
- rt_uint32_t EMAC_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained int (Ring mode) */
+ rt_uint32_t EMAC_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained int (Ring mode) */
- rt_uint32_t EMAC_DMAArbitration; /* Selects the DMA Tx/Rx arbitration
- This parameter can be a value of @ref EMAC_DMA_Arbitration */
+ rt_uint32_t EMAC_DMAArbitration; /* Selects the DMA Tx/Rx arbitration
+ This parameter can be a value of @ref EMAC_DMA_Arbitration */
} EMAC_InitTypeDef;
/**--------------------------------------------------------------------------**/
@@ -608,10 +608,10 @@ typedef struct
*/
typedef struct
{
- rt_uint32_t Status; /* Status */
- rt_uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */
- rt_uint32_t Buffer1Addr; /* Buffer1 address pointer */
- rt_uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */
+ rt_uint32_t Status; /* Status */
+ rt_uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */
+ rt_uint32_t Buffer1Addr; /* Buffer1 address pointer */
+ rt_uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */
} EMAC_DMADESCTypeDef;
/**--------------------------------------------------------------------------**/
@@ -620,14 +620,14 @@ typedef struct
*/
/**--------------------------------------------------------------------------**/
-#define EMAC_MAX_PACKET_SIZE 1520 /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */
-#define EMAC_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
-#define EMAC_CRC 4 /* Ethernet CRC */
-#define EMAC_EXTRA 2 /* Extra bytes in some cases */
-#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */
-#define MIN_EMAC_PAYLOAD 46 /* Minimum Ethernet payload size */
-#define MAX_EMAC_PAYLOAD 1500 /* Maximum Ethernet payload size */
-#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */
+#define EMAC_MAX_PACKET_SIZE 1520 /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */
+#define EMAC_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define EMAC_CRC 4 /* Ethernet CRC */
+#define EMAC_EXTRA 2 /* Extra bytes in some cases */
+#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */
+#define MIN_EMAC_PAYLOAD 46 /* Minimum Ethernet payload size */
+#define MAX_EMAC_PAYLOAD 1500 /* Maximum Ethernet payload size */
+#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */
/**--------------------------------------------------------------------------**/
/**
@@ -1084,7 +1084,7 @@ struct rt_synopsys_eth
volatile rt_uint32_t FCR;
volatile rt_uint32_t VTR;
rt_uint8_t RESERVED0[8];
-
+
volatile rt_uint32_t RWFFR;
volatile rt_uint32_t PMTR;
volatile rt_uint32_t LPICSR;
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-24 05:19:24 +0000