diff options
Diffstat (limited to 'libcpu/mips')
24 files changed, 2821 insertions, 2821 deletions
diff --git a/libcpu/mips/common/exception.h b/libcpu/mips/common/exception.h index 2cb03d20e7..77fdb4a659 100644 --- a/libcpu/mips/common/exception.h +++ b/libcpu/mips/common/exception.h @@ -18,9 +18,9 @@ /* * important register numbers */ -#define REG_EPC 37 -#define REG_FP 72 -#define REG_SP 29 +#define REG_EPC 37 +#define REG_FP 72 +#define REG_SP 29 /* * Stack layout for the GDB exception handler @@ -28,117 +28,117 @@ * * The first PTRSIZE*6 bytes are argument save space for C subroutines. */ -#define NUMREGS 90 +#define NUMREGS 90 -#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */ -#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */ -#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */ -#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */ -#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */ -#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */ -#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */ -#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */ -#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */ -#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */ -#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */ -#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */ -#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */ -#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */ -#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */ -#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */ -#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */ -#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */ -#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */ -#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */ -#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */ -#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */ -#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */ -#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */ -#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */ -#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */ -#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */ -#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */ -#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */ -#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */ -#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */ -#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */ +#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */ +#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */ +#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */ +#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */ +#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */ +#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */ +#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */ +#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */ +#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */ +#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */ +#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */ +#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */ +#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */ +#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */ +#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */ +#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */ +#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */ +#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */ +#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */ +#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */ +#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */ +#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */ +#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */ +#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */ +#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */ +#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */ +#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */ +#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */ +#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */ +#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */ +#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */ +#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */ /* * Saved special registers */ -#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */ -#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */ -#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */ -#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */ -#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */ -#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */ +#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */ +#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */ +#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */ +#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */ +#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */ +#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */ ///* // * Saved floating point registers // */ -//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */ -//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */ -//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */ -//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */ -//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */ -//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */ -//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */ -//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */ -//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */ -//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */ -//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */ -//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */ -//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */ -//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */ -//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */ -//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */ -//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */ -//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */ -//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */ -//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */ -//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */ -//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */ -//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */ -//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */ -//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */ -//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */ -//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */ -//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */ -//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */ -//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */ -//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */ -//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */ +//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */ +//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */ +//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */ +//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */ +//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */ +//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */ +//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */ +//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */ +//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */ +//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */ +//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */ +//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */ +//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */ +//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */ +//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */ +//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */ +//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */ +//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */ +//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */ +//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */ +//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */ +//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */ +//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */ +//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */ +//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */ +//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */ +//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */ +//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */ +//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */ +//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */ +//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */ +//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */ // -//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */ -//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */ -//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */ +//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */ +//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */ +//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */ // -//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */ +//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */ // ///* // * Again, CP0 registers // */ -//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */ -#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */ -#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */ +//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */ +#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */ +#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */ -#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */ -#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */ -#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */ -#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */ -#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */ -#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */ -#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */ -#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */ -#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */ -#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */ -#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */ -#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */ -#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */ -#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */ -#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */ +#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */ +#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */ +#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */ +#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */ +#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */ +#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */ +#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */ +#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */ +#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */ +#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */ +#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */ +#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */ +#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */ +#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */ +#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */ -#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) +#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) /* * This is the same as above, but for the high-level @@ -146,15 +146,15 @@ */ typedef struct pt_regs_s { - /* Saved main processor registers. */ - rt_base_t regs[32]; - /* Saved special registers. */ - rt_base_t cp0_status; - rt_base_t hi; - rt_base_t lo; - rt_base_t cp0_badvaddr; - rt_base_t cp0_cause; - rt_base_t cp0_epc; + /* Saved main processor registers. */ + rt_base_t regs[32]; + /* Saved special registers. */ + rt_base_t cp0_status; + rt_base_t hi; + rt_base_t lo; + rt_base_t cp0_badvaddr; + rt_base_t cp0_cause; + rt_base_t cp0_epc; } pt_regs_t; typedef void (* exception_func_t)(pt_regs_t *regs); diff --git a/libcpu/mips/common/mips.h b/libcpu/mips/common/mips.h index a4bc74a050..f7f87aced9 100644 --- a/libcpu/mips/common/mips.h +++ b/libcpu/mips/common/mips.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/common/mips_addrspace.h b/libcpu/mips/common/mips_addrspace.h index 5a101e1c0c..7a3ff76f13 100644 --- a/libcpu/mips/common/mips_addrspace.h +++ b/libcpu/mips/common/mips_addrspace.h @@ -19,15 +19,15 @@ #define _ATYPE_ #define _ATYPE32_ #define _ATYPE64_ -#define _CONST64_(x) x +#define _CONST64_(x) x #else -#define _ATYPE_ __PTRDIFF_TYPE__ -#define _ATYPE32_ int -#define _ATYPE64_ __s64 +#define _ATYPE_ __PTRDIFF_TYPE__ +#define _ATYPE32_ int +#define _ATYPE64_ __s64 #ifdef CONFIG_64BIT -#define _CONST64_(x) x ## L +#define _CONST64_(x) x ## L #else -#define _CONST64_(x) x ## LL +#define _CONST64_(x) x ## LL #endif #endif @@ -38,21 +38,21 @@ #define _ACAST32_ #define _ACAST64_ #else -#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ -#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ +#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ +#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ #endif /* * Returns the kernel segment base of a given address */ -#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) +#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) /* * Returns the physical address of a CKSEGx / XKPHYS address */ -#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) -#define XPHYSADDR(a) ((_ACAST64_(a)) & \ - _CONST64_(0x000000ffffffffff)) +#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) +#define XPHYSADDR(a) ((_ACAST64_(a)) & \ + _CONST64_(0x000000ffffffffff)) #ifdef CONFIG_64BIT @@ -61,73 +61,73 @@ * The compatibility segments use the full 64-bit sign extended value. Note * the R8000 doesn't have them so don't reference these in generic MIPS code. */ -#define XKUSEG _CONST64_(0x0000000000000000) -#define XKSSEG _CONST64_(0x4000000000000000) -#define XKPHYS _CONST64_(0x8000000000000000) -#define XKSEG _CONST64_(0xc000000000000000) -#define CKSEG0 _CONST64_(0xffffffff80000000) -#define CKSEG1 _CONST64_(0xffffffffa0000000) -#define CKSSEG _CONST64_(0xffffffffc0000000) -#define CKSEG3 _CONST64_(0xffffffffe0000000) +#define XKUSEG _CONST64_(0x0000000000000000) +#define XKSSEG _CONST64_(0x4000000000000000) +#define XKPHYS _CONST64_(0x8000000000000000) +#define XKSEG _CONST64_(0xc000000000000000) +#define CKSEG0 _CONST64_(0xffffffff80000000) +#define CKSEG1 _CONST64_(0xffffffffa0000000) +#define CKSSEG _CONST64_(0xffffffffc0000000) +#define CKSEG3 _CONST64_(0xffffffffe0000000) -#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) +#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) #else -#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) +#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) /* * Map an address to a certain kernel segment */ -#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) -#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) -#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) -#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) +#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) +#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) +#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) +#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) /* * Memory segments (32bit kernel mode addresses) * These are the traditional names used in the 32-bit universe. */ -//#define KUSEGBASE 0x00000000 -//#define KSEG0BASE 0x80000000 -//#define KSEG1BASE 0xa0000000 -//#define KSEG2BASE 0xc0000000 -//#define KSEG3BASE 0xe0000000 +//#define KUSEGBASE 0x00000000 +//#define KSEG0BASE 0x80000000 +//#define KSEG1BASE 0xa0000000 +//#define KSEG2BASE 0xc0000000 +//#define KSEG3BASE 0xe0000000 -#define CKUSEG 0x00000000 -#define CKSEG0 0x80000000 -#define CKSEG1 0xa0000000 -#define CKSEG2 0xc0000000 -#define CKSEG3 0xe0000000 +#define CKUSEG 0x00000000 +#define CKSEG0 0x80000000 +#define CKSEG1 0xa0000000 +#define CKSEG2 0xc0000000 +#define CKSEG3 0xe0000000 #endif /* * Cache modes for XKPHYS address conversion macros */ -#define K_CALG_COH_EXCL1_NOL2 0 -#define K_CALG_COH_SHRL1_NOL2 1 -#define K_CALG_UNCACHED 2 -#define K_CALG_NONCOHERENT 3 -#define K_CALG_COH_EXCL 4 -#define K_CALG_COH_SHAREABLE 5 -#define K_CALG_NOTUSED 6 -#define K_CALG_UNCACHED_ACCEL 7 +#define K_CALG_COH_EXCL1_NOL2 0 +#define K_CALG_COH_SHRL1_NOL2 1 +#define K_CALG_UNCACHED 2 +#define K_CALG_NONCOHERENT 3 +#define K_CALG_COH_EXCL 4 +#define K_CALG_COH_SHAREABLE 5 +#define K_CALG_NOTUSED 6 +#define K_CALG_UNCACHED_ACCEL 7 /* * 64-bit address conversions */ -#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) -#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) -#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) -#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ - (_CONST64_(cm) << 59) | (a)) +#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) +#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) +#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) +#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ + (_CONST64_(cm) << 59) | (a)) /* * Returns the uncached address of a sdram address @@ -137,17 +137,17 @@ /* We use a 36 bit physical address map here and cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) -#else /* !CONFIG_SOC_AU1X00 */ +#else /* !CONFIG_SOC_AU1X00 */ #define UNCACHED_SDRAM(a) CKSEG1ADDR(a) -#endif /* CONFIG_SOC_AU1X00 */ -#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_SOC_AU1X00 */ +#endif /* __ASSEMBLY__ */ /* * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting * the region, 3 bits for the CCA mode. This leaves 59 bits of which the * R8000 implements most with its 48-bit physical address space. */ -#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ +#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ #ifndef CONFIG_CPU_R8000 @@ -156,13 +156,13 @@ * in order to catch bugs in the source code. */ -#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) -#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ +#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) +#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ #endif -#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) -#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) +#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) +#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) #ifndef __ASSEMBLY__ @@ -173,18 +173,18 @@ static inline phys_addr_t virt_to_phys(volatile void * address) { #ifndef CONFIG_64BIT - return CPHYSADDR(address); + return CPHYSADDR(address); #else - return XPHYSADDR(address); + return XPHYSADDR(address); #endif } static inline void * phys_to_virt(unsigned long address) { #ifndef CONFIG_64BIT - return (void *)KSEG0ADDR(address); + return (void *)KSEG0ADDR(address); #else - return (void *)CKSEG0ADDR(address); + return (void *)CKSEG0ADDR(address); #endif } #endif diff --git a/libcpu/mips/common/mips_asm.h b/libcpu/mips/common/mips_asm.h index 949cea9019..5a566b3bd8 100644 --- a/libcpu/mips/common/mips_asm.h +++ b/libcpu/mips/common/mips_asm.h @@ -47,31 +47,31 @@ * in makefile. */ #ifdef _BSS_OLD_ -#define BSS .##section bss +#define BSS .##section bss #else -#define BSS .##bss +#define BSS .##bss #endif #define LEAF(name)\ - .##text;\ - .##globl name;\ - .##ent name;\ + .##text;\ + .##globl name;\ + .##ent name;\ name: #define SLEAF(name)\ - .##text;\ - .##ent name;\ + .##text;\ + .##ent name;\ name: #ifdef __ghs__ #define END(name)\ - .##end name + .##end name #else #define END(name)\ - .##size name,.-name;\ - .##end name + .##size name,.-name;\ + .##end name #endif @@ -151,7 +151,7 @@ typedef union tunSU32 #define True !False #ifndef NULL -#define NULL ((void *)0) +#define NULL ((void *)0) #endif//NULL #ifndef MIN @@ -159,31 +159,31 @@ typedef union tunSU32 #endif//MIN #ifndef MAX -#define MAX(x,y) ((x) > (y) ? (x) : (y)) +#define MAX(x,y) ((x) > (y) ? (x) : (y)) #endif//MAX -#define MAXUINT(w) (\ - ((w) == sizeof(U8)) ? 0xFFU :\ - ((w) == sizeof(U16)) ? 0xFFFFU :\ - ((w) == sizeof(U32)) ? 0xFFFFFFFFU : 0\ - ) +#define MAXUINT(w) (\ + ((w) == sizeof(U8)) ? 0xFFU :\ + ((w) == sizeof(U16)) ? 0xFFFFU :\ + ((w) == sizeof(U32)) ? 0xFFFFFFFFU : 0\ + ) -#define MAXINT(w) (\ - ((w) == sizeof(S8)) ? 0x7F :\ - ((w) == sizeof(S16)) ? 0x7FFF :\ - ((w) == sizeof(S32)) ? 0x7FFFFFFF : 0\ - ) +#define MAXINT(w) (\ + ((w) == sizeof(S8)) ? 0x7F :\ + ((w) == sizeof(S16)) ? 0x7FFF :\ + ((w) == sizeof(S32)) ? 0x7FFFFFFF : 0\ + ) -#define MSK(n) ((1 << (n)) - 1) +#define MSK(n) ((1 << (n)) - 1) -#define KUSEG_MSK 0x80000000 -#define KSEG_MSK 0xE0000000 +#define KUSEG_MSK 0x80000000 +#define KSEG_MSK 0xE0000000 -#define KUSEGBASE 0x00000000 -#define KSEG0BASE 0x80000000 -#define KSEG1BASE 0xA0000000 -#define KSSEGBASE 0xC0000000 -#define KSEG3BASE 0xE0000000 +#define KUSEGBASE 0x00000000 +#define KSEG0BASE 0x80000000 +#define KSEG1BASE 0xA0000000 +#define KSSEGBASE 0xC0000000 +#define KSEG3BASE 0xE0000000 /* Below macros perform the following functions : * @@ -197,8 +197,8 @@ typedef union tunSU32 * KSEG1A : Same as KSEG1 but operates on register rather than constant. * PHYSA : Same as PHYS but operates on register rather than constant. * CACHED : Alias for KSEG0 macro . - * (Note that KSEG0 cache attribute is determined by K0 - * field of Config register, but this is typically cached). + * (Note that KSEG0 cache attribute is determined by K0 + * field of Config register, but this is typically cached). * UNCACHED : Alias for KSEG1 macro . */ #ifdef __ASSEMBLY__ @@ -208,117 +208,117 @@ typedef union tunSU32 #define KSEG3(addr) (((addr) & ~KSEG_MSK) | KSEG3BASE) #define KUSEG(addr) (((addr) & ~KUSEG_MSK) | KUSEGBASE) #define PHYS(addr) ( (addr) & ~KSEG_MSK) -#define KSEG0A(reg) and reg, ~KSEG_MSK; or reg, KSEG0BASE -#define KSEG1A(reg) and reg, ~KSEG_MSK; or reg, KSEG1BASE -#define PHYSA(reg) and reg, ~KSEG_MSK +#define KSEG0A(reg) and reg, ~KSEG_MSK; or reg, KSEG0BASE +#define KSEG1A(reg) and reg, ~KSEG_MSK; or reg, KSEG1BASE +#define PHYSA(reg) and reg, ~KSEG_MSK #else #define KSEG0(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG0BASE) #define KSEG1(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG1BASE) -#define KSSEG(addr) (((U32)(addr) & ~KSEG_MSK) | KSSEGBASE) -#define KSEG3(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG3BASE) -#define KUSEG(addr) (((U32)(addr) & ~KUSEG_MSK) | KUSEGBASE) -#define PHYS(addr) ((U32)(addr) & ~KSEG_MSK) +#define KSSEG(addr) (((U32)(addr) & ~KSEG_MSK) | KSSEGBASE) +#define KSEG3(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG3BASE) +#define KUSEG(addr) (((U32)(addr) & ~KUSEG_MSK) | KUSEGBASE) +#define PHYS(addr) ((U32)(addr) & ~KSEG_MSK) #endif -#define CACHED(addr) KSEG0(addr) -#define UNCACHED(addr) KSEG1(addr) +#define CACHED(addr) KSEG0(addr) +#define UNCACHED(addr) KSEG1(addr) #ifdef __ASSEMBLY__ /* Macroes to access variables at constant addresses * Compensates for signed 16 bit displacement - * Typical use: li a0, HIKSEG1(ATLAS_ASCIIWORD) - * sw v1, LO_OFFS(ATLAS_ASCIIWORD)(a0) + * Typical use: li a0, HIKSEG1(ATLAS_ASCIIWORD) + * sw v1, LO_OFFS(ATLAS_ASCIIWORD)(a0) */ -#define HIKSEG0(addr) ((KSEG0(addr) + 0x8000) & 0xffff0000) -#define HIKSEG1(addr) ((KSEG1(addr) + 0x8000) & 0xffff0000) -#define HI_PART(addr) (((addr) + 0x8000) & 0xffff0000) -#define LO_OFFS(addr) ((addr) & 0xffff) +#define HIKSEG0(addr) ((KSEG0(addr) + 0x8000) & 0xffff0000) +#define HIKSEG1(addr) ((KSEG1(addr) + 0x8000) & 0xffff0000) +#define HI_PART(addr) (((addr) + 0x8000) & 0xffff0000) +#define LO_OFFS(addr) ((addr) & 0xffff) #endif /* Most/Least significant 32 bit from 64 bit double word */ -#define HI32(data64) ((U32)(data64 >> 32)) -#define LO32(data64) ((U32)(data64 & 0xFFFFFFFF)) +#define HI32(data64) ((U32)(data64 >> 32)) +#define LO32(data64) ((U32)(data64 & 0xFFFFFFFF)) #if ((!defined(__ASSEMBLY__)) && (!defined(__LANGUAGE_ASSEMBLY))) -#define REG8( addr ) (*(volatile U8 *) (addr)) -#define REG16( addr ) (*(volatile U16 *)(addr)) -#define REG32( addr ) (*(volatile U32 *)(addr)) -#define REG64( addr ) (*(volatile U64 *)(addr)) +#define REG8( addr ) (*(volatile U8 *) (addr)) +#define REG16( addr ) (*(volatile U16 *)(addr)) +#define REG32( addr ) (*(volatile U32 *)(addr)) +#define REG64( addr ) (*(volatile U64 *)(addr)) #endif /* Register field mapping */ -#define REGFIELD(reg, rfld) (((reg) & rfld##_MSK) >> rfld##_SHF) +#define REGFIELD(reg, rfld) (((reg) & rfld##_MSK) >> rfld##_SHF) -/* absolute register address, access */ -#define REGA(addr) REG32(addr) +/* absolute register address, access */ +#define REGA(addr) REG32(addr) -/* physical register address, access: base address + offsett */ -#define REGP(base,phys) REG32( (U32)(base) + (phys) ) +/* physical register address, access: base address + offsett */ +#define REGP(base,phys) REG32( (U32)(base) + (phys) ) -/* relative register address, access: base address + offsett */ +/* relative register address, access: base address + offsett */ #define REG(base,offs) REG32( (U32)(base) + offs##_##OFS ) -/* relative register address, access: base address + offsett */ +/* relative register address, access: base address + offsett */ #define REG_8(base,offs) REG8( (U32)(base) + offs##_##OFS ) -/* relative register address, access: base address + offsett */ +/* relative register address, access: base address + offsett */ #define REG_16(base,offs) REG16( (U32)(base) + offs##_##OFS ) -/* relative register address, access: base address + offsett */ +/* relative register address, access: base address + offsett */ #define REG_64(base,offs) REG64( (U32)(base) + offs##_##OFS ) /************************************** * Macroes not used by YAMON any more * (kept for backwards compatibility) */ -/* register read field */ -#define REGARD(addr,fld) ((REGA(addr) & addr##_##fld##_##MSK) \ - >> addr##_##fld##_##SHF) +/* register read field */ +#define REGARD(addr,fld) ((REGA(addr) & addr##_##fld##_##MSK) \ + >> addr##_##fld##_##SHF) -/* register write numeric field value */ -#define REGAWRI(addr,fld,intval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\ - | ((intval) << addr##_##fld##_##SHF)) +/* register write numeric field value */ +#define REGAWRI(addr,fld,intval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\ + | ((intval) << addr##_##fld##_##SHF)) -/* register write enumerated field value */ -#define REGAWRE(addr,fld,enumval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\ - | ((addr##_##fld##_##enumval) << addr##_##fld##_##SHF)) +/* register write enumerated field value */ +#define REGAWRE(addr,fld,enumval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\ + | ((addr##_##fld##_##enumval) << addr##_##fld##_##SHF)) /* Examples: * - * exccode = REGARD(CPU_CAUSE,EXC); + * exccode = REGARD(CPU_CAUSE,EXC); * - * REGA(SDR_CONTROL) = REGAWRI(OSG_CONTROL,TMO,17) - * | REGAWRE(OSG_CONTROL,DTYPE,PC1); + * REGA(SDR_CONTROL) = REGAWRI(OSG_CONTROL,TMO,17) + * | REGAWRE(OSG_CONTROL,DTYPE,PC1); */ -/* register read field */ -#define REGRD(base,offs,fld) ((REG(base,offs) & offs##_##fld##_##MSK) \ - >> offs##_##fld##_##SHF) +/* register read field */ +#define REGRD(base,offs,fld) ((REG(base,offs) & offs##_##fld##_##MSK) \ + >> offs##_##fld##_##SHF) -/* register write numeric field value */ -#define REGWRI(base,offs,fld,intval)((REG(base,offs)& ~(offs##_##fld##_##MSK))\ +/* register write numeric field value */ +#define REGWRI(base,offs,fld,intval)((REG(base,offs)& ~(offs##_##fld##_##MSK))\ | (((intval) << offs##_##fld##_##SHF) & offs##_##fld##_##MSK)) -/* register write enumerated field value */ -#define REGWRE(base,offs,fld,enumval)((REG(base,offs) & ~(offs##_##fld##_##MSK))\ - | ((offs##_##fld##_##enumval) << offs##_##fld##_##SHF)) +/* register write enumerated field value */ +#define REGWRE(base,offs,fld,enumval)((REG(base,offs) & ~(offs##_##fld##_##MSK))\ + | ((offs##_##fld##_##enumval) << offs##_##fld##_##SHF)) -/* physical register read field */ -#define REGPRD(base,phys,fld) ((REGP(base,phys) & phys##_##fld##_##MSK) \ - >> phys##_##fld##_##SHF) +/* physical register read field */ +#define REGPRD(base,phys,fld) ((REGP(base,phys) & phys##_##fld##_##MSK) \ + >> phys##_##fld##_##SHF) -/* physical register write numeric field value */ -#define REGPWRI(base,phys,fld,intval)((REGP(base,phys)& ~(phys##_##fld##_##MSK))\ - | ((intval) << phys##_##fld##_##SHF)) +/* physical register write numeric field value */ +#define REGPWRI(base,phys,fld,intval)((REGP(base,phys)& ~(phys##_##fld##_##MSK))\ + | ((intval) << phys##_##fld##_##SHF)) -/* physical register write enumerated field value */ -#define REGPWRE(base,phys,fld,enumval)((REGP(base,phys) & ~(phys##_##fld##_##MSK))\ - | ((phys##_##fld##_##enumval) << phys##_##fld##_##SHF)) +/* physical register write enumerated field value */ +#define REGPWRE(base,phys,fld,enumval)((REGP(base,phys) & ~(phys##_##fld##_##MSK))\ + | ((phys##_##fld##_##enumval) << phys##_##fld##_##SHF)) /* * End of macroes not used by YAMON any more *********************************************/ @@ -330,14 +330,14 @@ typedef union tunSU32 /* Set byte address to little endian format */ #ifdef EL -#define SWAP_BYTEADDR_EL(addr) addr +#define SWAP_BYTEADDR_EL(addr) addr #else #define SWAP_BYTEADDR_EL(addr) SWAP_BYTEADDR32( addr ) #endif /* Set byte address to big endian format */ #ifdef EB -#define SWAP_BYTEADDR_EB(addr) addr +#define SWAP_BYTEADDR_EB(addr) addr #else #define SWAP_BYTEADDR_EB(addr) SWAP_BYTEADDR32( addr ) #endif diff --git a/libcpu/mips/common/mips_cache.c b/libcpu/mips/common/mips_cache.c index d89a05e8e6..1f20e15e56 100644 --- a/libcpu/mips/common/mips_cache.c +++ b/libcpu/mips/common/mips_cache.c @@ -14,7 +14,7 @@ extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size); void r4k_cache_init(void) { -// cache_init(dcache_size, cpu_dcache_line_size); +// cache_init(dcache_size, cpu_dcache_line_size); } void r4k_cache_flush_all(void) @@ -31,7 +31,7 @@ void r4k_icache_flush_all(void) void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; + rt_ubase_t end, a; if (size > g_mips_core.icache_size) { @@ -39,7 +39,7 @@ void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) } else { - rt_ubase_t ic_lsize = g_mips_core.icache_line_size; + rt_ubase_t ic_lsize = g_mips_core.icache_line_size; a = addr & ~(ic_lsize - 1); end = ((addr + size) - 1) & ~(ic_lsize - 1); @@ -55,8 +55,8 @@ void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; - rt_ubase_t ic_lsize = g_mips_core.icache_line_size; + rt_ubase_t end, a; + rt_ubase_t ic_lsize = g_mips_core.icache_line_size; a = addr & ~(ic_lsize - 1); end = ((addr + size) - 1) & ~(ic_lsize - 1); @@ -71,7 +71,7 @@ void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size) void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; + rt_ubase_t end, a; rt_ubase_t dc_lsize = g_mips_core.dcache_line_size; a = addr & ~(dc_lsize - 1); @@ -87,7 +87,7 @@ void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size) void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; + rt_ubase_t end, a; if (size >= g_mips_core.dcache_size) { @@ -95,7 +95,7 @@ void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size) } else { - rt_ubase_t dc_lsize = g_mips_core.dcache_line_size; + rt_ubase_t dc_lsize = g_mips_core.dcache_line_size; a = addr & ~(dc_lsize - 1); end = ((addr + size) - 1) & ~(dc_lsize - 1); diff --git a/libcpu/mips/common/mips_cache.h b/libcpu/mips/common/mips_cache.h index 17a728df7e..c260ed3047 100644 --- a/libcpu/mips/common/mips_cache.h +++ b/libcpu/mips/common/mips_cache.h @@ -106,7 +106,7 @@ enum dma_data_direction #define INDEX_STORE_DATA_D 0x1d #define INDEX_STORE_DATA_S 0x1f -#define cache_op(op, addr) \ +#define cache_op(op, addr) \ __asm__ __volatile__( \ ".set push\n" \ ".set noreorder\n" \ @@ -116,95 +116,95 @@ enum dma_data_direction : \ : "i" (op), "R" (*(unsigned char *)(addr))) -#define cache16_unroll32(base, op) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips3 \n" \ - " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ - " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ - " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ - " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ - " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ - " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ - " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ - " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ - " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ - " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ - " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ - " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ - " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ - " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ - " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ - " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ - " .set mips0 \n" \ - " .set reorder \n" \ - : \ - : "r" (base), \ - "i" (op)); +#define cache16_unroll32(base, op) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips3 \n" \ + " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ + " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ + " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ + " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ + " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ + " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ + " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ + " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ + " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ + " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ + " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ + " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ + " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ + " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ + " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ + " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ + " .set mips0 \n" \ + " .set reorder \n" \ + : \ + : "r" (base), \ + "i" (op)); static inline void flush_icache_line_indexed(rt_ubase_t addr) { - cache_op(INDEX_INVALIDATE_I, addr); + cache_op(INDEX_INVALIDATE_I, addr); } static inline void flush_dcache_line_indexed(rt_ubase_t addr) { - cache_op(INDEX_WRITEBACK_INV_D, addr); + cache_op(INDEX_WRITEBACK_INV_D, addr); } static inline void flush_icache_line(rt_ubase_t addr) { - cache_op(HIT_INVALIDATE_I, addr); + cache_op(HIT_INVALIDATE_I, addr); } static inline void lock_icache_line(rt_ubase_t addr) { - cache_op(FETCH_AND_LOCK_I, addr); + cache_op(FETCH_AND_LOCK_I, addr); } static inline void lock_dcache_line(rt_ubase_t addr) { - cache_op(FETCH_AND_LOCK_D, addr); + cache_op(FETCH_AND_LOCK_D, addr); } static inline void flush_dcache_line(rt_ubase_t addr) { - cache_op(HIT_WRITEBACK_INV_D, addr); + cache_op(HIT_WRITEBACK_INV_D, addr); } static inline void invalidate_dcache_line(rt_ubase_t addr) { - cache_op(HIT_INVALIDATE_D, addr); + cache_op(HIT_INVALIDATE_D, addr); } static inline void blast_dcache16(void) { - rt_ubase_t start = KSEG0BASE; - rt_ubase_t end = start + g_mips_core.dcache_size; - rt_ubase_t addr; + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.dcache_size; + rt_ubase_t addr; - for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) - cache16_unroll32(addr, INDEX_WRITEBACK_INV_D); + for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) + cache16_unroll32(addr, INDEX_WRITEBACK_INV_D); } static inline void inv_dcache16(void) { - rt_ubase_t start = KSEG0BASE; - rt_ubase_t end = start + g_mips_core.dcache_size; - rt_ubase_t addr; + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.dcache_size; + rt_ubase_t addr; - for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) - cache16_unroll32(addr, HIT_INVALIDATE_D); + for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) + cache16_unroll32(addr, HIT_INVALIDATE_D); } static inline void blast_icache16(void) { - rt_ubase_t start = KSEG0BASE; - rt_ubase_t end = start + g_mips_core.icache_size; - rt_ubase_t addr; + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.icache_size; + rt_ubase_t addr; - for (addr = start; addr < end; addr += g_mips_core.icache_line_size) - cache16_unroll32(addr, INDEX_INVALIDATE_I); + for (addr = start; addr < end; addr += g_mips_core.icache_line_size) + cache16_unroll32(addr, INDEX_INVALIDATE_I); } void r4k_cache_init(void); diff --git a/libcpu/mips/common/mips_cfg.h b/libcpu/mips/common/mips_cfg.h index 8385ce34c2..0dff9b787d 100644 --- a/libcpu/mips/common/mips_cfg.h +++ b/libcpu/mips/common/mips_cfg.h @@ -24,7 +24,7 @@ typedef struct mips32_core_cfg // uint16_t dcache_ways; uint16_t dcache_size; - uint16_t max_tlb_entries; /* number of tlb entry */ + uint16_t max_tlb_entries; /* number of tlb entry */ } mips32_core_cfg_t; extern mips32_core_cfg_t g_mips_core; diff --git a/libcpu/mips/common/mips_context.h b/libcpu/mips/common/mips_context.h index 9e23c3864b..4663530123 100644 --- a/libcpu/mips/common/mips_context.h +++ b/libcpu/mips/common/mips_context.h @@ -11,12 +11,12 @@ #ifndef _MIPS_CONTEXT_ASM_H_ #define _MIPS_CONTEXT_ASM_H_ -#define CONTEXT_SIZE ( STK_CTX_SIZE + FPU_ADJ ) +#define CONTEXT_SIZE ( STK_CTX_SIZE + FPU_ADJ ) #ifdef __mips_hard_float -#define FPU_ADJ (32 * 4 + 8) /* FP0-FP31 + CP1_STATUS */ -#define FPU_CTX ( CONTEXT_SIZE - FPU_ADJ ) +#define FPU_ADJ (32 * 4 + 8) /* FP0-FP31 + CP1_STATUS */ +#define FPU_CTX ( CONTEXT_SIZE - FPU_ADJ ) #else -#define FPU_ADJ 0 +#define FPU_ADJ 0 #endif @@ -29,237 +29,237 @@ #endif .macro SAVE_CONTEXT - .set push - .set noat - .set noreorder - .set volatile + .set push + .set noat + .set noreorder + .set volatile - //save SP - move k1, sp - move k0, sp - subu sp, k1, CONTEXT_SIZE - sw k0, (29 * 4)(sp) + //save SP + move k1, sp + move k0, sp + subu sp, k1, CONTEXT_SIZE + sw k0, (29 * 4)(sp) - //save REG - sw $0, ( 0 * 4)(sp) - sw $1, ( 1 * 4)(sp) - sw $2, ( 2 * 4)(sp) - sw $3, ( 3 * 4)(sp) - sw $4, ( 4 * 4)(sp) - sw $5, ( 5 * 4)(sp) - sw $6, ( 6 * 4)(sp) - sw $7, ( 7 * 4)(sp) - sw $8, ( 8 * 4)(sp) - sw $9, ( 9 * 4)(sp) - sw $10, (10 * 4)(sp) - sw $11, (11 * 4)(sp) - sw $12, (12 * 4)(sp) - sw $13, (13 * 4)(sp) - sw $14, (14 * 4)(sp) - sw $15, (15 * 4)(sp) - sw $16, (16 * 4)(sp) - sw $17, (17 * 4)(sp) - sw $18, (18 * 4)(sp) - sw $19, (19 * 4)(sp) - sw $20, (20 * 4)(sp) - sw $21, (21 * 4)(sp) - sw $22, (22 * 4)(sp) - sw $23, (23 * 4)(sp) - sw $24, (24 * 4)(sp) - sw $25, (25 * 4)(sp) - /* K0 K1 */ - sw $28, (28 * 4)(sp) - /* SP */ - sw $30, (30 * 4)(sp) - sw $31, (31 * 4)(sp) + //save REG + sw $0, ( 0 * 4)(sp) + sw $1, ( 1 * 4)(sp) + sw $2, ( 2 * 4)(sp) + sw $3, ( 3 * 4)(sp) + sw $4, ( 4 * 4)(sp) + sw $5, ( 5 * 4)(sp) + sw $6, ( 6 * 4)(sp) + sw $7, ( 7 * 4)(sp) + sw $8, ( 8 * 4)(sp) + sw $9, ( 9 * 4)(sp) + sw $10, (10 * 4)(sp) + sw $11, (11 * 4)(sp) + sw $12, (12 * 4)(sp) + sw $13, (13 * 4)(sp) + sw $14, (14 * 4)(sp) + sw $15, (15 * 4)(sp) + sw $16, (16 * 4)(sp) + sw $17, (17 * 4)(sp) + sw $18, (18 * 4)(sp) + sw $19, (19 * 4)(sp) + sw $20, (20 * 4)(sp) + sw $21, (21 * 4)(sp) + sw $22, (22 * 4)(sp) + sw $23, (23 * 4)(sp) + sw $24, (24 * 4)(sp) + sw $25, (25 * 4)(sp) + /* K0 K1 */ + sw $28, (28 * 4)(sp) + /* SP */ + sw $30, (30 * 4)(sp) + sw $31, (31 * 4)(sp) - /* STATUS CAUSE EPC.... */ - mfc0 $2, CP0_STATUS - sw $2, STK_OFFSET_SR(sp) + /* STATUS CAUSE EPC.... */ + mfc0 $2, CP0_STATUS + sw $2, STK_OFFSET_SR(sp) - mfc0 $2, CP0_CAUSE - sw $2, STK_OFFSET_CAUSE(sp) + mfc0 $2, CP0_CAUSE + sw $2, STK_OFFSET_CAUSE(sp) - mfc0 $2, CP0_BADVADDR - sw $2, STK_OFFSET_BADVADDR(sp) + mfc0 $2, CP0_BADVADDR + sw $2, STK_OFFSET_BADVADDR(sp) - MFC0 $2, CP0_EPC - sw $2, STK_OFFSET_EPC(sp) + MFC0 $2, CP0_EPC + sw $2, STK_OFFSET_EPC(sp) - mfhi $2 - sw $2, STK_OFFSET_HI(sp) + mfhi $2 + sw $2, STK_OFFSET_HI(sp) - mflo $2 - sw $2, STK_OFFSET_LO(sp) + mflo $2 + sw $2, STK_OFFSET_LO(sp) #ifdef __mips_hard_float - add a0, sp,STK_CTX_SIZE + add a0, sp,STK_CTX_SIZE - mfc0 t0, CP0_STATUS - .set push - .set at - or t0, M_StatusCU1 - .set push - mtc0 t0, CP0_STATUS + mfc0 t0, CP0_STATUS + .set push + .set at + or t0, M_StatusCU1 + .set push + mtc0 t0, CP0_STATUS - cfc1 t0, CP1_STATUS + cfc1 t0, CP1_STATUS sw t0 , 0x00(a0) - swc1 $f0,(0x04 * 1)(a0) - swc1 $f1,(0x04 * 2)(a0) - swc1 $f2,(0x04 * 3)(a0) - swc1 $f3,(0x04 * 4)(a0) - swc1 $f4,(0x04 * 5)(a0) - swc1 $f5,(0x04 * 6)(a0) - swc1 $f6,(0x04 * 7)(a0) - swc1 $f7,(0x04 * 8)(a0) - swc1 $f8,(0x04 * 9)(a0) - swc1 $f9,(0x04 * 10)(a0) - swc1 $f10,(0x04 * 11)(a0) - swc1 $f11,(0x04 * 12)(a0) - swc1 $f12,(0x04 * 13)(a0) - swc1 $f13,(0x04 * 14)(a0) - swc1 $f14,(0x04 * 15)(a0) - swc1 $f15,(0x04 * 16)(a0) - swc1 $f16,(0x04 * 17)(a0) - swc1 $f17,(0x04 * 18)(a0) - swc1 $f18,(0x04 * 19)(a0) - swc1 $f19,(0x04 * 20)(a0) - swc1 $f20,(0x04 * 21)(a0) - swc1 $f21,(0x04 * 22)(a0) - swc1 $f22,(0x04 * 23)(a0) - swc1 $f23,(0x04 * 24)(a0) - swc1 $f24,(0x04 * 25)(a0) - swc1 $f25,(0x04 * 26)(a0) - swc1 $f26,(0x04 * 27)(a0) - swc1 $f27,(0x04 * 28)(a0) - swc1 $f28,(0x04 * 29)(a0) - swc1 $f29,(0x04 * 30)(a0) - swc1 $f30,(0x04 * 31)(a0) - swc1 $f31,(0x04 * 32)(a0) + swc1 $f0,(0x04 * 1)(a0) + swc1 $f1,(0x04 * 2)(a0) + swc1 $f2,(0x04 * 3)(a0) + swc1 $f3,(0x04 * 4)(a0) + swc1 $f4,(0x04 * 5)(a0) + swc1 $f5,(0x04 * 6)(a0) + swc1 $f6,(0x04 * 7)(a0) + swc1 $f7,(0x04 * 8)(a0) + swc1 $f8,(0x04 * 9)(a0) + swc1 $f9,(0x04 * 10)(a0) + swc1 $f10,(0x04 * 11)(a0) + swc1 $f11,(0x04 * 12)(a0) + swc1 $f12,(0x04 * 13)(a0) + swc1 $f13,(0x04 * 14)(a0) + swc1 $f14,(0x04 * 15)(a0) + swc1 $f15,(0x04 * 16)(a0) + swc1 $f16,(0x04 * 17)(a0) + swc1 $f17,(0x04 * 18)(a0) + swc1 $f18,(0x04 * 19)(a0) + swc1 $f19,(0x04 * 20)(a0) + swc1 $f20,(0x04 * 21)(a0) + swc1 $f21,(0x04 * 22)(a0) + swc1 $f22,(0x04 * 23)(a0) + swc1 $f23,(0x04 * 24)(a0) + swc1 $f24,(0x04 * 25)(a0) + swc1 $f25,(0x04 * 26)(a0) + swc1 $f26,(0x04 * 27)(a0) + swc1 $f27,(0x04 * 28)(a0) + swc1 $f28,(0x04 * 29)(a0) + swc1 $f29,(0x04 * 30)(a0) + swc1 $f30,(0x04 * 31)(a0) + swc1 $f31,(0x04 * 32)(a0) - nop + nop #endif - //restore a0 - lw a0, (REG_A0 * 4)(sp) + //restore a0 + lw a0, (REG_A0 * 4)(sp) - .set pop + .set pop .endm .macro RESTORE_CONTEXT - .set push - .set noat - .set noreorder - .set volatile + .set push + .set noat + .set noreorder + .set volatile #ifdef __mips_hard_float - add a0, sp,STK_CTX_SIZE + add a0, sp,STK_CTX_SIZE - mfc0 t0, CP0_STATUS - .set push - .set at + mfc0 t0, CP0_STATUS + .set push + .set at or t0, M_StatusCU1 - .set noat - mtc0 t0, CP0_STATUS + .set noat + mtc0 t0, CP0_STATUS lw t0 , 0x00(a0) - lwc1 $f0,(0x04 * 1)(a0) - lwc1 $f1,(0x04 * 2)(a0) - lwc1 $f2,(0x04 * 3)(a0) - lwc1 $f3,(0x04 * 4)(a0) - lwc1 $f4,(0x04 * 5)(a0) - lwc1 $f5,(0x04 * 6)(a0) - lwc1 $f6,(0x04 * 7)(a0) - lwc1 $f7,(0x04 * 8)(a0) - lwc1 $f8,(0x04 * 9)(a0) - lwc1 $f9,(0x04 * 10)(a0) - lwc1 $f10,(0x04 * 11)(a0) - lwc1 $f11,(0x04 * 12)(a0) - lwc1 $f12,(0x04 * 13)(a0) - lwc1 $f13,(0x04 * 14)(a0) - lwc1 $f14,(0x04 * 15)(a0) - lwc1 $f15,(0x04 * 16)(a0) - lwc1 $f16,(0x04 * 17)(a0) - lwc1 $f17,(0x04 * 18)(a0) - lwc1 $f18,(0x04 * 19)(a0) - lwc1 $f19,(0x04 * 20)(a0) - lwc1 $f20,(0x04 * 21)(a0) - lwc1 $f21,(0x04 * 22)(a0) - lwc1 $f22,(0x04 * 23)(a0) - lwc1 $f23,(0x04 * 24)(a0) - lwc1 $f24,(0x04 * 25)(a0) - lwc1 $f25,(0x04 * 26)(a0) - lwc1 $f26,(0x04 * 27)(a0) - lwc1 $f27,(0x04 * 28)(a0) - lwc1 $f28,(0x04 * 29)(a0) - lwc1 $f29,(0x04 * 30)(a0) - lwc1 $f30,(0x04 * 31)(a0) - lwc1 $f31,(0x04 * 32)(a0) - ctc1 t0, CP1_STATUS ;/* restore fpp status reg */ + lwc1 $f0,(0x04 * 1)(a0) + lwc1 $f1,(0x04 * 2)(a0) + lwc1 $f2,(0x04 * 3)(a0) + lwc1 $f3,(0x04 * 4)(a0) + lwc1 $f4,(0x04 * 5)(a0) + lwc1 $f5,(0x04 * 6)(a0) + lwc1 $f6,(0x04 * 7)(a0) + lwc1 $f7,(0x04 * 8)(a0) + lwc1 $f8,(0x04 * 9)(a0) + lwc1 $f9,(0x04 * 10)(a0) + lwc1 $f10,(0x04 * 11)(a0) + lwc1 $f11,(0x04 * 12)(a0) + lwc1 $f12,(0x04 * 13)(a0) + lwc1 $f13,(0x04 * 14)(a0) + lwc1 $f14,(0x04 * 15)(a0) + lwc1 $f15,(0x04 * 16)(a0) + lwc1 $f16,(0x04 * 17)(a0) + lwc1 $f17,(0x04 * 18)(a0) + lwc1 $f18,(0x04 * 19)(a0) + lwc1 $f19,(0x04 * 20)(a0) + lwc1 $f20,(0x04 * 21)(a0) + lwc1 $f21,(0x04 * 22)(a0) + lwc1 $f22,(0x04 * 23)(a0) + lwc1 $f23,(0x04 * 24)(a0) + lwc1 $f24,(0x04 * 25)(a0) + lwc1 $f25,(0x04 * 26)(a0) + lwc1 $f26,(0x04 * 27)(a0) + lwc1 $f27,(0x04 * 28)(a0) + lwc1 $f28,(0x04 * 29)(a0) + lwc1 $f29,(0x04 * 30)(a0) + lwc1 $f30,(0x04 * 31)(a0) + lwc1 $f31,(0x04 * 32)(a0) + ctc1 t0, CP1_STATUS ;/* restore fpp status reg */ - nop + nop #endif - /* ͨ通用寄存器 */ - /* ZERO */ - lw $1, ( 1 * 4)(sp) - /* V0 */ - lw $3, ( 3 * 4)(sp) - lw $4, ( 4 * 4)(sp) - lw $5, ( 5 * 4)(sp) - lw $6, ( 6 * 4)(sp) - lw $7, ( 7 * 4)(sp) - lw $8, ( 8 * 4)(sp) - lw $9, ( 9 * 4)(sp) - lw $10, (10 * 4)(sp) - lw $11, (11 * 4)(sp) - lw $12, (12 * 4)(sp) - lw $13, (13 * 4)(sp) - lw $14, (14 * 4)(sp) - lw $15, (15 * 4)(sp) - lw $16, (16 * 4)(sp) - lw $17, (17 * 4)(sp) - lw $18, (18 * 4)(sp) - lw $19, (19 * 4)(sp) - lw $20, (20 * 4)(sp) - lw $21, (21 * 4)(sp) - lw $22, (22 * 4)(sp) - lw $23, (23 * 4)(sp) - lw $24, (24 * 4)(sp) - lw $25, (25 * 4)(sp) - lw $26, (26 * 4)(sp) - lw $27, (27 * 4)(sp) - lw $28, (28 * 4)(sp) - /* SP */ - lw $30, (30 * 4)(sp) - lw $31, (31 * 4)(sp) + /* ͨ通用寄存器 */ + /* ZERO */ + lw $1, ( 1 * 4)(sp) + /* V0 */ + lw $3, ( 3 * 4)(sp) + lw $4, ( 4 * 4)(sp) + lw $5, ( 5 * 4)(sp) + lw $6, ( 6 * 4)(sp) + lw $7, ( 7 * 4)(sp) + lw $8, ( 8 * 4)(sp) + lw $9, ( 9 * 4)(sp) + lw $10, (10 * 4)(sp) + lw $11, (11 * 4)(sp) + lw $12, (12 * 4)(sp) + lw $13, (13 * 4)(sp) + lw $14, (14 * 4)(sp) + lw $15, (15 * 4)(sp) + lw $16, (16 * 4)(sp) + lw $17, (17 * 4)(sp) + lw $18, (18 * 4)(sp) + lw $19, (19 * 4)(sp) + lw $20, (20 * 4)(sp) + lw $21, (21 * 4)(sp) + lw $22, (22 * 4)(sp) + lw $23, (23 * 4)(sp) + lw $24, (24 * 4)(sp) + lw $25, (25 * 4)(sp) + lw $26, (26 * 4)(sp) + lw $27, (27 * 4)(sp) + lw $28, (28 * 4)(sp) + /* SP */ + lw $30, (30 * 4)(sp) + lw $31, (31 * 4)(sp) - /* STATUS CAUSE EPC.... */ - lw $2, STK_OFFSET_HI(sp) - mthi $2 - lw $2, STK_OFFSET_LO(sp) - mtlo $2 + /* STATUS CAUSE EPC.... */ + lw $2, STK_OFFSET_HI(sp) + mthi $2 + lw $2, STK_OFFSET_LO(sp) + mtlo $2 - lw $2, STK_OFFSET_SR(sp) - mtc0 $2, CP0_STATUS + lw $2, STK_OFFSET_SR(sp) + mtc0 $2, CP0_STATUS - lw $2, STK_OFFSET_BADVADDR(sp) - mtc0 $2, CP0_BADVADDR + lw $2, STK_OFFSET_BADVADDR(sp) + mtc0 $2, CP0_BADVADDR - lw $2, STK_OFFSET_CAUSE(sp) - mtc0 $2, CP0_CAUSE + lw $2, STK_OFFSET_CAUSE(sp) + mtc0 $2, CP0_CAUSE - lw $2, STK_OFFSET_EPC(sp) - MTC0 $2, CP0_EPC + lw $2, STK_OFFSET_EPC(sp) + MTC0 $2, CP0_EPC - //restore $2 - lw $2, ( 2 * 4)(sp) - //restore sp - lw $29, (29 * 4)(sp) + //restore $2 + lw $2, ( 2 * 4)(sp) + //restore sp + lw $29, (29 * 4)(sp) - eret - nop + eret + nop .set pop .endm #endif diff --git a/libcpu/mips/common/mips_def.h b/libcpu/mips/common/mips_def.h index 1727684f50..3ac965f65a 100644 --- a/libcpu/mips/common/mips_def.h +++ b/libcpu/mips/common/mips_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -35,24 +35,24 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnOpcode 26 -#define M_InstnOpcode (0x3f << S_InstnOpcode) -#define S_InstnRS 21 -#define M_InstnRS (0x1f << S_InstnRS) -#define S_InstnRT 16 -#define M_InstnRT (0x1f << S_InstnRT) -#define S_InstnRD 11 -#define M_InstnRD (0x1f << S_InstnRD) -#define S_InstnSA 6 -#define M_InstnSA (0x1f << S_InstnSA) -#define S_InstnTcode 6 -#define M_InstnTcode (0x3ff << S_InstnTcode) -#define S_InstnBcode 6 -#define M_InstnBcode (0xfffff << S_InstnBcode) -#define S_InstnFunc 0 -#define M_InstnFunc (0x3f << S_InstnFunc) -#define S_InstnSel 0 -#define M_InstnSel (0x7 << S_InstnSel) +#define S_InstnOpcode 26 +#define M_InstnOpcode (0x3f << S_InstnOpcode) +#define S_InstnRS 21 +#define M_InstnRS (0x1f << S_InstnRS) +#define S_InstnRT 16 +#define M_InstnRT (0x1f << S_InstnRT) +#define S_InstnRD 11 +#define M_InstnRD (0x1f << S_InstnRD) +#define S_InstnSA 6 +#define M_InstnSA (0x1f << S_InstnSA) +#define S_InstnTcode 6 +#define M_InstnTcode (0x3ff << S_InstnTcode) +#define S_InstnBcode 6 +#define M_InstnBcode (0xfffff << S_InstnBcode) +#define S_InstnFunc 0 +#define M_InstnFunc (0x3f << S_InstnFunc) +#define S_InstnSel 0 +#define M_InstnSel (0x7 << S_InstnSel) /* * I-Type (load, store, branch, immediate) @@ -64,8 +64,8 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnOffset 0 -#define M_InstnOffset (0xffff << S_InstnOffset) +#define S_InstnOffset 0 +#define M_InstnOffset (0xffff << S_InstnOffset) /* * I-Type (pref) @@ -77,8 +77,8 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnHint S_InstnRT -#define M_InstnHint M_InstnRT +#define S_InstnHint S_InstnRT +#define M_InstnHint M_InstnRT /* * J-Type (jump) @@ -90,8 +90,8 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnJIndex 0 -#define M_InstnJIndex (0x03ffffff << S_InstnJIndex) +#define S_InstnJIndex 0 +#define M_InstnJIndex (0x03ffffff << S_InstnJIndex) /* * FP R-Type (operate) @@ -103,14 +103,14 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnFmt S_InstnRS -#define M_InstnFmt M_InstnRS -#define S_InstnFT S_InstnRT -#define M_InstnFT M_InstnRT -#define S_InstnFS S_InstnRD -#define M_InstnFS M_InstnRD -#define S_InstnFD S_InstnSA -#define M_InstnFD M_InstnSA +#define S_InstnFmt S_InstnRS +#define M_InstnFmt M_InstnRS +#define S_InstnFT S_InstnRT +#define M_InstnFT M_InstnRT +#define S_InstnFS S_InstnRD +#define M_InstnFS M_InstnRD +#define S_InstnFD S_InstnSA +#define M_InstnFD M_InstnSA /* * FP R-Type (cpu <-> cpu data movement)) @@ -122,8 +122,8 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnSub S_InstnRS -#define M_InstnSub M_InstnRS +#define S_InstnSub S_InstnRS +#define M_InstnSub M_InstnRS /* * FP R-Type (compare) @@ -137,10 +137,10 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnCCcmp 8 -#define M_InstnCCcmp (0x7 << S_InstnCCcmp) -#define S_InstnCABS 6 -#define M_InstnCABS (0x1 << S_InstnCABS) +#define S_InstnCCcmp 8 +#define M_InstnCCcmp (0x7 << S_InstnCCcmp) +#define S_InstnCABS 6 +#define M_InstnCABS (0x1 << S_InstnCABS) /* * FP R-Type (FPR conditional move on FP cc) @@ -153,12 +153,12 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnCC 18 -#define M_InstnCC (0x7 << S_InstnCC) -#define S_InstnND 17 -#define M_InstnND (0x1 << S_InstnND) -#define S_InstnTF 16 -#define M_InstnTF (0x1 << S_InstnTF) +#define S_InstnCC 18 +#define M_InstnCC (0x7 << S_InstnCC) +#define S_InstnND 17 +#define M_InstnND (0x1 << S_InstnND) +#define S_InstnTF 16 +#define M_InstnTF (0x1 << S_InstnTF) /* * FP R-Type (3-operand operate) @@ -170,12 +170,12 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnFR S_InstnRS -#define M_InstnFR M_InstnRS -#define S_InstnOp4 3 -#define M_InstnOp4 (0x7 << S_InstnOp4) -#define S_InstnFmt3 0 -#define M_InstnFmt3 (0x7 << S_InstnFmt3) +#define S_InstnFR S_InstnRS +#define M_InstnFR M_InstnRS +#define S_InstnOp4 3 +#define M_InstnOp4 (0x7 << S_InstnOp4) +#define S_InstnFmt3 0 +#define M_InstnFmt3 (0x7 << S_InstnFmt3) /* * FP R-Type (Indexed load, store) @@ -196,8 +196,8 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define S_InstnHintX S_InstnRD -#define M_InstnHintX M_InstnRD +#define S_InstnHintX S_InstnRD +#define M_InstnHintX M_InstnRD /* * FP R-Type (GPR conditional move on FP cc) @@ -239,19 +239,19 @@ */ #ifdef MIPSADDR64 -#define A_K0BASE UNS64Const(0xffffffff80000000) -#define A_K1BASE UNS64Const(0xffffffffa0000000) -#define A_K2BASE UNS64Const(0xffffffffc0000000) -#define A_K3BASE UNS64Const(0xffffffffe0000000) -#define A_REGION UNS64Const(0xc000000000000000) -#define A_XKPHYS_ATTR UNS64Const(0x3800000000000000) +#define A_K0BASE UNS64Const(0xffffffff80000000) +#define A_K1BASE UNS64Const(0xffffffffa0000000) +#define A_K2BASE UNS64Const(0xffffffffc0000000) +#define A_K3BASE UNS64Const(0xffffffffe0000000) +#define A_REGION UNS64Const(0xc000000000000000) +#define A_XKPHYS_ATTR UNS64Const(0x3800000000000000) #else -#define A_K0BASE 0x80000000 -#define A_K1BASE 0xa0000000 -#define A_K2BASE 0xc0000000 -#define A_K3BASE 0xe0000000 +#define A_K0BASE 0x80000000 +#define A_K1BASE 0xa0000000 +#define A_K2BASE 0xc0000000 +#define A_K3BASE 0xe0000000 #endif -#define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */ +#define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */ #ifdef MIPS_Model64 @@ -352,41 +352,41 @@ /* * Cache encodings */ -#define K_CachePriI 0 /* Primary Icache */ -#define K_CachePriD 1 /* Primary Dcache */ -#define K_CachePriU 1 /* Unified primary */ -#define K_CacheTerU 2 /* Unified Tertiary */ -#define K_CacheSecU 3 /* Unified secondary */ +#define K_CachePriI 0 /* Primary Icache */ +#define K_CachePriD 1 /* Primary Dcache */ +#define K_CachePriU 1 /* Unified primary */ +#define K_CacheTerU 2 /* Unified Tertiary */ +#define K_CacheSecU 3 /* Unified secondary */ /* * Function encodings */ -#define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */ -#define K_CacheIndexInv 0 /* Index invalidate */ -#define K_CacheIndexWBInv 0 /* Index writeback invalidate */ -#define K_CacheIndexLdTag 1 /* Index load tag */ -#define K_CacheIndexStTag 2 /* Index store tag */ -#define K_CacheHitInv 4 /* Hit Invalidate */ -#define K_CacheFill 5 /* Fill (Icache only) */ -#define K_CacheHitWBInv 5 /* Hit writeback invalidate */ -#define K_CacheHitWB 6 /* Hit writeback */ -#define K_CacheFetchLock 7 /* Fetch and lock */ +#define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */ +#define K_CacheIndexInv 0 /* Index invalidate */ +#define K_CacheIndexWBInv 0 /* Index writeback invalidate */ +#define K_CacheIndexLdTag 1 /* Index load tag */ +#define K_CacheIndexStTag 2 /* Index store tag */ +#define K_CacheHitInv 4 /* Hit Invalidate */ +#define K_CacheFill 5 /* Fill (Icache only) */ +#define K_CacheHitWBInv 5 /* Hit writeback invalidate */ +#define K_CacheHitWB 6 /* Hit writeback */ +#define K_CacheFetchLock 7 /* Fetch and lock */ -#define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI) -#define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD) -#define DCIndexInv DCIndexWBInv -#define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI) -#define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD) -#define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI) -#define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD) -#define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI) -#define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD) -#define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI) -#define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD) -#define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD) -#define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI) -#define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD) +#define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI) +#define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD) +#define DCIndexInv DCIndexWBInv +#define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI) +#define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD) +#define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI) +#define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD) +#define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI) +#define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD) +#define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI) +#define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD) +#define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD) +#define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI) +#define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD) /* @@ -395,14 +395,14 @@ ************************************************************************* */ -#define PrefLoad 0 -#define PrefStore 1 -#define PrefLoadStreamed 4 -#define PrefStoreStreamed 5 -#define PrefLoadRetained 6 -#define PrefStoreRetained 7 -#define PrefWBInval 25 -#define PrefNudge 25 +#define PrefLoad 0 +#define PrefStore 1 +#define PrefLoadStreamed 4 +#define PrefStoreStreamed 5 +#define PrefLoadRetained 6 +#define PrefStoreRetained 7 +#define PrefWBInval 25 +#define PrefNudge 25 /* @@ -418,38 +418,38 @@ ************************************************************************* */ #ifdef __ASSEMBLY__ -#define zero $0 -#define AT $1 -#define v0 $2 -#define v1 $3 -#define a0 $4 -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 -#define t9 $25 -#define k0 $26 -#define k1 $27 -#define gp $28 -#define sp $29 -#define fp $30 -#define ra $31 +#define zero $0 +#define AT $1 +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 +#define k1 $27 +#define gp $28 +#define sp $29 +#define fp $30 +#define ra $31 /* * The following registers are used by the AVP environment and @@ -457,8 +457,8 @@ */ #ifdef MIPSAVPENV -#define repc $25 /* Expected exception PC */ -#define tid $30 /* Current test case address */ +#define repc $25 /* Expected exception PC */ +#define tid $30 /* Current test case address */ #endif @@ -472,53 +472,53 @@ * Removing them causes assembly rather than runtime errors for tests that * use the `r' names. * - * - r25 (repc) is used as the expected PC on an exception - * - r26-r27 (k0, k1) are used in the exception handler - * - r30 (tid) is used as the current test address + * - r25 (repc) is used as the expected PC on an exception + * - r26-r27 (k0, k1) are used in the exception handler + * - r30 (tid) is used as the current test address */ -#define r0 $0 -#define r1 $1 -#define r2 $2 -#define r3 $3 -#define r4 $4 -#define r5 $5 -#define r6 $6 -#define r7 $7 -#define r8 $8 -#define r9 $9 -#define r10 $10 -#define r11 $11 -#define r12 $12 -#define r13 $13 -#define r14 $14 -#define r15 $15 -#define r16 $16 -#define r17 $17 -#define r18 $18 -#define r19 $19 -#define r20 $20 -#define r21 $21 -#define r22 $22 -#define r23 $23 -#define r24 $24 +#define r0 $0 +#define r1 $1 +#define r2 $2 +#define r3 $3 +#define r4 $4 +#define r5 $5 +#define r6 $6 +#define r7 $7 +#define r8 $8 +#define r9 $9 +#define r10 $10 +#define r11 $11 +#define r12 $12 +#define r13 $13 +#define r14 $14 +#define r15 $15 +#define r16 $16 +#define r17 $17 +#define r18 $18 +#define r19 $19 +#define r20 $20 +#define r21 $21 +#define r22 $22 +#define r23 $23 +#define r24 $24 #ifdef MIPSAVPENV -#define r25 r25_unknown -#define r26 r26_unknown -#define r27 r27_unknown +#define r25 r25_unknown +#define r26 r26_unknown +#define r27 r27_unknown #else -#define r25 $25 -#define r26 $26 -#define r27 $27 +#define r25 $25 +#define r26 $26 +#define r27 $27 #endif -#define r28 $28 -#define r29 $29 +#define r28 $28 +#define r29 $29 #ifdef MIPSAVPENV -#define r30 r30_unknown +#define r30 r30_unknown #else -#define r30 $30 +#define r30 $30 #endif -#define r31 $31 +#define r31 $31 #endif @@ -531,40 +531,40 @@ * to the assembler register name ($n). */ -#define R_r0 0 -#define R_r1 1 -#define R_r2 2 -#define R_r3 3 -#define R_r4 4 -#define R_r5 5 -#define R_r6 6 -#define R_r7 7 -#define R_r8 8 -#define R_r9 9 -#define R_r10 10 -#define R_r11 11 -#define R_r12 12 -#define R_r13 13 -#define R_r14 14 -#define R_r15 15 -#define R_r16 16 -#define R_r17 17 -#define R_r18 18 -#define R_r19 19 -#define R_r20 20 -#define R_r21 21 -#define R_r22 22 -#define R_r23 23 -#define R_r24 24 -#define R_r25 25 -#define R_r26 26 -#define R_r27 27 -#define R_r28 28 -#define R_r29 29 -#define R_r30 30 -#define R_r31 31 -#define R_hi 32 /* Hi register */ -#define R_lo 33 /* Lo register */ +#define R_r0 0 +#define R_r1 1 +#define R_r2 2 +#define R_r3 3 +#define R_r4 4 +#define R_r5 5 +#define R_r6 6 +#define R_r7 7 +#define R_r8 8 +#define R_r9 9 +#define R_r10 10 +#define R_r11 11 +#define R_r12 12 +#define R_r13 13 +#define R_r14 14 +#define R_r15 15 +#define R_r16 16 +#define R_r17 17 +#define R_r18 18 +#define R_r19 19 +#define R_r20 20 +#define R_r21 21 +#define R_r22 22 +#define R_r23 23 +#define R_r24 24 +#define R_r25 25 +#define R_r26 26 +#define R_r27 27 +#define R_r28 28 +#define R_r29 29 +#define R_r30 30 +#define R_r31 31 +#define R_hi 32 /* Hi register */ +#define R_lo 33 /* Lo register */ /* @@ -575,37 +575,37 @@ * These definitions provide the bit mask corresponding to the GPR number */ -#define M_AT (1<<1) -#define M_v0 (1<<2) -#define M_v1 (1<<3) -#define M_a0 (1<<4) -#define M_a1 (1<<5) -#define M_a2 (1<<6) -#define M_a3 (1<<7) -#define M_t0 (1<<8) -#define M_t1 (1<<9) -#define M_t2 (1<<10) -#define M_t3 (1<<11) -#define M_t4 (1<<12) -#define M_t5 (1<<13) -#define M_t6 (1<<14) -#define M_t7 (1<<15) -#define M_s0 (1<<16) -#define M_s1 (1<<17) -#define M_s2 (1<<18) -#define M_s3 (1<<19) -#define M_s4 (1<<20) -#define M_s5 (1<<21) -#define M_s6 (1<<22) -#define M_s7 (1<<23) -#define M_t8 (1<<24) -#define M_t9 (1<<25) -#define M_k0 (1<<26) -#define M_k1 (1<<27) -#define M_gp (1<<28) -#define M_sp (1<<29) -#define M_fp (1<<30) -#define M_ra (1<<31) +#define M_AT (1<<1) +#define M_v0 (1<<2) +#define M_v1 (1<<3) +#define M_a0 (1<<4) +#define M_a1 (1<<5) +#define M_a2 (1<<6) +#define M_a3 (1<<7) +#define M_t0 (1<<8) +#define M_t1 (1<<9) +#define M_t2 (1<<10) +#define M_t3 (1<<11) +#define M_t4 (1<<12) +#define M_t5 (1<<13) +#define M_t6 (1<<14) +#define M_t7 (1<<15) +#define M_s0 (1<<16) +#define M_s1 (1<<17) +#define M_s2 (1<<18) +#define M_s3 (1<<19) +#define M_s4 (1<<20) +#define M_s5 (1<<21) +#define M_s6 (1<<22) +#define M_s7 (1<<23) +#define M_t8 (1<<24) +#define M_t9 (1<<25) +#define M_k0 (1<<26) +#define M_k1 (1<<27) +#define M_gp (1<<28) +#define M_sp (1<<29) +#define M_fp (1<<30) +#define M_ra (1<<31) /* @@ -614,16 +614,16 @@ ************************************************************************* * Each register has the following definitions: * - * C0_rrr The register number (as a $n value) - * R_C0_rrr The register index (as an integer corresponding - * to the register number) + * C0_rrr The register number (as a $n value) + * R_C0_rrr The register index (as an integer corresponding + * to the register number) * * Each field in a register has the following definitions: * - * S_rrrfff The shift count required to right-justify - * the field. This corresponds to the bit - * number of the right-most bit in the field. - * M_rrrfff The Mask required to isolate the field. + * S_rrrfff The shift count required to right-justify + * the field. This corresponds to the bit + * number of the right-most bit in the field. + * M_rrrfff The Mask required to isolate the field. * * Register diagrams included below as comments correspond to the * MIPS32 and MIPS64 architecture specifications. Refer to other @@ -643,18 +643,18 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Index $0 -#define R_C0_Index 0 -#define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Index $0 +#define R_C0_Index 0 +#define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_IndexP 31 /* Probe failure (R)*/ -#define M_IndexP (0x1 << S_IndexP) +#define S_IndexP 31 /* Probe failure (R)*/ +#define M_IndexP (0x1 << S_IndexP) -#define S_IndexIndex 0 /* TLB index (R/W)*/ -#define M_IndexIndex (0x3f << S_IndexIndex) +#define S_IndexIndex 0 /* TLB index (R/W)*/ +#define M_IndexIndex (0x3f << S_IndexIndex) -#define M_Index0Fields 0x7fffffc0 -#define M_IndexRFields 0x80000000 +#define M_Index0Fields 0x7fffffc0 +#define M_IndexRFields 0x80000000 /* @@ -669,15 +669,15 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Random $1 -#define R_C0_Random 1 -#define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Random $1 +#define R_C0_Random 1 +#define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_RandomIndex 0 /* TLB random index (R)*/ -#define M_RandomIndex (0x3f << S_RandomIndex) +#define S_RandomIndex 0 /* TLB random index (R)*/ +#define M_RandomIndex (0x3f << S_RandomIndex) -#define M_Random0Fields 0xffffffc0 -#define M_RandomRFields 0x0000003f +#define M_Random0Fields 0xffffffc0 +#define M_RandomRFields 0x0000003f /* @@ -692,42 +692,42 @@ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_EntryLo0 $2 -#define R_C0_EntryLo0 2 -#define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_EntryLo0 $2 +#define R_C0_EntryLo0 2 +#define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_EntryLoPFN 6 /* PFN (R/W) */ -#define M_EntryLoPFN (0xffffff << S_EntryLoPFN) -#define S_EntryLoC 3 /* Coherency attribute (R/W) */ -#define M_EntryLoC (0x7 << S_EntryLoC) -#define S_EntryLoD 2 /* Dirty (R/W) */ -#define M_EntryLoD (0x1 << S_EntryLoD) -#define S_EntryLoV 1 /* Valid (R/W) */ -#define M_EntryLoV (0x1 << S_EntryLoV) -#define S_EntryLoG 0 /* Global (R/W) */ -#define M_EntryLoG (0x1 << S_EntryLoG) -#define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */ -#define S_EntryLo_RS K_PageAlign /* Right-justify PFN */ -#define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */ +#define S_EntryLoPFN 6 /* PFN (R/W) */ +#define M_EntryLoPFN (0xffffff << S_EntryLoPFN) +#define S_EntryLoC 3 /* Coherency attribute (R/W) */ +#define M_EntryLoC (0x7 << S_EntryLoC) +#define S_EntryLoD 2 /* Dirty (R/W) */ +#define M_EntryLoD (0x1 << S_EntryLoD) +#define S_EntryLoV 1 /* Valid (R/W) */ +#define M_EntryLoV (0x1 << S_EntryLoV) +#define S_EntryLoG 0 /* Global (R/W) */ +#define M_EntryLoG (0x1 << S_EntryLoG) +#define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */ +#define S_EntryLo_RS K_PageAlign /* Right-justify PFN */ +#define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */ -#define M_EntryLo0Fields 0x00000000 -#define M_EntryLoRFields 0xc0000000 -#define M_EntryLo0Fields64 UNS64Const(0x0000000000000000) -#define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000) +#define M_EntryLo0Fields 0x00000000 +#define M_EntryLoRFields 0xc0000000 +#define M_EntryLo0Fields64 UNS64Const(0x0000000000000000) +#define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000) /* * Cache attribute values in the C field of EntryLo and the * K0 field of Config */ -#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */ -#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */ -#define K_CacheAttrU 2 /* Uncached */ -#define K_CacheAttrC 3 /* Cacheable */ -#define K_CacheAttrCN 3 /* Cacheable, non-coherent */ -#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */ -#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */ -#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */ -#define K_CacheAttrUA 7 /* Uncached accelerated */ +#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */ +#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */ +#define K_CacheAttrU 2 /* Uncached */ +#define K_CacheAttrC 3 /* Cacheable */ +#define K_CacheAttrCN 3 /* Cacheable, non-coherent */ +#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */ +#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */ +#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */ +#define K_CacheAttrUA 7 /* Uncached accelerated */ /* @@ -742,9 +742,9 @@ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_EntryLo1 $3 -#define R_C0_EntryLo1 3 -#define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_EntryLo1 $3 +#define R_C0_EntryLo1 3 +#define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */ /* * Field definitions are as given for EntryLo0 above @@ -763,21 +763,21 @@ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Context $4 -#define R_C0_Context 4 -#define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Context $4 +#define R_C0_Context 4 +#define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_ContextPTEBase 23 /* PTE base (R/W) */ -#define M_ContextPTEBase (0x1ff << S_ContextPTEBase) -#define S_ContextBadVPN 4 /* BadVPN2 (R) */ -#define M_ContextBadVPN (0x7ffff << S_ContextBadVPN) -#define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */ -#define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */ +#define S_ContextPTEBase 23 /* PTE base (R/W) */ +#define M_ContextPTEBase (0x1ff << S_ContextPTEBase) +#define S_ContextBadVPN 4 /* BadVPN2 (R) */ +#define M_ContextBadVPN (0x7ffff << S_ContextBadVPN) +#define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */ +#define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */ -#define M_Context0Fields 0x0000000f -#define M_ContextRFields 0x007ffff0 -#define M_Context0Fields64 UNS64Const(0x000000000000000f) -#define M_ContextRFields64 UNS64Const(0x00000000007ffff0) +#define M_Context0Fields 0x0000000f +#define M_ContextRFields 0x007ffff0 +#define M_Context0Fields64 UNS64Const(0x000000000000000f) +#define M_ContextRFields64 UNS64Const(0x00000000007ffff0) /* @@ -792,34 +792,34 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_PageMask $5 -#define R_C0_PageMask 5 /* Mask (R/W) */ -#define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_PageMask $5 +#define R_C0_PageMask 5 /* Mask (R/W) */ +#define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_PageMaskMask 13 -#define M_PageMaskMask (0xfff << S_PageMaskMask) +#define S_PageMaskMask 13 +#define M_PageMaskMask (0xfff << S_PageMaskMask) -#define M_PageMask0Fields 0xfe001fff -#define M_PageMaskRFields 0x00000000 +#define M_PageMask0Fields 0xfe001fff +#define M_PageMaskRFields 0x00000000 /* * Values in the Mask field */ -#define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */ -#define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */ -#define K_PageMask64K 0x00f -#define K_PageMask256K 0x03f -#define K_PageMask1M 0x0ff -#define K_PageMask4M 0x3ff -#define K_PageMask16M 0xfff +#define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */ +#define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */ +#define K_PageMask64K 0x00f +#define K_PageMask256K 0x03f +#define K_PageMask1M 0x0ff +#define K_PageMask4M 0x3ff +#define K_PageMask16M 0xfff -#define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */ -#define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */ -#define M_PageMask64K (K_PageMask64K << S_PageMaskMask) -#define M_PageMask256K (K_PageMask256K << S_PageMaskMask) -#define M_PageMask1M (K_PageMask1M << S_PageMaskMask) -#define M_PageMask4M (K_PageMask4M << S_PageMaskMask) -#define M_PageMask16M (K_PageMask16M << S_PageMaskMask) +#define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */ +#define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */ +#define M_PageMask64K (K_PageMask64K << S_PageMaskMask) +#define M_PageMask256K (K_PageMask256K << S_PageMaskMask) +#define M_PageMask1M (K_PageMask1M << S_PageMaskMask) +#define M_PageMask4M (K_PageMask4M << S_PageMaskMask) +#define M_PageMask16M (K_PageMask16M << S_PageMaskMask) /* @@ -834,15 +834,15 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Wired $6 -#define R_C0_Wired 6 -#define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Wired $6 +#define R_C0_Wired 6 +#define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_WiredIndex 0 /* TLB wired boundary (R/W) */ -#define M_WiredIndex (0x3f << S_WiredIndex) +#define S_WiredIndex 0 /* TLB wired boundary (R/W) */ +#define M_WiredIndex (0x3f << S_WiredIndex) -#define M_Wired0Fields 0xffffffc0 -#define M_WiredRFields 0x00000000 +#define M_Wired0Fields 0xffffffc0 +#define M_WiredRFields 0x00000000 /* @@ -857,16 +857,16 @@ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_BadVAddr $8 -#define R_C0_BadVAddr 8 -#define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_BadVAddr $8 +#define R_C0_BadVAddr 8 +#define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */ +#define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */ -#define M_BadVAddr0Fields 0x00000000 -#define M_BadVAddrRFields 0xffffffff -#define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000) -#define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff) +#define M_BadVAddr0Fields 0x00000000 +#define M_BadVAddrRFields 0xffffffff +#define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000) +#define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff) /* ************************************************************************ @@ -880,12 +880,12 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Count $9 -#define R_C0_Count 9 -#define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Count $9 +#define R_C0_Count 9 +#define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define M_Count0Fields 0x00000000 -#define M_CountRFields 0x00000000 +#define M_Count0Fields 0x00000000 +#define M_CountRFields 0x00000000 /* @@ -900,23 +900,23 @@ * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_EntryHi $10 -#define R_C0_EntryHi 10 -#define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_EntryHi $10 +#define R_C0_EntryHi 10 +#define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_EntryHiR64 62 /* Region (R/W) */ -#define M_EntryHiR64 UNS64Const(0xc000000000000000) -#define S_EntryHiVPN2 13 /* VPN/2 (R/W) */ -#define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2) -#define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000) -#define S_EntryHiASID 0 /* ASID (R/W) */ -#define M_EntryHiASID (0xff << S_EntryHiASID) -#define S_EntryHiVPN_Shf S_EntryHiVPN2 +#define S_EntryHiR64 62 /* Region (R/W) */ +#define M_EntryHiR64 UNS64Const(0xc000000000000000) +#define S_EntryHiVPN2 13 /* VPN/2 (R/W) */ +#define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2) +#define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000) +#define S_EntryHiASID 0 /* ASID (R/W) */ +#define M_EntryHiASID (0xff << S_EntryHiASID) +#define S_EntryHiVPN_Shf S_EntryHiVPN2 -#define M_EntryHi0Fields 0x00001f00 -#define M_EntryHiRFields 0x00000000 -#define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00) -#define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000) +#define M_EntryHi0Fields 0x00001f00 +#define M_EntryHiRFields 0x00000000 +#define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00) +#define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000) /* @@ -931,12 +931,12 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Compare $11 -#define R_C0_Compare 11 -#define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Compare $11 +#define R_C0_Compare 11 +#define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define M_Compare0Fields 0x00000000 -#define M_CompareRFields 0x00000000 +#define M_Compare0Fields 0x00000000 +#define M_CompareRFields 0x00000000 /* @@ -953,86 +953,86 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Status $12 -#define R_C0_Status 12 -#define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Status $12 +#define R_C0_Status 12 +#define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_StatusCU 28 /* Coprocessor enable (R/W) */ -#define M_StatusCU (0xf << S_StatusCU) -#define S_StatusCU3 31 -#define M_StatusCU3 (0x1 << S_StatusCU3) -#define S_StatusCU2 30 -#define M_StatusCU2 (0x1 << S_StatusCU2) -#define S_StatusCU1 29 -#define M_StatusCU1 (0x1 << S_StatusCU1) -#define S_StatusCU0 28 -#define M_StatusCU0 (0x1 << S_StatusCU0) -#define S_StatusRP 27 /* Enable reduced power mode (R/W) */ -#define M_StatusRP (0x1 << S_StatusRP) -#define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */ -#define M_StatusFR (0x1 << S_StatusFR) -#define S_StatusRE 25 /* Enable reverse endian (R/W) */ -#define M_StatusRE (0x1 << S_StatusRE) -#define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */ -#define M_StatusMX (0x1 << S_StatusMX) -#define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */ -#define M_StatusPX (0x1 << S_StatusPX) -#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */ -#define M_StatusBEV (0x1 << S_StatusBEV) -#define S_StatusTS 21 /* Denote TLB shutdown (R/W) */ -#define M_StatusTS (0x1 << S_StatusTS) -#define S_StatusSR 20 /* Denote soft reset (R/W) */ -#define M_StatusSR (0x1 << S_StatusSR) -#define S_StatusNMI 19 -#define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */ -#define S_StatusIM 8 /* Interrupt mask (R/W) */ -#define M_StatusIM (0xff << S_StatusIM) -#define S_StatusIM7 15 -#define M_StatusIM7 (0x1 << S_StatusIM7) -#define S_StatusIM6 14 -#define M_StatusIM6 (0x1 << S_StatusIM6) -#define S_StatusIM5 13 -#define M_StatusIM5 (0x1 << S_StatusIM5) -#define S_StatusIM4 12 -#define M_StatusIM4 (0x1 << S_StatusIM4) -#define S_StatusIM3 11 -#define M_StatusIM3 (0x1 << S_StatusIM3) -#define S_StatusIM2 10 -#define M_StatusIM2 (0x1 << S_StatusIM2) -#define S_StatusIM1 9 -#define M_StatusIM1 (0x1 << S_StatusIM1) -#define S_StatusIM0 8 -#define M_StatusIM0 (0x1 << S_StatusIM0) -#define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */ -#define M_StatusKX (0x1 << S_StatusKX) -#define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */ -#define M_StatusSX (0x1 << S_StatusSX) -#define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */ -#define M_StatusUX (0x1 << S_StatusUX) -#define S_StatusKSU 3 /* Two-bit current mode (R/W) */ -#define M_StatusKSU (0x3 << S_StatusKSU) -#define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */ -#define M_StatusUM (0x1 << S_StatusUM) -#define S_StatusSM 3 /* Supervisor mode (R/W) */ -#define M_StatusSM (0x1 << S_StatusSM) -#define S_StatusERL 2 /* Denotes error level (R/W) */ -#define M_StatusERL (0x1 << S_StatusERL) -#define S_StatusEXL 1 /* Denotes exception level (R/W) */ -#define M_StatusEXL (0x1 << S_StatusEXL) -#define S_StatusIE 0 /* Enables interrupts (R/W) */ -#define M_StatusIE (0x1 << S_StatusIE) +#define S_StatusCU 28 /* Coprocessor enable (R/W) */ +#define M_StatusCU (0xf << S_StatusCU) +#define S_StatusCU3 31 +#define M_StatusCU3 (0x1 << S_StatusCU3) +#define S_StatusCU2 30 +#define M_StatusCU2 (0x1 << S_StatusCU2) +#define S_StatusCU1 29 +#define M_StatusCU1 (0x1 << S_StatusCU1) +#define S_StatusCU0 28 +#define M_StatusCU0 (0x1 << S_StatusCU0) +#define S_StatusRP 27 /* Enable reduced power mode (R/W) */ +#define M_StatusRP (0x1 << S_StatusRP) +#define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */ +#define M_StatusFR (0x1 << S_StatusFR) +#define S_StatusRE 25 /* Enable reverse endian (R/W) */ +#define M_StatusRE (0x1 << S_StatusRE) +#define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */ +#define M_StatusMX (0x1 << S_StatusMX) +#define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */ +#define M_StatusPX (0x1 << S_StatusPX) +#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */ +#define M_StatusBEV (0x1 << S_StatusBEV) +#define S_StatusTS 21 /* Denote TLB shutdown (R/W) */ +#define M_StatusTS (0x1 << S_StatusTS) +#define S_StatusSR 20 /* Denote soft reset (R/W) */ +#define M_StatusSR (0x1 << S_StatusSR) +#define S_StatusNMI 19 +#define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */ +#define S_StatusIM 8 /* Interrupt mask (R/W) */ +#define M_StatusIM (0xff << S_StatusIM) +#define S_StatusIM7 15 +#define M_StatusIM7 (0x1 << S_StatusIM7) +#define S_StatusIM6 14 +#define M_StatusIM6 (0x1 << S_StatusIM6) +#define S_StatusIM5 13 +#define M_StatusIM5 (0x1 << S_StatusIM5) +#define S_StatusIM4 12 +#define M_StatusIM4 (0x1 << S_StatusIM4) +#define S_StatusIM3 11 +#define M_StatusIM3 (0x1 << S_StatusIM3) +#define S_StatusIM2 10 +#define M_StatusIM2 (0x1 << S_StatusIM2) +#define S_StatusIM1 9 +#define M_StatusIM1 (0x1 << S_StatusIM1) +#define S_StatusIM0 8 +#define M_StatusIM0 (0x1 << S_StatusIM0) +#define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */ +#define M_StatusKX (0x1 << S_StatusKX) +#define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */ +#define M_StatusSX (0x1 << S_StatusSX) +#define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */ +#define M_StatusUX (0x1 << S_StatusUX) +#define S_StatusKSU 3 /* Two-bit current mode (R/W) */ +#define M_StatusKSU (0x3 << S_StatusKSU) +#define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */ +#define M_StatusUM (0x1 << S_StatusUM) +#define S_StatusSM 3 /* Supervisor mode (R/W) */ +#define M_StatusSM (0x1 << S_StatusSM) +#define S_StatusERL 2 /* Denotes error level (R/W) */ +#define M_StatusERL (0x1 << S_StatusERL) +#define S_StatusEXL 1 /* Denotes exception level (R/W) */ +#define M_StatusEXL (0x1 << S_StatusEXL) +#define S_StatusIE 0 /* Enables interrupts (R/W) */ +#define M_StatusIE (0x1 << S_StatusIE) -#define M_Status0Fields 0x00040000 -#define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */ -#define M_Status0Fields64 0x00040000 -#define M_StatusRFields64 0x00000000 +#define M_Status0Fields 0x00040000 +#define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */ +#define M_Status0Fields64 0x00040000 +#define M_StatusRFields64 0x00000000 /* * Values in the KSU field */ -#define K_StatusKSU_U 2 /* User mode in KSU field */ -#define K_StatusKSU_S 1 /* Supervisor mode in KSU field */ -#define K_StatusKSU_K 0 /* Kernel mode in KSU field */ +#define K_StatusKSU_U 2 /* User mode in KSU field */ +#define K_StatusKSU_S 1 /* Supervisor mode in KSU field */ +#define K_StatusKSU_K 0 /* Kernel mode in KSU field */ /* @@ -1049,101 +1049,101 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Cause $13 -#define R_C0_Cause 13 -#define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Cause $13 +#define R_C0_Cause 13 +#define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_CauseBD 31 -#define M_CauseBD (0x1 << S_CauseBD) -#define S_CauseCE 28 -#define M_CauseCE (0x3<< S_CauseCE) -#define S_CauseIV 23 -#define M_CauseIV (0x1 << S_CauseIV) -#define S_CauseWP 22 -#define M_CauseWP (0x1 << S_CauseWP) -#define S_CauseIP 8 -#define M_CauseIP (0xff << S_CauseIP) -#define S_CauseIPEXT 10 -#define M_CauseIPEXT (0x3f << S_CauseIPEXT) -#define S_CauseIP7 15 -#define M_CauseIP7 (0x1 << S_CauseIP7) -#define S_CauseIP6 14 -#define M_CauseIP6 (0x1 << S_CauseIP6) -#define S_CauseIP5 13 -#define M_CauseIP5 (0x1 << S_CauseIP5) -#define S_CauseIP4 12 -#define M_CauseIP4 (0x1 << S_CauseIP4) -#define S_CauseIP3 11 -#define M_CauseIP3 (0x1 << S_CauseIP3) -#define S_CauseIP2 10 -#define M_CauseIP2 (0x1 << S_CauseIP2) -#define S_CauseIP1 9 -#define M_CauseIP1 (0x1 << S_CauseIP1) -#define S_CauseIP0 8 -#define M_CauseIP0 (0x1 << S_CauseIP0) -#define S_CauseExcCode 2 -#define M_CauseExcCode (0x1f << S_CauseExcCode) +#define S_CauseBD 31 +#define M_CauseBD (0x1 << S_CauseBD) +#define S_CauseCE 28 +#define M_CauseCE (0x3<< S_CauseCE) +#define S_CauseIV 23 +#define M_CauseIV (0x1 << S_CauseIV) +#define S_CauseWP 22 +#define M_CauseWP (0x1 << S_CauseWP) +#define S_CauseIP 8 +#define M_CauseIP (0xff << S_CauseIP) +#define S_CauseIPEXT 10 +#define M_CauseIPEXT (0x3f << S_CauseIPEXT) +#define S_CauseIP7 15 +#define M_CauseIP7 (0x1 << S_CauseIP7) +#define S_CauseIP6 14 +#define M_CauseIP6 (0x1 << S_CauseIP6) +#define S_CauseIP5 13 +#define M_CauseIP5 (0x1 << S_CauseIP5) +#define S_CauseIP4 12 +#define M_CauseIP4 (0x1 << S_CauseIP4) +#define S_CauseIP3 11 +#define M_CauseIP3 (0x1 << S_CauseIP3) +#define S_CauseIP2 10 +#define M_CauseIP2 (0x1 << S_CauseIP2) +#define S_CauseIP1 9 +#define M_CauseIP1 (0x1 << S_CauseIP1) +#define S_CauseIP0 8 +#define M_CauseIP0 (0x1 << S_CauseIP0) +#define S_CauseExcCode 2 +#define M_CauseExcCode (0x1f << S_CauseExcCode) -#define M_Cause0Fields 0x4f3f0083 -#define M_CauseRFields 0xb000fc7c +#define M_Cause0Fields 0x4f3f0083 +#define M_CauseRFields 0xb000fc7c /* * Values in the CE field */ -#define K_CauseCE0 0 /* Coprocessor 0 in the CE field */ -#define K_CauseCE1 1 /* Coprocessor 1 in the CE field */ -#define K_CauseCE2 2 /* Coprocessor 2 in the CE field */ -#define K_CauseCE3 3 /* Coprocessor 3 in the CE field */ +#define K_CauseCE0 0 /* Coprocessor 0 in the CE field */ +#define K_CauseCE1 1 /* Coprocessor 1 in the CE field */ +#define K_CauseCE2 2 /* Coprocessor 2 in the CE field */ +#define K_CauseCE3 3 /* Coprocessor 3 in the CE field */ /* * Values in the ExcCode field */ -#define EX_INT 0 /* Interrupt */ -#define EXC_INT (EX_INT << S_CauseExcCode) -#define EX_MOD 1 /* TLB modified */ -#define EXC_MOD (EX_MOD << S_CauseExcCode) -#define EX_TLBL 2 /* TLB exception (load or ifetch) */ -#define EXC_TLBL (EX_TLBL << S_CauseExcCode) -#define EX_TLBS 3 /* TLB exception (store) */ -#define EXC_TLBS (EX_TLBS << S_CauseExcCode) -#define EX_ADEL 4 /* Address error (load or ifetch) */ -#define EXC_ADEL (EX_ADEL << S_CauseExcCode) -#define EX_ADES 5 /* Address error (store) */ -#define EXC_ADES (EX_ADES << S_CauseExcCode) -#define EX_IBE 6 /* Instruction Bus Error */ -#define EXC_IBE (EX_IBE << S_CauseExcCode) -#define EX_DBE 7 /* Data Bus Error */ -#define EXC_DBE (EX_DBE << S_CauseExcCode) -#define EX_SYS 8 /* Syscall */ -#define EXC_SYS (EX_SYS << S_CauseExcCode) -#define EX_SYSCALL EX_SYS -#define EXC_SYSCALL EXC_SYS -#define EX_BP 9 /* Breakpoint */ -#define EXC_BP (EX_BP << S_CauseExcCode) -#define EX_BREAK EX_BP -#define EXC_BREAK EXC_BP -#define EX_RI 10 /* Reserved instruction */ -#define EXC_RI (EX_RI << S_CauseExcCode) -#define EX_CPU 11 /* CoProcessor Unusable */ -#define EXC_CPU (EX_CPU << S_CauseExcCode) -#define EX_OV 12 /* OVerflow */ -#define EXC_OV (EX_OV << S_CauseExcCode) -#define EX_TR 13 /* Trap instruction */ -#define EXC_TR (EX_TR << S_CauseExcCode) -#define EX_TRAP EX_TR -#define EXC_TRAP EXC_TR -#define EX_FPE 15 /* floating point exception */ -#define EXC_FPE (EX_FPE << S_CauseExcCode) -#define EX_C2E 18 /* COP2 exception */ -#define EXC_C2E (EX_C2E << S_CauseExcCode) -#define EX_MDMX 22 /* MDMX exception */ -#define EXC_MDMX (EX_MDMX << S_CauseExcCode) -#define EX_WATCH 23 /* Watch exception */ -#define EXC_WATCH (EX_WATCH << S_CauseExcCode) -#define EX_MCHECK 24 /* Machine check exception */ -#define EXC_MCHECK (EX_MCHECK << S_CauseExcCode) -#define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */ -#define EXC_CacheErr (EX_CacheErr << S_CauseExcCode) +#define EX_INT 0 /* Interrupt */ +#define EXC_INT (EX_INT << S_CauseExcCode) +#define EX_MOD 1 /* TLB modified */ +#define EXC_MOD (EX_MOD << S_CauseExcCode) +#define EX_TLBL 2 /* TLB exception (load or ifetch) */ +#define EXC_TLBL (EX_TLBL << S_CauseExcCode) +#define EX_TLBS 3 /* TLB exception (store) */ +#define EXC_TLBS (EX_TLBS << S_CauseExcCode) +#define EX_ADEL 4 /* Address error (load or ifetch) */ +#define EXC_ADEL (EX_ADEL << S_CauseExcCode) +#define EX_ADES 5 /* Address error (store) */ +#define EXC_ADES (EX_ADES << S_CauseExcCode) +#define EX_IBE 6 /* Instruction Bus Error */ +#define EXC_IBE (EX_IBE << S_CauseExcCode) +#define EX_DBE 7 /* Data Bus Error */ +#define EXC_DBE (EX_DBE << S_CauseExcCode) +#define EX_SYS 8 /* Syscall */ +#define EXC_SYS (EX_SYS << S_CauseExcCode) +#define EX_SYSCALL EX_SYS +#define EXC_SYSCALL EXC_SYS +#define EX_BP 9 /* Breakpoint */ +#define EXC_BP (EX_BP << S_CauseExcCode) +#define EX_BREAK EX_BP +#define EXC_BREAK EXC_BP +#define EX_RI 10 /* Reserved instruction */ +#define EXC_RI (EX_RI << S_CauseExcCode) +#define EX_CPU 11 /* CoProcessor Unusable */ +#define EXC_CPU (EX_CPU << S_CauseExcCode) +#define EX_OV 12 /* OVerflow */ +#define EXC_OV (EX_OV << S_CauseExcCode) +#define EX_TR 13 /* Trap instruction */ +#define EXC_TR (EX_TR << S_CauseExcCode) +#define EX_TRAP EX_TR +#define EXC_TRAP EXC_TR +#define EX_FPE 15 /* floating point exception */ +#define EXC_FPE (EX_FPE << S_CauseExcCode) +#define EX_C2E 18 /* COP2 exception */ +#define EXC_C2E (EX_C2E << S_CauseExcCode) +#define EX_MDMX 22 /* MDMX exception */ +#define EXC_MDMX (EX_MDMX << S_CauseExcCode) +#define EX_WATCH 23 /* Watch exception */ +#define EXC_WATCH (EX_WATCH << S_CauseExcCode) +#define EX_MCHECK 24 /* Machine check exception */ +#define EXC_MCHECK (EX_MCHECK << S_CauseExcCode) +#define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */ +#define EXC_CacheErr (EX_CacheErr << S_CauseExcCode) /* @@ -1158,13 +1158,13 @@ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_EPC $14 -#define R_C0_EPC 14 +#define C0_EPC $14 +#define R_C0_EPC 14 -#define M_EPC0Fields 0x00000000 -#define M_EPCRFields 0x00000000 -#define M_EPC0Fields64 UNS64Const(0x0000000000000000) -#define M_EPCRFields64 UNS64Const(0x0000000000000000) +#define M_EPC0Fields 0x00000000 +#define M_EPCRFields 0x00000000 +#define M_EPC0Fields64 UNS64Const(0x0000000000000000) +#define M_EPCRFields64 UNS64Const(0x0000000000000000) /* ************************************************************************ @@ -1178,25 +1178,25 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_PRId $15 -#define R_C0_PRId 15 -#define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_PRId $15 +#define R_C0_PRId 15 +#define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_PRIdCoOpt 24 /* Company options (R) */ -#define M_PRIdCoOpt (0xff << S_PRIdCoOpt) -#define S_PRIdCoID 16 /* Company ID (R) */ -#define M_PRIdCoID (0xff << S_PRIdCoID) -#define S_PRIdImp 8 /* Implementation ID (R) */ -#define M_PRIdImp (0xff << S_PRIdImp) -#define S_PRIdRev 0 /* Revision (R) */ -#define M_PRIdRev (0xff << S_PRIdRev) +#define S_PRIdCoOpt 24 /* Company options (R) */ +#define M_PRIdCoOpt (0xff << S_PRIdCoOpt) +#define S_PRIdCoID 16 /* Company ID (R) */ +#define M_PRIdCoID (0xff << S_PRIdCoID) +#define S_PRIdImp 8 /* Implementation ID (R) */ +#define M_PRIdImp (0xff << S_PRIdImp) +#define S_PRIdRev 0 /* Revision (R) */ +#define M_PRIdRev (0xff << S_PRIdRev) -#define M_PRId0Fields 0x00000000 -#define M_PRIdRFields 0xffffffff +#define M_PRId0Fields 0x00000000 +#define M_PRIdRFields 0xffffffff /* * Values in the Company ID field */ -#define K_PRIdCoID_MIPS 1 +#define K_PRIdCoID_MIPS 1 #define K_PRIdCoID_Broadcom 2 #define K_PRIdCoID_Alchemy 3 #define K_PRIdCoID_SiByte 4 @@ -1208,21 +1208,21 @@ /* * Values in the implementation number field */ -#define K_PRIdImp_Jade 0x80 -#define K_PRIdImp_Opal 0x81 -#define K_PRIdImp_Ruby 0x82 -#define K_PRIdImp_JadeLite 0x83 +#define K_PRIdImp_Jade 0x80 +#define K_PRIdImp_Opal 0x81 +#define K_PRIdImp_Ruby 0x82 +#define K_PRIdImp_JadeLite 0x83 #define K_PRIdImp_4KEc 0x84 /* Emerald with TLB MMU */ #define K_PRIdImp_4KEmp 0x85 /* Emerald with FM MMU */ #define K_PRIdImp_4KSc 0x86 /* Coral */ -#define K_PRIdImp_R3000 0x01 -#define K_PRIdImp_R4000 0x04 -#define K_PRIdImp_R10000 0x09 -#define K_PRIdImp_R4300 0x0b -#define K_PRIdImp_R5000 0x23 -#define K_PRIdImp_R5200 0x28 -#define K_PRIdImp_R5400 0x54 +#define K_PRIdImp_R3000 0x01 +#define K_PRIdImp_R4000 0x04 +#define K_PRIdImp_R10000 0x09 +#define K_PRIdImp_R4300 0x0b +#define K_PRIdImp_R5000 0x23 +#define K_PRIdImp_R5200 0x28 +#define K_PRIdImp_R5400 0x54 /* ************************************************************************ @@ -1237,24 +1237,24 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Config $16 -#define R_C0_Config 16 -#define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_Config $16 +#define R_C0_Config 16 +#define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_ConfigMore 31 /* Additional config registers present (R) */ -#define M_ConfigMore (0x1 << S_ConfigMore) -#define S_ConfigImpl 16 /* Implementation-specific fields */ -#define M_ConfigImpl (0x7fff << S_ConfigImpl) -#define S_ConfigBE 15 /* Denotes big-endian operation (R) */ -#define M_ConfigBE (0x1 << S_ConfigBE) -#define S_ConfigAT 13 /* Architecture type (R) */ -#define M_ConfigAT (0x3 << S_ConfigAT) -#define S_ConfigAR 10 /* Architecture revision (R) */ -#define M_ConfigAR (0x7 << S_ConfigAR) -#define S_ConfigMT 7 /* MMU Type (R) */ -#define M_ConfigMT (0x7 << S_ConfigMT) -#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */ -#define M_ConfigK0 (0x7 << S_ConfigK0) +#define S_ConfigMore 31 /* Additional config registers present (R) */ +#define M_ConfigMore (0x1 << S_ConfigMore) +#define S_ConfigImpl 16 /* Implementation-specific fields */ +#define M_ConfigImpl (0x7fff << S_ConfigImpl) +#define S_ConfigBE 15 /* Denotes big-endian operation (R) */ +#define M_ConfigBE (0x1 << S_ConfigBE) +#define S_ConfigAT 13 /* Architecture type (R) */ +#define M_ConfigAT (0x3 << S_ConfigAT) +#define S_ConfigAR 10 /* Architecture revision (R) */ +#define M_ConfigAR (0x7 << S_ConfigAR) +#define S_ConfigMT 7 /* MMU Type (R) */ +#define M_ConfigMT (0x7 << S_ConfigMT) +#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */ +#define M_ConfigK0 (0x7 << S_ConfigK0) /* * The following definitions are technically part of the "reserved for @@ -1263,28 +1263,28 @@ * references. For that reason, they are included here, but may be * overridden by true implementation-specific definitions */ -#define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */ -#define M_ConfigK23 (0x7 << S_ConfigK23) -#define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */ -#define M_ConfigKU (0x7 << S_ConfigKU) +#define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */ +#define M_ConfigK23 (0x7 << S_ConfigK23) +#define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */ +#define M_ConfigKU (0x7 << S_ConfigKU) -#define M_Config0Fields 0x00000078 -#define M_ConfigRFields 0x8000ff80 +#define M_Config0Fields 0x00000078 +#define M_ConfigRFields 0x8000ff80 /* * Values in the AT field */ -#define K_ConfigAT_MIPS32 0 /* MIPS32 */ -#define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */ -#define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */ +#define K_ConfigAT_MIPS32 0 /* MIPS32 */ +#define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */ +#define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */ /* * Values in the MT field */ -#define K_ConfigMT_NoMMU 0 /* No MMU */ -#define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */ -#define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */ -#define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */ +#define K_ConfigMT_NoMMU 0 /* No MMU */ +#define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */ +#define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */ +#define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */ /* @@ -1300,72 +1300,72 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Config1 $16,1 -#define R_C0_Config1 16 +#define C0_Config1 $16,1 +#define R_C0_Config1 16 -#define S_Config1More 31 /* Additional Config registers present (R) */ -#define M_Config1More (0x1 << S_Config1More) -#define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */ -#define M_Config1MMUSize (0x3f << S_Config1MMUSize) -#define S_Config1IS 22 /* Icache sets per way (R) */ -#define M_Config1IS (0x7 << S_Config1IS) -#define S_Config1IL 19 /* Icache line size (R) */ -#define M_Config1IL (0x7 << S_Config1IL) -#define S_Config1IA 16 /* Icache associativity - 1 (R) */ -#define M_Config1IA (0x7 << S_Config1IA) -#define S_Config1DS 13 /* Dcache sets per way (R) */ -#define M_Config1DS (0x7 << S_Config1DS) -#define S_Config1DL 10 /* Dcache line size (R) */ -#define M_Config1DL (0x7 << S_Config1DL) -#define S_Config1DA 7 /* Dcache associativity (R) */ -#define M_Config1DA (0x7 << S_Config1DA) -#define S_Config1C2 6 /* Coprocessor 2 present (R) */ -#define M_Config1C2 (0x1 << S_Config1C2) -#define S_Config1MD 5 /* Denotes MDMX present (R) */ -#define M_Config1MD (0x1 << S_Config1MD) -#define S_Config1PC 4 /* Denotes performance counters present (R) */ -#define M_Config1PC (0x1 << S_Config1PC) -#define S_Config1WR 3 /* Denotes watch registers present (R) */ -#define M_Config1WR (0x1 << S_Config1WR) -#define S_Config1CA 2 /* Denotes MIPS-16 present (R) */ -#define M_Config1CA (0x1 << S_Config1CA) -#define S_Config1EP 1 /* Denotes EJTAG present (R) */ -#define M_Config1EP (0x1 << S_Config1EP) -#define S_Config1FP 0 /* Denotes floating point present (R) */ -#define M_Config1FP (0x1 << S_Config1FP) +#define S_Config1More 31 /* Additional Config registers present (R) */ +#define M_Config1More (0x1 << S_Config1More) +#define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */ +#define M_Config1MMUSize (0x3f << S_Config1MMUSize) +#define S_Config1IS 22 /* Icache sets per way (R) */ +#define M_Config1IS (0x7 << S_Config1IS) +#define S_Config1IL 19 /* Icache line size (R) */ +#define M_Config1IL (0x7 << S_Config1IL) +#define S_Config1IA 16 /* Icache associativity - 1 (R) */ +#define M_Config1IA (0x7 << S_Config1IA) +#define S_Config1DS 13 /* Dcache sets per way (R) */ +#define M_Config1DS (0x7 << S_Config1DS) +#define S_Config1DL 10 /* Dcache line size (R) */ +#define M_Config1DL (0x7 << S_Config1DL) +#define S_Config1DA 7 /* Dcache associativity (R) */ +#define M_Config1DA (0x7 << S_Config1DA) +#define S_Config1C2 6 /* Coprocessor 2 present (R) */ +#define M_Config1C2 (0x1 << S_Config1C2) +#define S_Config1MD 5 /* Denotes MDMX present (R) */ +#define M_Config1MD (0x1 << S_Config1MD) +#define S_Config1PC 4 /* Denotes performance counters present (R) */ +#define M_Config1PC (0x1 << S_Config1PC) +#define S_Config1WR 3 /* Denotes watch registers present (R) */ +#define M_Config1WR (0x1 << S_Config1WR) +#define S_Config1CA 2 /* Denotes MIPS-16 present (R) */ +#define M_Config1CA (0x1 << S_Config1CA) +#define S_Config1EP 1 /* Denotes EJTAG present (R) */ +#define M_Config1EP (0x1 << S_Config1EP) +#define S_Config1FP 0 /* Denotes floating point present (R) */ +#define M_Config1FP (0x1 << S_Config1FP) -#define M_Config10Fields 0x00000060 -#define M_Config1RFields 0x7fffff9f +#define M_Config10Fields 0x00000060 +#define M_Config1RFields 0x7fffff9f /* * The following macro generates a table that is indexed * by the Icache or Dcache sets field in Config1 and * contains the decoded value of sets per way */ -#define Config1CacheSets() \ - HALF(64); \ - HALF(128); \ - HALF(256); \ - HALF(512); \ - HALF(1024); \ - HALF(2048); \ - HALF(4096); \ - HALF(8192); +#define Config1CacheSets() \ + HALF(64); \ + HALF(128); \ + HALF(256); \ + HALF(512); \ + HALF(1024); \ + HALF(2048); \ + HALF(4096); \ + HALF(8192); /* * The following macro generates a table that is indexed * by the Icache or Dcache line size field in Config1 and * contains the decoded value of the cache line size, in bytes */ -#define Config1CacheLineSize() \ - HALF(0); \ - HALF(4); \ - HALF(8); \ - HALF(16); \ - HALF(32); \ - HALF(64); \ - HALF(128); \ - HALF(256); +#define Config1CacheLineSize() \ + HALF(0); \ + HALF(4); \ + HALF(8); \ + HALF(16); \ + HALF(32); \ + HALF(64); \ + HALF(128); \ + HALF(256); /* @@ -1381,18 +1381,18 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Config2 $16,2 -#define R_C0_Config2 16 +#define C0_Config2 $16,2 +#define R_C0_Config2 16 -#define S_Config2More 31 /* Additional Config registers present (R) */ -#define M_Config2More (0x1 << S_Config2More) -#define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */ -#define M_Config2SM (0x1 << S_Config2SM) -#define S_Config2TL 0 /* Denotes Tracing Logic present (R) */ -#define M_Config2TL (0x1 << S_Config2TL) +#define S_Config2More 31 /* Additional Config registers present (R) */ +#define M_Config2More (0x1 << S_Config2More) +#define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */ +#define M_Config2SM (0x1 << S_Config2SM) +#define S_Config2TL 0 /* Denotes Tracing Logic present (R) */ +#define M_Config2TL (0x1 << S_Config2TL) -#define M_Config20Fields 0xfffffffc -#define M_Config2RFields 0x00000003 +#define M_Config20Fields 0xfffffffc +#define M_Config2RFields 0x00000003 /* ************************************************************************ @@ -1406,14 +1406,14 @@ * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_LLAddr $17 -#define R_C0_LLAddr 17 -#define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_LLAddr $17 +#define R_C0_LLAddr 17 +#define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define M_LLAddr0Fields 0x00000000 -#define M_LLAddrRFields 0x00000000 -#define M_LLAddr0Fields64 UNS64Const(0x0000000000000000) -#define M_LLAddrRFields64 UNS64Const(0x0000000000000000) +#define M_LLAddr0Fields 0x00000000 +#define M_LLAddrRFields 0x00000000 +#define M_LLAddr0Fields64 UNS64Const(0x0000000000000000) +#define M_LLAddrRFields64 UNS64Const(0x0000000000000000) /* @@ -1428,25 +1428,25 @@ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_WatchLo $18 -#define R_C0_WatchLo 18 -#define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_WatchLo $18 +#define R_C0_WatchLo 18 +#define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */ -#define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr) -#define S_WatchLoI 2 /* Enable Istream watch (R/W) */ -#define M_WatchLoI (0x1 << S_WatchLoI) -#define S_WatchLoR 1 /* Enable data read watch (R/W) */ -#define M_WatchLoR (0x1 << S_WatchLoR) -#define S_WatchLoW 0 /* Enable data write watch (R/W) */ -#define M_WatchLoW (0x1 << S_WatchLoW) +#define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */ +#define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr) +#define S_WatchLoI 2 /* Enable Istream watch (R/W) */ +#define M_WatchLoI (0x1 << S_WatchLoI) +#define S_WatchLoR 1 /* Enable data read watch (R/W) */ +#define M_WatchLoR (0x1 << S_WatchLoR) +#define S_WatchLoW 0 /* Enable data write watch (R/W) */ +#define M_WatchLoW (0x1 << S_WatchLoW) -#define M_WatchLo0Fields 0x00000000 -#define M_WatchLoRFields 0x00000000 -#define M_WatchLo0Fields64 UNS64Const(0x0000000000000000) -#define M_WatchLoRFields64 UNS64Const(0x0000000000000000) +#define M_WatchLo0Fields 0x00000000 +#define M_WatchLoRFields 0x00000000 +#define M_WatchLo0Fields64 UNS64Const(0x0000000000000000) +#define M_WatchLoRFields64 UNS64Const(0x0000000000000000) -#define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW) +#define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW) /* @@ -1461,21 +1461,21 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_WatchHi $19 -#define R_C0_WatchHi 19 -#define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_WatchHi $19 +#define R_C0_WatchHi 19 +#define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */ -#define M_WatchHiM (0x1 << S_WatchHiM) -#define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */ -#define M_WatchHiG (0x1 << S_WatchHiG) -#define S_WatchHiASID 16 /* ASID value to match (R/W) */ -#define M_WatchHiASID (0xff << S_WatchHiASID) -#define S_WatchHiMask 3 /* Address inhibit mask (R/W) */ -#define M_WatchHiMask (0x1ff << S_WatchHiMask) +#define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */ +#define M_WatchHiM (0x1 << S_WatchHiM) +#define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */ +#define M_WatchHiG (0x1 << S_WatchHiG) +#define S_WatchHiASID 16 /* ASID value to match (R/W) */ +#define M_WatchHiASID (0xff << S_WatchHiASID) +#define S_WatchHiMask 3 /* Address inhibit mask (R/W) */ +#define M_WatchHiMask (0x1ff << S_WatchHiMask) -#define M_WatchHi0Fields 0x3f00f007 -#define M_WatchHiRFields 0x80000000 +#define M_WatchHi0Fields 0x3f00f007 +#define M_WatchHiRFields 0x80000000 /* @@ -1490,14 +1490,14 @@ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_XContext $20 -#define R_C0_XContext 20 -#define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_XContext $20 +#define R_C0_XContext 20 +#define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_XContextBadVPN2 4 /* BadVPN2 (R) */ -#define S_XContextBadVPN S_XContextBadVPN2 +#define S_XContextBadVPN2 4 /* BadVPN2 (R) */ +#define S_XContextBadVPN S_XContextBadVPN2 -#define M_XContext0Fields 0x0000000f +#define M_XContext0Fields 0x0000000f /* @@ -1519,60 +1519,60 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_Debug $23 /* EJTAG */ -#define R_C0_Debug 23 +#define C0_Debug $23 /* EJTAG */ +#define R_C0_Debug 23 -#define S_DebugDBD 31 /* Debug branch delay (R) */ -#define M_DebugDBD (0x1 << S_DebugDBD) -#define S_DebugDM 30 /* Debug mode (R) */ -#define M_DebugDM (0x1 << S_DebugDM) -#define S_DebugNoDCR 29 /* No debug control register present (R) */ -#define M_DebugNoDCR (0x1 << S_DebugNoDCR) -#define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */ -#define M_DebugLSNM (0x1 << S_DebugLSNM) -#define S_DebugDoze 27 /* Doze (R) */ -#define M_DebugDoze (0x1 << S_DebugDoze) -#define S_DebugHalt 26 /* Halt (R) */ -#define M_DebugHalt (0x1 << S_DebugHalt) -#define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */ -#define M_DebugCountDM (0x1 << S_DebugCountDM) -#define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */ -#define M_DebugIBusEP (0x1 << S_DebugIBusEP) -#define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */ -#define M_DebugMCheckP (0x1 << S_DebugMCheckP) -#define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */ -#define M_DebugCacheEP (0x1 << S_DebugCacheEP) -#define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */ -#define M_DebugDBusEP (0x1 << S_DebugDBusEP) -#define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */ -#define M_DebugIEXI (0x1 << S_DebugIEXI) -#define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */ -#define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr) -#define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */ -#define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr) -#define S_DebugEJTAGver 15 /* EJTAG version number (R) */ -#define M_DebugEJTAGver (0x7 << S_DebugEJTAGver) -#define S_DebugDExcCode 10 /* Debug exception code (R) */ -#define M_DebugDExcCode (0x1f << S_DebugDExcCode) -#define S_DebugNoSSt 9 /* No single step implemented (R) */ -#define M_DebugNoSSt (0x1 << S_DebugNoSSt) -#define S_DebugSSt 8 /* Single step enable (R/W) */ -#define M_DebugSSt (0x1 << S_DebugSSt) -#define S_DebugDINT 5 /* Debug interrupt (R) */ -#define M_DebugDINT (0x1 << S_DebugDINT) -#define S_DebugDIB 4 /* Debug instruction break (R) */ -#define M_DebugDIB (0x1 << S_DebugDIB) -#define S_DebugDDBS 3 /* Debug data break store (R) */ -#define M_DebugDDBS (0x1 << S_DebugDDBS) -#define S_DebugDDBL 2 /* Debug data break load (R) */ -#define M_DebugDDBL (0x1 << S_DebugDDBL) -#define S_DebugDBp 1 /* Debug breakpoint (R) */ -#define M_DebugDBp (0x1 << S_DebugDBp) -#define S_DebugDSS 0 /* Debug single step (R) */ -#define M_DebugDSS (0x1 << S_DebugDSS) +#define S_DebugDBD 31 /* Debug branch delay (R) */ +#define M_DebugDBD (0x1 << S_DebugDBD) +#define S_DebugDM 30 /* Debug mode (R) */ +#define M_DebugDM (0x1 << S_DebugDM) +#define S_DebugNoDCR 29 /* No debug control register present (R) */ +#define M_DebugNoDCR (0x1 << S_DebugNoDCR) +#define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */ +#define M_DebugLSNM (0x1 << S_DebugLSNM) +#define S_DebugDoze 27 /* Doze (R) */ +#define M_DebugDoze (0x1 << S_DebugDoze) +#define S_DebugHalt 26 /* Halt (R) */ +#define M_DebugHalt (0x1 << S_DebugHalt) +#define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */ +#define M_DebugCountDM (0x1 << S_DebugCountDM) +#define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */ +#define M_DebugIBusEP (0x1 << S_DebugIBusEP) +#define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */ +#define M_DebugMCheckP (0x1 << S_DebugMCheckP) +#define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */ +#define M_DebugCacheEP (0x1 << S_DebugCacheEP) +#define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */ +#define M_DebugDBusEP (0x1 << S_DebugDBusEP) +#define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */ +#define M_DebugIEXI (0x1 << S_DebugIEXI) +#define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */ +#define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr) +#define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */ +#define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr) +#define S_DebugEJTAGver 15 /* EJTAG version number (R) */ +#define M_DebugEJTAGver (0x7 << S_DebugEJTAGver) +#define S_DebugDExcCode 10 /* Debug exception code (R) */ +#define M_DebugDExcCode (0x1f << S_DebugDExcCode) +#define S_DebugNoSSt 9 /* No single step implemented (R) */ +#define M_DebugNoSSt (0x1 << S_DebugNoSSt) +#define S_DebugSSt 8 /* Single step enable (R/W) */ +#define M_DebugSSt (0x1 << S_DebugSSt) +#define S_DebugDINT 5 /* Debug interrupt (R) */ +#define M_DebugDINT (0x1 << S_DebugDINT) +#define S_DebugDIB 4 /* Debug instruction break (R) */ +#define M_DebugDIB (0x1 << S_DebugDIB) +#define S_DebugDDBS 3 /* Debug data break store (R) */ +#define M_DebugDDBS (0x1 << S_DebugDDBS) +#define S_DebugDDBL 2 /* Debug data break load (R) */ +#define M_DebugDDBL (0x1 << S_DebugDDBL) +#define S_DebugDBp 1 /* Debug breakpoint (R) */ +#define M_DebugDBp (0x1 << S_DebugDBp) +#define S_DebugDSS 0 /* Debug single step (R) */ +#define M_DebugDSS (0x1 << S_DebugDSS) -#define M_Debug0Fields 0x01f000c0 -#define M_DebugRFields 0xec0ffe3f +#define M_Debug0Fields 0x01f000c0 +#define M_DebugRFields 0xec0ffe3f /* @@ -1588,13 +1588,13 @@ */ -#define C0_DEPC $24 -#define R_C0_DEPC 24 +#define C0_DEPC $24 +#define R_C0_DEPC 24 -#define M_DEEPC0Fields 0x00000000 -#define M_DEEPCRFields 0x00000000 -#define M_DEEPC0Fields64 UNS64Const(0x0000000000000000) -#define M_DEEPCRFields64 UNS64Const(0x0000000000000000) +#define M_DEEPC0Fields 0x00000000 +#define M_DEEPCRFields 0x00000000 +#define M_DEEPC0Fields64 UNS64Const(0x0000000000000000) +#define M_DEEPCRFields64 UNS64Const(0x0000000000000000) /* @@ -1618,28 +1618,28 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_PerfCnt $25 -#define R_C0_PerfCnt 25 -#define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_PerfCnt $25 +#define R_C0_PerfCnt 25 +#define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define S_PerfCntM 31 /* More performance counters exist (R) */ -#define M_PerfCntM (1 << S_PerfCntM) -#define S_PerfCntEvent 5 /* Enabled event (R/W) */ -#define M_PerfCntEvent (0x3f << S_PerfCntEvent) -#define S_PerfCntIE 4 /* Interrupt Enable (R/W) */ -#define M_PerfCntIE (1 << S_PerfCntIE) -#define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */ -#define M_PerfCntU (1 << S_PerfCntU) -#define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */ -#define M_PerfCntS (1 << S_PerfCntS) -#define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */ -#define M_PerfCntK (1 << S_PerfCntK) -#define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */ -#define M_PerfCntEXL (1 << S_PerfCntEXL) +#define S_PerfCntM 31 /* More performance counters exist (R) */ +#define M_PerfCntM (1 << S_PerfCntM) +#define S_PerfCntEvent 5 /* Enabled event (R/W) */ +#define M_PerfCntEvent (0x3f << S_PerfCntEvent) +#define S_PerfCntIE 4 /* Interrupt Enable (R/W) */ +#define M_PerfCntIE (1 << S_PerfCntIE) +#define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */ +#define M_PerfCntU (1 << S_PerfCntU) +#define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */ +#define M_PerfCntS (1 << S_PerfCntS) +#define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */ +#define M_PerfCntK (1 << S_PerfCntK) +#define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */ +#define M_PerfCntEXL (1 << S_PerfCntEXL) -#define M_PerfCnt0Fields 0x7ffff800 -#define M_PerfCntRFields 0x80000000 +#define M_PerfCnt0Fields 0x7ffff800 +#define M_PerfCntRFields 0x80000000 /* @@ -1654,13 +1654,13 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_ErrCtl $26 -#define R_C0_ErrCtl 26 -#define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_ErrCtl $26 +#define R_C0_ErrCtl 26 +#define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define M_ErrCtl0Fields 0x00000000 -#define M_ErrCtlRFields 0x00000000 +#define M_ErrCtl0Fields 0x00000000 +#define M_ErrCtlRFields 0x00000000 /* @@ -1675,12 +1675,12 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_CacheErr $27 -#define R_C0_CacheErr 27 -#define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_CacheErr $27 +#define R_C0_CacheErr 27 +#define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define M_CacheErr0Fields 0x00000000 -#define M_CachErrRFields 0x00000000 +#define M_CacheErr0Fields 0x00000000 +#define M_CachErrRFields 0x00000000 /* @@ -1695,9 +1695,9 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_TagLo $28 -#define R_C0_TagLo 28 -#define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_TagLo $28 +#define R_C0_TagLo 28 +#define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */ /* * Some implementations use separate TagLo registers for the @@ -1705,11 +1705,11 @@ * definitions can be used in relevant code */ -#define C0_ITagLo $28,0 -#define C0_DTagLo $28,2 +#define C0_ITagLo $28,0 +#define C0_DTagLo $28,2 -#define M_TagLo0Fields 0x00000000 -#define M_TagLoRFields 0x00000000 +#define M_TagLo0Fields 0x00000000 +#define M_TagLoRFields 0x00000000 /* @@ -1724,8 +1724,8 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_DataLo $28,1 -#define R_C0_DataLo 28 +#define C0_DataLo $28,1 +#define R_C0_DataLo 28 /* * Some implementations use separate DataLo registers for the @@ -1733,11 +1733,11 @@ * definitions can be used in relevant code */ -#define C0_IDataLo $28,1 -#define C0_DDataLo $28,3 +#define C0_IDataLo $28,1 +#define C0_DDataLo $28,3 -#define M_DataLo0Fields 0x00000000 -#define M_DataLoRFields 0xffffffff +#define M_DataLo0Fields 0x00000000 +#define M_DataLoRFields 0xffffffff /* @@ -1752,9 +1752,9 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_TagHi $29 -#define R_C0_TagHi 29 -#define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_TagHi $29 +#define R_C0_TagHi 29 +#define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */ /* * Some implementations use separate TagHi registers for the @@ -1762,11 +1762,11 @@ * definitions can be used in relevant code */ -#define C0_ITagHi $29,0 -#define C0_DTagHi $29,2 +#define C0_ITagHi $29,0 +#define C0_DTagHi $29,2 -#define M_TagHi0Fields 0x00000000 -#define M_TagHiRFields 0x00000000 +#define M_TagHi0Fields 0x00000000 +#define M_TagHiRFields 0x00000000 /* @@ -1781,8 +1781,8 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_DataHi $29,1 -#define R_C0_DataHi 29 +#define C0_DataHi $29,1 +#define R_C0_DataHi 29 /* * Some implementations use separate DataHi registers for the @@ -1790,11 +1790,11 @@ * definitions can be used in relevant code */ -#define C0_IDataHi $29,1 -#define C0_DDataHi $29,3 +#define C0_IDataHi $29,1 +#define C0_DDataHi $29,3 -#define M_DataHi0Fields 0x00000000 -#define M_DataHiRFields 0xffffffff +#define M_DataHi0Fields 0x00000000 +#define M_DataHiRFields 0xffffffff /* @@ -1809,14 +1809,14 @@ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_ErrorEPC $30 -#define R_C0_ErrorEPC 30 -#define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_ErrorEPC $30 +#define R_C0_ErrorEPC 30 +#define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define M_ErrorEPC0Fields 0x00000000 -#define M_ErrorEPCRFields 0x00000000 -#define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000) -#define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000) +#define M_ErrorEPC0Fields 0x00000000 +#define M_ErrorEPCRFields 0x00000000 +#define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000) +#define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000) /* @@ -1831,13 +1831,13 @@ * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C0_DESAVE $31 -#define R_C0_DESAVE 31 +#define C0_DESAVE $31 +#define R_C0_DESAVE 31 -#define M_DESAVE0Fields 0x00000000 -#define M_DESAVERFields 0x00000000 -#define M_DESAVE0Fields64 UNS64Const(0x0000000000000000) -#define M_DESAVERFields64 UNS64Const(0x0000000000000000) +#define M_DESAVE0Fields 0x00000000 +#define M_DESAVERFields 0x00000000 +#define M_DESAVE0Fields64 UNS64Const(0x0000000000000000) +#define M_DESAVERFields64 UNS64Const(0x0000000000000000) /* @@ -1853,38 +1853,38 @@ ************************************************************************* */ -#define fp0 $f0 -#define fp1 $f1 -#define fp2 $f2 -#define fp3 $f3 -#define fp4 $f4 -#define fp5 $f5 -#define fp6 $f6 -#define fp7 $f7 -#define fp8 $f8 -#define fp9 $f9 -#define fp10 $f10 -#define fp11 $f11 -#define fp12 $f12 -#define fp13 $f13 -#define fp14 $f14 -#define fp15 $f15 -#define fp16 $f16 -#define fp17 $f17 -#define fp18 $f18 -#define fp19 $f19 -#define fp20 $f20 -#define fp21 $f21 -#define fp22 $f22 -#define fp23 $f23 -#define fp24 $f24 -#define fp25 $f25 -#define fp26 $f26 -#define fp27 $f27 -#define fp28 $f28 -#define fp29 $f29 -#define fp30 $f30 -#define fp31 $f31 +#define fp0 $f0 +#define fp1 $f1 +#define fp2 $f2 +#define fp3 $f3 +#define fp4 $f4 +#define fp5 $f5 +#define fp6 $f6 +#define fp7 $f7 +#define fp8 $f8 +#define fp9 $f9 +#define fp10 $f10 +#define fp11 $f11 +#define fp12 $f12 +#define fp13 $f13 +#define fp14 $f14 +#define fp15 $f15 +#define fp16 $f16 +#define fp17 $f17 +#define fp18 $f18 +#define fp19 $f19 +#define fp20 $f20 +#define fp21 $f21 +#define fp22 $f22 +#define fp23 $f23 +#define fp24 $f24 +#define fp25 $f25 +#define fp26 $f26 +#define fp27 $f27 +#define fp28 $f28 +#define fp29 $f29 +#define fp30 $f30 +#define fp31 $f31 /* * The following definitions are used to convert an FPR name @@ -1892,39 +1892,39 @@ * This is used in macro substitution in the AVPs. */ -#define fp1_even $f0 -#define fp3_even $f2 -#define fp5_even $f4 -#define fp7_even $f6 -#define fp9_even $f8 -#define fp11_even $f10 -#define fp13_even $f12 -#define fp15_even $f14 -#define fp17_even $f16 -#define fp19_even $f18 -#define fp21_even $f20 -#define fp23_even $f22 -#define fp25_even $f24 -#define fp27_even $f26 -#define fp29_even $f28 -#define fp31_even $f30 +#define fp1_even $f0 +#define fp3_even $f2 +#define fp5_even $f4 +#define fp7_even $f6 +#define fp9_even $f8 +#define fp11_even $f10 +#define fp13_even $f12 +#define fp15_even $f14 +#define fp17_even $f16 +#define fp19_even $f18 +#define fp21_even $f20 +#define fp23_even $f22 +#define fp25_even $f24 +#define fp27_even $f26 +#define fp29_even $f28 +#define fp31_even $f30 -#define fp0_odd $f1 -#define fp2_odd $f3 -#define fp4_odd $f5 -#define fp6_odd $f7 -#define fp8_odd $f9 -#define fp10_odd $f11 -#define fp12_odd $f13 -#define fp14_odd $f15 -#define fp16_odd $f17 -#define fp18_odd $f19 -#define fp20_odd $f21 -#define fp22_odd $f23 -#define fp24_odd $f25 -#define fp26_odd $f27 -#define fp28_odd $f29 -#define fp30_odd $f31 +#define fp0_odd $f1 +#define fp2_odd $f3 +#define fp4_odd $f5 +#define fp6_odd $f7 +#define fp8_odd $f9 +#define fp10_odd $f11 +#define fp12_odd $f13 +#define fp14_odd $f15 +#define fp16_odd $f17 +#define fp18_odd $f19 +#define fp20_odd $f21 +#define fp22_odd $f23 +#define fp24_odd $f25 +#define fp26_odd $f27 +#define fp28_odd $f29 +#define fp30_odd $f31 /* @@ -1936,38 +1936,38 @@ * to the assembler register name ($n). */ -#define R_fp0 0 -#define R_fp1 1 -#define R_fp2 2 -#define R_fp3 3 -#define R_fp4 4 -#define R_fp5 5 -#define R_fp6 6 -#define R_fp7 7 -#define R_fp8 8 -#define R_fp9 9 -#define R_fp10 10 -#define R_fp11 11 -#define R_fp12 12 -#define R_fp13 13 -#define R_fp14 14 -#define R_fp15 15 -#define R_fp16 16 -#define R_fp17 17 -#define R_fp18 18 -#define R_fp19 19 -#define R_fp20 20 -#define R_fp21 21 -#define R_fp22 22 -#define R_fp23 23 -#define R_fp24 24 -#define R_fp25 25 -#define R_fp26 26 -#define R_fp27 27 -#define R_fp28 28 -#define R_fp29 29 -#define R_fp30 30 -#define R_fp31 31 +#define R_fp0 0 +#define R_fp1 1 +#define R_fp2 2 +#define R_fp3 3 +#define R_fp4 4 +#define R_fp5 5 +#define R_fp6 6 +#define R_fp7 7 +#define R_fp8 8 +#define R_fp9 9 +#define R_fp10 10 +#define R_fp11 11 +#define R_fp12 12 +#define R_fp13 13 +#define R_fp14 14 +#define R_fp15 15 +#define R_fp16 16 +#define R_fp17 17 +#define R_fp18 18 +#define R_fp19 19 +#define R_fp20 20 +#define R_fp21 21 +#define R_fp22 22 +#define R_fp23 23 +#define R_fp24 24 +#define R_fp25 25 +#define R_fp26 26 +#define R_fp27 27 +#define R_fp28 28 +#define R_fp29 29 +#define R_fp30 30 +#define R_fp31 31 /* @@ -1976,11 +1976,11 @@ ************************************************************************* */ -#define fc0 $0 -#define fc25 $25 -#define fc26 $26 -#define fc28 $28 -#define fc31 $31 +#define fc0 $0 +#define fc25 $25 +#define fc26 $26 +#define fc28 $28 +#define fc31 $31 /* @@ -1992,11 +1992,11 @@ * to the assembler register name ($n). */ -#define R_fc0 0 -#define R_fc25 25 -#define R_fc26 26 -#define R_fc28 28 -#define R_fc31 31 +#define R_fc0 0 +#define R_fc25 25 +#define R_fc26 26 +#define R_fc28 28 +#define R_fc31 31 /* @@ -2005,14 +2005,14 @@ ************************************************************************* */ -#define cc0 $fcc0 -#define cc1 $fcc1 -#define cc2 $fcc2 -#define cc3 $fcc3 -#define cc4 $fcc4 -#define cc5 $fcc5 -#define cc6 $fcc6 -#define cc7 $fcc7 +#define cc0 $fcc0 +#define cc1 $fcc1 +#define cc2 $fcc2 +#define cc3 $fcc3 +#define cc4 $fcc4 +#define cc5 $fcc5 +#define cc6 $fcc6 +#define cc7 $fcc7 /* @@ -2024,14 +2024,14 @@ * to the assembler register name ($n). */ -#define R_cc0 0 -#define R_cc1 1 -#define R_cc2 2 -#define R_cc3 3 -#define R_cc4 4 -#define R_cc5 5 -#define R_cc6 6 -#define R_cc7 7 +#define R_cc0 0 +#define R_cc1 1 +#define R_cc2 2 +#define R_cc3 3 +#define R_cc4 4 +#define R_cc5 5 +#define R_cc6 6 +#define R_cc7 7 /* @@ -2047,27 +2047,27 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C1_FIR $0 -#define R_C1_FIR 0 +#define C1_FIR $0 +#define R_C1_FIR 0 -#define S_FIRConfigS 16 -#define M_FIRConfigS (0x1 << S_FIRConfigS) -#define S_FIRConfigD 17 -#define M_FIRConfigD (0x1 << S_FIRConfigD) -#define S_FIRConfigPS 18 -#define M_FIRConfigPS (0x1 << S_FIRConfigPS) -#define S_FIRConfig3D 19 -#define M_FIRConfig3D (0x1 << S_FIRConfig3D) -#define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D) +#define S_FIRConfigS 16 +#define M_FIRConfigS (0x1 << S_FIRConfigS) +#define S_FIRConfigD 17 +#define M_FIRConfigD (0x1 << S_FIRConfigD) +#define S_FIRConfigPS 18 +#define M_FIRConfigPS (0x1 << S_FIRConfigPS) +#define S_FIRConfig3D 19 +#define M_FIRConfig3D (0x1 << S_FIRConfig3D) +#define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D) -#define S_FIRImp 8 -#define M_FIRImp (0xff << S_FIRImp) +#define S_FIRImp 8 +#define M_FIRImp (0xff << S_FIRImp) -#define S_FIRRev 0 -#define M_FIRRev (0xff << S_FIRRev) +#define S_FIRRev 0 +#define M_FIRRev (0xff << S_FIRRev) -#define M_FIR0Fields 0xfff00000 -#define M_FIRRFields 0x000fffff +#define M_FIR0Fields 0xfff00000 +#define M_FIRRFields 0x000fffff /* ************************************************************************ @@ -2081,30 +2081,30 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C1_FCCR $25 -#define R_C1_FCCR 25 +#define C1_FCCR $25 +#define R_C1_FCCR 25 -#define S_FCCRCC 0 -#define M_FCCRCC (0xff << S_FCCRCC) -#define S_FCCRCC7 7 -#define M_FCCRCC7 (0x1 << S_FCCRCC7) -#define S_FCCRCC6 6 -#define M_FCCRCC6 (0x1 << S_FCCRCC6) -#define S_FCCRCC5 5 -#define M_FCCRCC5 (0x1 << S_FCCRCC5) -#define S_FCCRCC4 4 -#define M_FCCRCC4 (0x1 << S_FCCRCC4) -#define S_FCCRCC3 3 -#define M_FCCRCC3 (0x1 << S_FCCRCC3) -#define S_FCCRCC2 2 -#define M_FCCRCC2 (0x1 << S_FCCRCC2) -#define S_FCCRCC1 1 -#define M_FCCRCC1 (0x1 << S_FCCRCC1) -#define S_FCCRCC0 0 -#define M_FCCRCC0 (0x1 << S_FCCRCC0) +#define S_FCCRCC 0 +#define M_FCCRCC (0xff << S_FCCRCC) +#define S_FCCRCC7 7 +#define M_FCCRCC7 (0x1 << S_FCCRCC7) +#define S_FCCRCC6 6 +#define M_FCCRCC6 (0x1 << S_FCCRCC6) +#define S_FCCRCC5 5 +#define M_FCCRCC5 (0x1 << S_FCCRCC5) +#define S_FCCRCC4 4 +#define M_FCCRCC4 (0x1 << S_FCCRCC4) +#define S_FCCRCC3 3 +#define M_FCCRCC3 (0x1 << S_FCCRCC3) +#define S_FCCRCC2 2 +#define M_FCCRCC2 (0x1 << S_FCCRCC2) +#define S_FCCRCC1 1 +#define M_FCCRCC1 (0x1 << S_FCCRCC1) +#define S_FCCRCC0 0 +#define M_FCCRCC0 (0x1 << S_FCCRCC0) -#define M_FCCR0Fields 0xffffff00 -#define M_FCCRRFields 0x000000ff +#define M_FCCR0Fields 0xffffff00 +#define M_FCCRRFields 0x000000ff /* @@ -2120,39 +2120,39 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C1_FEXR $26 -#define R_C1_FEXR 26 +#define C1_FEXR $26 +#define R_C1_FEXR 26 -#define S_FEXRExc 12 -#define M_FEXRExc (0x3f << S_FEXRExc) -#define S_FEXRExcE 17 -#define M_FEXRExcE (0x1 << S_FEXRExcE) -#define S_FEXRExcV 16 -#define M_FEXRExcV (0x1 << S_FEXRExcV) -#define S_FEXRExcZ 15 -#define M_FEXRExcZ (0x1 << S_FEXRExcZ) -#define S_FEXRExcO 14 -#define M_FEXRExcO (0x1 << S_FEXRExcO) -#define S_FEXRExcU 13 -#define M_FEXRExcU (0x1 << S_FEXRExcU) -#define S_FEXRExcI 12 -#define M_FEXRExcI (0x1 << S_FEXRExcI) +#define S_FEXRExc 12 +#define M_FEXRExc (0x3f << S_FEXRExc) +#define S_FEXRExcE 17 +#define M_FEXRExcE (0x1 << S_FEXRExcE) +#define S_FEXRExcV 16 +#define M_FEXRExcV (0x1 << S_FEXRExcV) +#define S_FEXRExcZ 15 +#define M_FEXRExcZ (0x1 << S_FEXRExcZ) +#define S_FEXRExcO 14 +#define M_FEXRExcO (0x1 << S_FEXRExcO) +#define S_FEXRExcU 13 +#define M_FEXRExcU (0x1 << S_FEXRExcU) +#define S_FEXRExcI 12 +#define M_FEXRExcI (0x1 << S_FEXRExcI) -#define S_FEXRFlg 2 -#define M_FEXRFlg (0x1f << S_FEXRFlg) -#define S_FEXRFlgV 6 -#define M_FEXRFlgV (0x1 << S_FEXRFlgV) -#define S_FEXRFlgZ 5 -#define M_FEXRFlgZ (0x1 << S_FEXRFlgZ) -#define S_FEXRFlgO 4 -#define M_FEXRFlgO (0x1 << S_FEXRFlgO) -#define S_FEXRFlgU 3 -#define M_FEXRFlgU (0x1 << S_FEXRFlgU) -#define S_FEXRFlgI 2 -#define M_FEXRFlgI (0x1 << S_FEXRFlgI) +#define S_FEXRFlg 2 +#define M_FEXRFlg (0x1f << S_FEXRFlg) +#define S_FEXRFlgV 6 +#define M_FEXRFlgV (0x1 << S_FEXRFlgV) +#define S_FEXRFlgZ 5 +#define M_FEXRFlgZ (0x1 << S_FEXRFlgZ) +#define S_FEXRFlgO 4 +#define M_FEXRFlgO (0x1 << S_FEXRFlgO) +#define S_FEXRFlgU 3 +#define M_FEXRFlgU (0x1 << S_FEXRFlgU) +#define S_FEXRFlgI 2 +#define M_FEXRFlgI (0x1 << S_FEXRFlgI) -#define M_FEXR0Fields 0xfffc0f83 -#define M_FEXRRFields 0x00000000 +#define M_FEXR0Fields 0xfffc0f83 +#define M_FEXRRFields 0x00000000 /* @@ -2168,30 +2168,30 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C1_FENR $28 -#define R_C1_FENR 28 +#define C1_FENR $28 +#define R_C1_FENR 28 -#define S_FENREna 7 -#define M_FENREna (0x1f << S_FENREna) -#define S_FENREnaV 11 -#define M_FENREnaV (0x1 << S_FENREnaV) -#define S_FENREnaZ 10 -#define M_FENREnaZ (0x1 << S_FENREnaZ) -#define S_FENREnaO 9 -#define M_FENREnaO (0x1 << S_FENREnaO) -#define S_FENREnaU 8 -#define M_FENREnaU (0x1 << S_FENREnaU) -#define S_FENREnaI 7 -#define M_FENREnaI (0x1 << S_FENREnaI) +#define S_FENREna 7 +#define M_FENREna (0x1f << S_FENREna) +#define S_FENREnaV 11 +#define M_FENREnaV (0x1 << S_FENREnaV) +#define S_FENREnaZ 10 +#define M_FENREnaZ (0x1 << S_FENREnaZ) +#define S_FENREnaO 9 +#define M_FENREnaO (0x1 << S_FENREnaO) +#define S_FENREnaU 8 +#define M_FENREnaU (0x1 << S_FENREnaU) +#define S_FENREnaI 7 +#define M_FENREnaI (0x1 << S_FENREnaI) -#define S_FENRFS 2 -#define M_FENRFS (0x1 << S_FENRFS) +#define S_FENRFS 2 +#define M_FENRFS (0x1 << S_FENRFS) -#define S_FENRRM 0 -#define M_FENRRM (0x3 << S_FENRRM) +#define S_FENRRM 0 +#define M_FENRRM (0x3 << S_FENRRM) -#define M_FENR0Fields 0xfffff078 -#define M_FENRRFields 0x00000000 +#define M_FENR0Fields 0xfffff078 +#define M_FENRRFields 0x00000000 /* @@ -2207,90 +2207,90 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ -#define C1_FCSR $31 -#define R_C1_FCSR 31 +#define C1_FCSR $31 +#define R_C1_FCSR 31 -#define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */ -#define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1) -#define S_FCSRCC7 31 -#define M_FCSRCC7 (0x1 << S_FCSRCC7) -#define S_FCSRCC6 30 -#define M_FCSRCC6 (0x1 << S_FCSRCC6) -#define S_FCSRCC5 29 -#define M_FCSRCC5 (0x1 << S_FCSRCC5) -#define S_FCSRCC4 28 -#define M_FCSRCC4 (0x1 << S_FCSRCC4) -#define S_FCSRCC3 27 -#define M_FCSRCC3 (0x1 << S_FCSRCC3) -#define S_FCSRCC2 26 -#define M_FCSRCC2 (0x1 << S_FCSRCC2) -#define S_FCSRCC1 25 -#define M_FCSRCC1 (0x1 << S_FCSRCC1) +#define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */ +#define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1) +#define S_FCSRCC7 31 +#define M_FCSRCC7 (0x1 << S_FCSRCC7) +#define S_FCSRCC6 30 +#define M_FCSRCC6 (0x1 << S_FCSRCC6) +#define S_FCSRCC5 29 +#define M_FCSRCC5 (0x1 << S_FCSRCC5) +#define S_FCSRCC4 28 +#define M_FCSRCC4 (0x1 << S_FCSRCC4) +#define S_FCSRCC3 27 +#define M_FCSRCC3 (0x1 << S_FCSRCC3) +#define S_FCSRCC2 26 +#define M_FCSRCC2 (0x1 << S_FCSRCC2) +#define S_FCSRCC1 25 +#define M_FCSRCC1 (0x1 << S_FCSRCC1) -#define S_FCSRFS 24 /* Flush denorms to zero (R/W) */ -#define M_FCSRFS (0x1 << S_FCSRFS) +#define S_FCSRFS 24 /* Flush denorms to zero (R/W) */ +#define M_FCSRFS (0x1 << S_FCSRFS) -#define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */ -#define M_FCSRCC0 (0x1 << S_FCSRCC0) -#define S_FCSRCC S_FCSRCC0 -#define M_FCSRCC M_FCSRCC0 +#define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */ +#define M_FCSRCC0 (0x1 << S_FCSRCC0) +#define S_FCSRCC S_FCSRCC0 +#define M_FCSRCC M_FCSRCC0 -#define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */ -#define M_FCSRImpl (0x3 << S_FCSRImpl) +#define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */ +#define M_FCSRImpl (0x3 << S_FCSRImpl) -#define S_FCSRExc 12 /* Exception cause (R/W) */ -#define M_FCSRExc (0x3f << S_FCSRExc) -#define S_FCSRExcE 17 -#define M_FCSRExcE (0x1 << S_FCSRExcE) -#define S_FCSRExcV 16 -#define M_FCSRExcV (0x1 << S_FCSRExcV) -#define S_FCSRExcZ 15 -#define M_FCSRExcZ (0x1 << S_FCSRExcZ) -#define S_FCSRExcO 14 -#define M_FCSRExcO (0x1 << S_FCSRExcO) -#define S_FCSRExcU 13 -#define M_FCSRExcU (0x1 << S_FCSRExcU) -#define S_FCSRExcI 12 -#define M_FCSRExcI (0x1 << S_FCSRExcI) +#define S_FCSRExc 12 /* Exception cause (R/W) */ +#define M_FCSRExc (0x3f << S_FCSRExc) +#define S_FCSRExcE 17 +#define M_FCSRExcE (0x1 << S_FCSRExcE) +#define S_FCSRExcV 16 +#define M_FCSRExcV (0x1 << S_FCSRExcV) +#define S_FCSRExcZ 15 +#define M_FCSRExcZ (0x1 << S_FCSRExcZ) +#define S_FCSRExcO 14 +#define M_FCSRExcO (0x1 << S_FCSRExcO) +#define S_FCSRExcU 13 +#define M_FCSRExcU (0x1 << S_FCSRExcU) +#define S_FCSRExcI 12 +#define M_FCSRExcI (0x1 << S_FCSRExcI) -#define S_FCSREna 7 /* Exception enable (R/W) */ -#define M_FCSREna (0x1f << S_FCSREna) -#define S_FCSREnaV 11 -#define M_FCSREnaV (0x1 << S_FCSREnaV) -#define S_FCSREnaZ 10 -#define M_FCSREnaZ (0x1 << S_FCSREnaZ) -#define S_FCSREnaO 9 -#define M_FCSREnaO (0x1 << S_FCSREnaO) -#define S_FCSREnaU 8 -#define M_FCSREnaU (0x1 << S_FCSREnaU) -#define S_FCSREnaI 7 -#define M_FCSREnaI (0x1 << S_FCSREnaI) +#define S_FCSREna 7 /* Exception enable (R/W) */ +#define M_FCSREna (0x1f << S_FCSREna) +#define S_FCSREnaV 11 +#define M_FCSREnaV (0x1 << S_FCSREnaV) +#define S_FCSREnaZ 10 +#define M_FCSREnaZ (0x1 << S_FCSREnaZ) +#define S_FCSREnaO 9 +#define M_FCSREnaO (0x1 << S_FCSREnaO) +#define S_FCSREnaU 8 +#define M_FCSREnaU (0x1 << S_FCSREnaU) +#define S_FCSREnaI 7 +#define M_FCSREnaI (0x1 << S_FCSREnaI) -#define S_FCSRFlg 2 /* Exception flags (R/W) */ -#define M_FCSRFlg (0x1f << S_FCSRFlg) -#define S_FCSRFlgV 6 -#define M_FCSRFlgV (0x1 << S_FCSRFlgV) -#define S_FCSRFlgZ 5 -#define M_FCSRFlgZ (0x1 << S_FCSRFlgZ) -#define S_FCSRFlgO 4 -#define M_FCSRFlgO (0x1 << S_FCSRFlgO) -#define S_FCSRFlgU 3 -#define M_FCSRFlgU (0x1 << S_FCSRFlgU) -#define S_FCSRFlgI 2 -#define M_FCSRFlgI (0x1 << S_FCSRFlgI) +#define S_FCSRFlg 2 /* Exception flags (R/W) */ +#define M_FCSRFlg (0x1f << S_FCSRFlg) +#define S_FCSRFlgV 6 +#define M_FCSRFlgV (0x1 << S_FCSRFlgV) +#define S_FCSRFlgZ 5 +#define M_FCSRFlgZ (0x1 << S_FCSRFlgZ) +#define S_FCSRFlgO 4 +#define M_FCSRFlgO (0x1 << S_FCSRFlgO) +#define S_FCSRFlgU 3 +#define M_FCSRFlgU (0x1 << S_FCSRFlgU) +#define S_FCSRFlgI 2 +#define M_FCSRFlgI (0x1 << S_FCSRFlgI) -#define S_FCSRRM 0 /* Rounding mode (R/W) */ -#define M_FCSRRM (0x3 << S_FCSRRM) +#define S_FCSRRM 0 /* Rounding mode (R/W) */ +#define M_FCSRRM (0x3 << S_FCSRRM) -#define M_FCSR0Fields 0x001c0000 -#define M_FCSRRFields 0x00000000 +#define M_FCSR0Fields 0x001c0000 +#define M_FCSRRFields 0x00000000 /* * Values in the rounding mode field (of both FCSR and FCCR) */ -#define K_FCSRRM_RN 0 -#define K_FCSRRM_RZ 1 -#define K_FCSRRM_RP 2 -#define K_FCSRRM_RM 3 +#define K_FCSRRM_RN 0 +#define K_FCSRRM_RZ 1 +#define K_FCSRRM_RP 2 +#define K_FCSRRM_RM 3 #endif /* _COMMON_MIPS_DEF_H_ */ diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h index 429de4c5cb..aa8b5a6cd5 100644 --- a/libcpu/mips/common/mips_regs.h +++ b/libcpu/mips/common/mips_regs.h @@ -17,25 +17,25 @@ #define MIPS_REG_NR 32 typedef struct { - rt_uint32_t regs[MIPS_REG_NR]; /* 32 个通用目的寄存器 */ - rt_uint32_t CP0Status; /* CP0 协处理器状态寄存器 */ - rt_uint32_t CP0DataHI; /* 除数高位寄存器 */ - rt_uint32_t CP0DataLO; /* 除数低位寄存器 */ - rt_uint32_t CP0BadVAddr; /* 出错地址寄存器 */ - rt_uint32_t CP0Cause; /* 产生中断或者异常查看的寄存器*/ - rt_uint32_t CP0EPC; /* 程序计数器寄存器 */ + rt_uint32_t regs[MIPS_REG_NR]; /* 32 个通用目的寄存器 */ + rt_uint32_t CP0Status; /* CP0 协处理器状态寄存器 */ + rt_uint32_t CP0DataHI; /* 除数高位寄存器 */ + rt_uint32_t CP0DataLO; /* 除数低位寄存器 */ + rt_uint32_t CP0BadVAddr; /* 出错地址寄存器 */ + rt_uint32_t CP0Cause; /* 产生中断或者异常查看的寄存器*/ + rt_uint32_t CP0EPC; /* 程序计数器寄存器 */ } mips_reg_ctx; #define MIPS_ARG_REG_NR 4 typedef struct { - rt_uint32_t args[MIPS_ARG_REG_NR]; /* 4 个参数寄存器 */ + rt_uint32_t args[MIPS_ARG_REG_NR]; /* 4 个参数寄存器 */ } mips_arg_ctx; struct linkctx { - rt_uint32_t id; - struct linkctx *next; + rt_uint32_t id; + struct linkctx *next; }; struct fpctx @@ -51,8 +51,8 @@ struct fp32ctx struct fpctx fp; union { - double d[16]; /* even doubles */ - float s[32]; /* even singles, padded */ + double d[16]; /* even doubles */ + float s[32]; /* even singles, padded */ }; }; @@ -61,15 +61,15 @@ struct fp64ctx struct fpctx fp; union { - double d[32]; /* even doubles, followed by odd doubles */ - float s[64]; /* even singles, followed by odd singles, padded */ + double d[32]; /* even doubles, followed by odd doubles */ + float s[64]; /* even singles, followed by odd singles, padded */ }; }; #endif /* !defined(__ASSEMBLY__) && !defined(ASSEMBLY) */ -#define MIPS_STK_CTX_WORD_SIZE 38 -#define SZREG 4 +#define MIPS_STK_CTX_WORD_SIZE 38 +#define SZREG 4 /********************************************************************************************************* MIPS 的寄存器索引 *********************************************************************************************************/ @@ -117,8 +117,8 @@ struct fp64ctx #define STK_OFFSET_LAST ((MIPS_STK_CTX_WORD_SIZE - 1) * SZREG) -#define FP32CTX_CSR ((SZREG)*2) -#define FP64CTX_CSR ((SZREG)*2) +#define FP32CTX_CSR ((SZREG)*2) +#define FP64CTX_CSR ((SZREG)*2) #define LINKCTX_ID ((SZREG)*0) #define LINKCTX_NEXT ((SZREG)*1) @@ -128,61 +128,61 @@ struct fp64ctx #define LINKCTX_TYPE_FMSA 0x463D5341 #define LINKCTX_TYPE_DSP 0x00445350 #define LINKCTX_TYPE_STKSWP 0x53574150 -#define LINKCTX_TYPE_XPA 0x00585041 +#define LINKCTX_TYPE_XPA 0x00585041 -#define FP32CTX_0 ((SZREG)*4) -#define FP32CTX_2 (FP32CTX_0 + (1 * 8)) -#define FP32CTX_4 (FP32CTX_0 + (2 * 8)) -#define FP32CTX_6 (FP32CTX_0 + (3 * 8)) -#define FP32CTX_8 (FP32CTX_0 + (4 * 8)) -#define FP32CTX_10 (FP32CTX_0 + (5 * 8)) -#define FP32CTX_12 (FP32CTX_0 + (6 * 8)) -#define FP32CTX_14 (FP32CTX_0 + (7 * 8)) -#define FP32CTX_16 (FP32CTX_0 + (8 * 8)) -#define FP32CTX_18 (FP32CTX_0 + (9 * 8)) -#define FP32CTX_20 (FP32CTX_0 + (10 * 8)) -#define FP32CTX_22 (FP32CTX_0 + (11 * 8)) -#define FP32CTX_24 (FP32CTX_0 + (12 * 8)) -#define FP32CTX_26 (FP32CTX_0 + (13 * 8)) -#define FP32CTX_28 (FP32CTX_0 + (14 * 8)) -#define FP32CTX_30 (FP32CTX_0 + (15 * 8)) -#define FP32CTX_SIZE (FP32CTX_30 + (17 * 8)) +#define FP32CTX_0 ((SZREG)*4) +#define FP32CTX_2 (FP32CTX_0 + (1 * 8)) +#define FP32CTX_4 (FP32CTX_0 + (2 * 8)) +#define FP32CTX_6 (FP32CTX_0 + (3 * 8)) +#define FP32CTX_8 (FP32CTX_0 + (4 * 8)) +#define FP32CTX_10 (FP32CTX_0 + (5 * 8)) +#define FP32CTX_12 (FP32CTX_0 + (6 * 8)) +#define FP32CTX_14 (FP32CTX_0 + (7 * 8)) +#define FP32CTX_16 (FP32CTX_0 + (8 * 8)) +#define FP32CTX_18 (FP32CTX_0 + (9 * 8)) +#define FP32CTX_20 (FP32CTX_0 + (10 * 8)) +#define FP32CTX_22 (FP32CTX_0 + (11 * 8)) +#define FP32CTX_24 (FP32CTX_0 + (12 * 8)) +#define FP32CTX_26 (FP32CTX_0 + (13 * 8)) +#define FP32CTX_28 (FP32CTX_0 + (14 * 8)) +#define FP32CTX_30 (FP32CTX_0 + (15 * 8)) +#define FP32CTX_SIZE (FP32CTX_30 + (17 * 8)) -#define FP64CTX_0 ((SZREG)*4) -#define FP64CTX_2 (FP64CTX_0 + (1 * 8)) -#define FP64CTX_4 (FP64CTX_0 + (2 * 8)) -#define FP64CTX_6 (FP64CTX_0 + (3 * 8)) -#define FP64CTX_8 (FP64CTX_0 + (4 * 8)) -#define FP64CTX_10 (FP64CTX_0 + (5 * 8)) -#define FP64CTX_12 (FP64CTX_0 + (6 * 8)) -#define FP64CTX_14 (FP64CTX_0 + (7 * 8)) -#define FP64CTX_16 (FP64CTX_0 + (8 * 8)) -#define FP64CTX_18 (FP64CTX_0 + (9 * 8)) -#define FP64CTX_20 (FP64CTX_0 + (10 * 8)) -#define FP64CTX_22 (FP64CTX_0 + (11 * 8)) -#define FP64CTX_24 (FP64CTX_0 + (12 * 8)) -#define FP64CTX_26 (FP64CTX_0 + (13 * 8)) -#define FP64CTX_28 (FP64CTX_0 + (14 * 8)) -#define FP64CTX_30 (FP64CTX_0 + (15 * 8)) -#define FP64CTX_1 (FP64CTX_30 + (1 * 8)) -#define FP64CTX_3 (FP64CTX_30 + (2 * 8)) -#define FP64CTX_5 (FP64CTX_30 + (3 * 8)) -#define FP64CTX_7 (FP64CTX_30 + (4 * 8)) -#define FP64CTX_9 (FP64CTX_30 + (5 * 8)) -#define FP64CTX_11 (FP64CTX_30 + (6 * 8)) -#define FP64CTX_13 (FP64CTX_30 + (7 * 8)) -#define FP64CTX_15 (FP64CTX_30 + (8 * 8)) -#define FP64CTX_17 (FP64CTX_30 + (9 * 8)) -#define FP64CTX_19 (FP64CTX_30 + (10 * 8)) -#define FP64CTX_21 (FP64CTX_30 + (11 * 8)) -#define FP64CTX_23 (FP64CTX_30 + (12 * 8)) -#define FP64CTX_25 (FP64CTX_30 + (13 * 8)) -#define FP64CTX_27 (FP64CTX_30 + (14 * 8)) -#define FP64CTX_29 (FP64CTX_30 + (15 * 8)) -#define FP64CTX_31 (FP64CTX_30 + (16 * 8)) -#define FP64CTX_SIZE (FP64CTX_31 + (17 * 8)) +#define FP64CTX_0 ((SZREG)*4) +#define FP64CTX_2 (FP64CTX_0 + (1 * 8)) +#define FP64CTX_4 (FP64CTX_0 + (2 * 8)) +#define FP64CTX_6 (FP64CTX_0 + (3 * 8)) +#define FP64CTX_8 (FP64CTX_0 + (4 * 8)) +#define FP64CTX_10 (FP64CTX_0 + (5 * 8)) +#define FP64CTX_12 (FP64CTX_0 + (6 * 8)) +#define FP64CTX_14 (FP64CTX_0 + (7 * 8)) +#define FP64CTX_16 (FP64CTX_0 + (8 * 8)) +#define FP64CTX_18 (FP64CTX_0 + (9 * 8)) +#define FP64CTX_20 (FP64CTX_0 + (10 * 8)) +#define FP64CTX_22 (FP64CTX_0 + (11 * 8)) +#define FP64CTX_24 (FP64CTX_0 + (12 * 8)) +#define FP64CTX_26 (FP64CTX_0 + (13 * 8)) +#define FP64CTX_28 (FP64CTX_0 + (14 * 8)) +#define FP64CTX_30 (FP64CTX_0 + (15 * 8)) +#define FP64CTX_1 (FP64CTX_30 + (1 * 8)) +#define FP64CTX_3 (FP64CTX_30 + (2 * 8)) +#define FP64CTX_5 (FP64CTX_30 + (3 * 8)) +#define FP64CTX_7 (FP64CTX_30 + (4 * 8)) +#define FP64CTX_9 (FP64CTX_30 + (5 * 8)) +#define FP64CTX_11 (FP64CTX_30 + (6 * 8)) +#define FP64CTX_13 (FP64CTX_30 + (7 * 8)) +#define FP64CTX_15 (FP64CTX_30 + (8 * 8)) +#define FP64CTX_17 (FP64CTX_30 + (9 * 8)) +#define FP64CTX_19 (FP64CTX_30 + (10 * 8)) +#define FP64CTX_21 (FP64CTX_30 + (11 * 8)) +#define FP64CTX_23 (FP64CTX_30 + (12 * 8)) +#define FP64CTX_25 (FP64CTX_30 + (13 * 8)) +#define FP64CTX_27 (FP64CTX_30 + (14 * 8)) +#define FP64CTX_29 (FP64CTX_30 + (15 * 8)) +#define FP64CTX_31 (FP64CTX_30 + (16 * 8)) +#define FP64CTX_SIZE (FP64CTX_31 + (17 * 8)) -#define FPCTX_SIZE() (mips_getsr() & ST0_FR ? FP64CTX_SIZE : FP32CTX_SIZE) +#define FPCTX_SIZE() (mips_getsr() & ST0_FR ? FP64CTX_SIZE : FP32CTX_SIZE) /* * The following macros are especially useful for __asm__ @@ -265,7 +265,7 @@ struct fp64ctx /* * TX39 Series */ -#define CP0_TX39_CACHE $7 +#define CP0_TX39_CACHE $7 /* * Coprocessor 1 (FPU) register names @@ -332,38 +332,38 @@ struct fp64ctx /* Why doesn't stupidity hurt ... */ -#define PM_1K 0x00000000 -#define PM_4K 0x00001800 -#define PM_16K 0x00007800 -#define PM_64K 0x0001f800 -#define PM_256K 0x0007f800 +#define PM_1K 0x00000000 +#define PM_4K 0x00001800 +#define PM_16K 0x00007800 +#define PM_64K 0x0001f800 +#define PM_256K 0x0007f800 #else -#define PM_4K 0x00000000 -#define PM_16K 0x00006000 -#define PM_64K 0x0001e000 -#define PM_256K 0x0007e000 -#define PM_1M 0x001fe000 -#define PM_4M 0x007fe000 -#define PM_16M 0x01ffe000 -#define PM_64M 0x07ffe000 -#define PM_256M 0x1fffe000 +#define PM_4K 0x00000000 +#define PM_16K 0x00006000 +#define PM_64K 0x0001e000 +#define PM_256K 0x0007e000 +#define PM_1M 0x001fe000 +#define PM_4M 0x007fe000 +#define PM_16M 0x01ffe000 +#define PM_64M 0x07ffe000 +#define PM_256M 0x1fffe000 #endif /* * Values used for computation of new tlb entries */ -#define PL_4K 12 -#define PL_16K 14 -#define PL_64K 16 -#define PL_256K 18 -#define PL_1M 20 -#define PL_4M 22 -#define PL_16M 24 -#define PL_64M 26 -#define PL_256M 28 +#define PL_4K 12 +#define PL_16K 14 +#define PL_64K 16 +#define PL_256K 18 +#define PL_1M 20 +#define PL_4M 22 +#define PL_16M 24 +#define PL_64M 26 +#define PL_256M 28 /* * R4x00 interrupt enable / cause bits @@ -392,234 +392,234 @@ struct fp64ctx /* * Bitfields in the R4xx0 cp0 status register */ -#define ST0_IE 0x00000001 -#define ST0_EXL 0x00000002 -#define ST0_ERL 0x00000004 -#define ST0_KSU 0x00000018 -# define KSU_USER 0x00000010 -# define KSU_SUPERVISOR 0x00000008 -# define KSU_KERNEL 0x00000000 -#define ST0_UX 0x00000020 -#define ST0_SX 0x00000040 -#define ST0_KX 0x00000080 -#define ST0_DE 0x00010000 -#define ST0_CE 0x00020000 +#define ST0_IE 0x00000001 +#define ST0_EXL 0x00000002 +#define ST0_ERL 0x00000004 +#define ST0_KSU 0x00000018 +# define KSU_USER 0x00000010 +# define KSU_SUPERVISOR 0x00000008 +# define KSU_KERNEL 0x00000000 +#define ST0_UX 0x00000020 +#define ST0_SX 0x00000040 +#define ST0_KX 0x00000080 +#define ST0_DE 0x00010000 +#define ST0_CE 0x00020000 /* * Bitfields in the R[23]000 cp0 status register. */ #define ST0_IEC 0x00000001 -#define ST0_KUC 0x00000002 -#define ST0_IEP 0x00000004 -#define ST0_KUP 0x00000008 -#define ST0_IEO 0x00000010 -#define ST0_KUO 0x00000020 +#define ST0_KUC 0x00000002 +#define ST0_IEP 0x00000004 +#define ST0_KUP 0x00000008 +#define ST0_IEO 0x00000010 +#define ST0_KUO 0x00000020 /* bits 6 & 7 are reserved on R[23]000 */ -#define ST0_ISC 0x00010000 -#define ST0_SWC 0x00020000 -#define ST0_CM 0x00080000 +#define ST0_ISC 0x00010000 +#define ST0_SWC 0x00020000 +#define ST0_CM 0x00080000 /* * Bits specific to the R4640/R4650 */ -#define ST0_UM (_ULCAST_(1) << 4) -#define ST0_IL (_ULCAST_(1) << 23) -#define ST0_DL (_ULCAST_(1) << 24) +#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_IL (_ULCAST_(1) << 23) +#define ST0_DL (_ULCAST_(1) << 24) /* * Bitfields in the TX39 family CP0 Configuration Register 3 */ -#define TX39_CONF_ICS_SHIFT 19 -#define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 +#define TX39_CONF_ICS_SHIFT 19 +#define TX39_CONF_ICS_MASK 0x00380000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 -#define TX39_CONF_DCS_SHIFT 16 -#define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 +#define TX39_CONF_DCS_SHIFT 16 +#define TX39_CONF_DCS_MASK 0x00070000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 -#define TX39_CONF_RF_SHIFT 10 -#define TX39_CONF_RF_MASK 0x00000c00 -#define TX39_CONF_DOZE 0x00000200 -#define TX39_CONF_HALT 0x00000100 -#define TX39_CONF_LOCK 0x00000080 -#define TX39_CONF_ICE 0x00000020 -#define TX39_CONF_DCE 0x00000010 -#define TX39_CONF_IRSIZE_SHIFT 2 -#define TX39_CONF_IRSIZE_MASK 0x0000000c -#define TX39_CONF_DRSIZE_SHIFT 0 -#define TX39_CONF_DRSIZE_MASK 0x00000003 +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_RF_SHIFT 10 +#define TX39_CONF_RF_MASK 0x00000c00 +#define TX39_CONF_DOZE 0x00000200 +#define TX39_CONF_HALT 0x00000100 +#define TX39_CONF_LOCK 0x00000080 +#define TX39_CONF_ICE 0x00000020 +#define TX39_CONF_DCE 0x00000010 +#define TX39_CONF_IRSIZE_SHIFT 2 +#define TX39_CONF_IRSIZE_MASK 0x0000000c +#define TX39_CONF_DRSIZE_SHIFT 0 +#define TX39_CONF_DRSIZE_MASK 0x00000003 /* * Status register bits available in all MIPS CPUs. */ -#define ST0_IM 0x0000ff00 -#define STATUSB_IP0 8 -#define STATUSF_IP0 (_ULCAST_(1) << 8) -#define STATUSB_IP1 9 -#define STATUSF_IP1 (_ULCAST_(1) << 9) -#define STATUSB_IP2 10 -#define STATUSF_IP2 (_ULCAST_(1) << 10) -#define STATUSB_IP3 11 -#define STATUSF_IP3 (_ULCAST_(1) << 11) -#define STATUSB_IP4 12 -#define STATUSF_IP4 (_ULCAST_(1) << 12) -#define STATUSB_IP5 13 -#define STATUSF_IP5 (_ULCAST_(1) << 13) -#define STATUSB_IP6 14 -#define STATUSF_IP6 (_ULCAST_(1) << 14) -#define STATUSB_IP7 15 -#define STATUSF_IP7 (_ULCAST_(1) << 15) -#define STATUSB_IP8 0 -#define STATUSF_IP8 (_ULCAST_(1) << 0) -#define STATUSB_IP9 1 -#define STATUSF_IP9 (_ULCAST_(1) << 1) -#define STATUSB_IP10 2 -#define STATUSF_IP10 (_ULCAST_(1) << 2) -#define STATUSB_IP11 3 -#define STATUSF_IP11 (_ULCAST_(1) << 3) -#define STATUSB_IP12 4 -#define STATUSF_IP12 (_ULCAST_(1) << 4) -#define STATUSB_IP13 5 -#define STATUSF_IP13 (_ULCAST_(1) << 5) -#define STATUSB_IP14 6 -#define STATUSF_IP14 (_ULCAST_(1) << 6) -#define STATUSB_IP15 7 -#define STATUSF_IP15 (_ULCAST_(1) << 7) -#define ST0_CH 0x00040000 -#define ST0_SR 0x00100000 -#define ST0_TS 0x00200000 -#define ST0_BEV 0x00400000 -#define ST0_RE 0x02000000 -#define ST0_FR 0x04000000 -#define ST0_CU 0xf0000000 -#define ST0_CU0 0x10000000 -#define ST0_CU1 0x20000000 -#define ST0_CU1_SHIFT 29 -#define ST0_CU2 0x40000000 -#define ST0_CU3 0x80000000 -#define ST0_XX 0x80000000 /* MIPS IV naming */ +#define ST0_IM 0x0000ff00 +#define STATUSB_IP0 8 +#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define ST0_CH 0x00040000 +#define ST0_SR 0x00100000 +#define ST0_TS 0x00200000 +#define ST0_BEV 0x00400000 +#define ST0_RE 0x02000000 +#define ST0_FR 0x04000000 +#define ST0_CU 0xf0000000 +#define ST0_CU0 0x10000000 +#define ST0_CU1 0x20000000 +#define ST0_CU1_SHIFT 29 +#define ST0_CU2 0x40000000 +#define ST0_CU3 0x80000000 +#define ST0_XX 0x80000000 /* MIPS IV naming */ /* * Bitfields and bit numbers in the coprocessor 0 cause register. * * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. */ -#define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) -#define CAUSEB_IP 8 -#define CAUSEF_IP (_ULCAST_(255) << 8) -#define CAUSEB_IP0 8 -#define CAUSEF_IP0 (_ULCAST_(1) << 8) -#define CAUSEB_IP1 9 -#define CAUSEF_IP1 (_ULCAST_(1) << 9) -#define CAUSEB_IP2 10 -#define CAUSEF_IP2 (_ULCAST_(1) << 10) -#define CAUSEB_IP3 11 -#define CAUSEF_IP3 (_ULCAST_(1) << 11) -#define CAUSEB_IP4 12 -#define CAUSEF_IP4 (_ULCAST_(1) << 12) -#define CAUSEB_IP5 13 -#define CAUSEF_IP5 (_ULCAST_(1) << 13) -#define CAUSEB_IP6 14 -#define CAUSEF_IP6 (_ULCAST_(1) << 14) -#define CAUSEB_IP7 15 -#define CAUSEF_IP7 (_ULCAST_(1) << 15) -#define CAUSEB_IV 23 -#define CAUSEF_IV (_ULCAST_(1) << 23) -#define CAUSEB_CE 28 -#define CAUSEF_CE (_ULCAST_(3) << 28) -#define CAUSEB_BD 31 -#define CAUSEF_BD (_ULCAST_(1) << 31) +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEB_IV 23 +#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_CE 28 +#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_BD 31 +#define CAUSEF_BD (_ULCAST_(1) << 31) /* * Bits in the coprocessor 0 config register. */ /* Generic bits. */ -#define CONF_CM_CACHABLE_NO_WA 0 -#define CONF_CM_CACHABLE_WA 1 -#define CONF_CM_UNCACHED 2 -#define CONF_CM_CACHABLE_NONCOHERENT 3 -#define CONF_CM_CACHABLE_CE 4 -#define CONF_CM_CACHABLE_COW 5 -#define CONF_CM_CACHABLE_CUW 6 -#define CONF_CM_CACHABLE_ACCELERATED 7 -#define CONF_CM_CMASK 7 -#define CONF_BE (_ULCAST_(1) << 15) +#define CONF_CM_CACHABLE_NO_WA 0 +#define CONF_CM_CACHABLE_WA 1 +#define CONF_CM_UNCACHED 2 +#define CONF_CM_CACHABLE_NONCOHERENT 3 +#define CONF_CM_CACHABLE_CE 4 +#define CONF_CM_CACHABLE_COW 5 +#define CONF_CM_CACHABLE_CUW 6 +#define CONF_CM_CACHABLE_ACCELERATED 7 +#define CONF_CM_CMASK 7 +#define CONF_BE (_ULCAST_(1) << 15) /* Bits common to various processors. */ -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_DC (_ULCAST_(7) << 6) -#define CONF_IC (_ULCAST_(7) << 9) -#define CONF_EB (_ULCAST_(1) << 13) -#define CONF_EM (_ULCAST_(1) << 14) -#define CONF_SM (_ULCAST_(1) << 16) -#define CONF_SC (_ULCAST_(1) << 17) -#define CONF_EW (_ULCAST_(3) << 18) -#define CONF_EP (_ULCAST_(15)<< 24) -#define CONF_EC (_ULCAST_(7) << 28) -#define CONF_CM (_ULCAST_(1) << 31) +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_EB (_ULCAST_(1) << 13) +#define CONF_EM (_ULCAST_(1) << 14) +#define CONF_SM (_ULCAST_(1) << 16) +#define CONF_SC (_ULCAST_(1) << 17) +#define CONF_EW (_ULCAST_(3) << 18) +#define CONF_EP (_ULCAST_(15)<< 24) +#define CONF_EC (_ULCAST_(7) << 28) +#define CONF_CM (_ULCAST_(1) << 31) /* Bits specific to the R4xx0. */ -#define R4K_CONF_SW (_ULCAST_(1) << 20) -#define R4K_CONF_SS (_ULCAST_(1) << 21) -#define R4K_CONF_SB (_ULCAST_(3) << 22) +#define R4K_CONF_SW (_ULCAST_(1) << 20) +#define R4K_CONF_SS (_ULCAST_(1) << 21) +#define R4K_CONF_SB (_ULCAST_(3) << 22) /* Bits specific to the R5000. */ -#define R5K_CONF_SE (_ULCAST_(1) << 12) -#define R5K_CONF_SS (_ULCAST_(3) << 20) +#define R5K_CONF_SE (_ULCAST_(1) << 12) +#define R5K_CONF_SS (_ULCAST_(3) << 20) /* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) -#define R10K_CONF_SB (_ULCAST_(1) << 13) -#define R10K_CONF_SK (_ULCAST_(1) << 14) -#define R10K_CONF_SS (_ULCAST_(7) << 16) -#define R10K_CONF_SC (_ULCAST_(7) << 19) -#define R10K_CONF_DC (_ULCAST_(7) << 26) -#define R10K_CONF_IC (_ULCAST_(7) << 29) +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15)<< 9) +#define R10K_CONF_SB (_ULCAST_(1) << 13) +#define R10K_CONF_SK (_ULCAST_(1) << 14) +#define R10K_CONF_SS (_ULCAST_(7) << 16) +#define R10K_CONF_SC (_ULCAST_(7) << 19) +#define R10K_CONF_DC (_ULCAST_(7) << 26) +#define R10K_CONF_IC (_ULCAST_(7) << 29) /* Bits specific to the VR41xx. */ -#define VR41_CONF_CS (_ULCAST_(1) << 12) -#define VR41_CONF_M16 (_ULCAST_(1) << 20) -#define VR41_CONF_AD (_ULCAST_(1) << 23) +#define VR41_CONF_CS (_ULCAST_(1) << 12) +#define VR41_CONF_M16 (_ULCAST_(1) << 20) +#define VR41_CONF_AD (_ULCAST_(1) << 23) /* Bits specific to the R30xx. */ -#define R30XX_CONF_FDM (_ULCAST_(1) << 19) -#define R30XX_CONF_REV (_ULCAST_(1) << 22) -#define R30XX_CONF_AC (_ULCAST_(1) << 23) -#define R30XX_CONF_RF (_ULCAST_(1) << 24) -#define R30XX_CONF_HALT (_ULCAST_(1) << 25) -#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) -#define R30XX_CONF_DBR (_ULCAST_(1) << 29) -#define R30XX_CONF_SB (_ULCAST_(1) << 30) -#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) +#define R30XX_CONF_FDM (_ULCAST_(1) << 19) +#define R30XX_CONF_REV (_ULCAST_(1) << 22) +#define R30XX_CONF_AC (_ULCAST_(1) << 23) +#define R30XX_CONF_RF (_ULCAST_(1) << 24) +#define R30XX_CONF_HALT (_ULCAST_(1) << 25) +#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) +#define R30XX_CONF_DBR (_ULCAST_(1) << 29) +#define R30XX_CONF_SB (_ULCAST_(1) << 30) +#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) /* Bits specific to the TX49. */ -#define TX49_CONF_DC (_ULCAST_(1) << 16) -#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ -#define TX49_CONF_HALT (_ULCAST_(1) << 18) -#define TX49_CONF_CWFON (_ULCAST_(1) << 27) +#define TX49_CONF_DC (_ULCAST_(1) << 16) +#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ +#define TX49_CONF_HALT (_ULCAST_(1) << 18) +#define TX49_CONF_CWFON (_ULCAST_(1) << 27) /* Bits specific to the MIPS32/64 PRA. */ -#define MIPS_CONF_MT (_ULCAST_(7) << 7) -#define MIPS_CONF_AR (_ULCAST_(7) << 10) -#define MIPS_CONF_AT (_ULCAST_(3) << 13) -#define MIPS_CONF_M (_ULCAST_(1) << 31) +#define MIPS_CONF_MT (_ULCAST_(7) << 7) +#define MIPS_CONF_AR (_ULCAST_(7) << 10) +#define MIPS_CONF_AT (_ULCAST_(3) << 13) +#define MIPS_CONF_M (_ULCAST_(1) << 31) /* * R10000 performance counter definitions. @@ -632,50 +632,50 @@ struct fp64ctx /* * Events counted by counter #0 */ -#define CE0_CYCLES 0 -#define CE0_INSN_ISSUED 1 -#define CE0_LPSC_ISSUED 2 -#define CE0_S_ISSUED 3 -#define CE0_SC_ISSUED 4 -#define CE0_SC_FAILED 5 -#define CE0_BRANCH_DECODED 6 -#define CE0_QW_WB_SECONDARY 7 -#define CE0_CORRECTED_ECC_ERRORS 8 -#define CE0_ICACHE_MISSES 9 -#define CE0_SCACHE_I_MISSES 10 -#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 -#define CE0_EXT_INTERVENTIONS_REQ 12 -#define CE0_EXT_INVALIDATE_REQ 13 -#define CE0_VIRTUAL_COHERENCY_COND 14 -#define CE0_INSN_GRADUATED 15 +#define CE0_CYCLES 0 +#define CE0_INSN_ISSUED 1 +#define CE0_LPSC_ISSUED 2 +#define CE0_S_ISSUED 3 +#define CE0_SC_ISSUED 4 +#define CE0_SC_FAILED 5 +#define CE0_BRANCH_DECODED 6 +#define CE0_QW_WB_SECONDARY 7 +#define CE0_CORRECTED_ECC_ERRORS 8 +#define CE0_ICACHE_MISSES 9 +#define CE0_SCACHE_I_MISSES 10 +#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 +#define CE0_EXT_INTERVENTIONS_REQ 12 +#define CE0_EXT_INVALIDATE_REQ 13 +#define CE0_VIRTUAL_COHERENCY_COND 14 +#define CE0_INSN_GRADUATED 15 /* * Events counted by counter #1 */ -#define CE1_CYCLES 0 -#define CE1_INSN_GRADUATED 1 -#define CE1_LPSC_GRADUATED 2 -#define CE1_S_GRADUATED 3 -#define CE1_SC_GRADUATED 4 -#define CE1_FP_INSN_GRADUATED 5 -#define CE1_QW_WB_PRIMARY 6 -#define CE1_TLB_REFILL 7 -#define CE1_BRANCH_MISSPREDICTED 8 -#define CE1_DCACHE_MISS 9 -#define CE1_SCACHE_D_MISSES 10 -#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 -#define CE1_EXT_INTERVENTION_HITS 12 -#define CE1_EXT_INVALIDATE_REQ 13 -#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 -#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 +#define CE1_CYCLES 0 +#define CE1_INSN_GRADUATED 1 +#define CE1_LPSC_GRADUATED 2 +#define CE1_S_GRADUATED 3 +#define CE1_SC_GRADUATED 4 +#define CE1_FP_INSN_GRADUATED 5 +#define CE1_QW_WB_PRIMARY 6 +#define CE1_TLB_REFILL 7 +#define CE1_BRANCH_MISSPREDICTED 8 +#define CE1_DCACHE_MISS 9 +#define CE1_SCACHE_D_MISSES 10 +#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 +#define CE1_EXT_INTERVENTION_HITS 12 +#define CE1_EXT_INVALIDATE_REQ 13 +#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 +#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 /* * These flags define in which priviledge mode the counters count events */ -#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ -#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ -#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ -#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ +#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ +#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ +#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ +#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ #ifndef __ASSEMBLY__ @@ -713,272 +713,272 @@ struct fp64ctx * Macros to access the system control coprocessor */ -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ +#define __read_32bit_c0_register(source, sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ }) -#define __read_64bit_c0_register(source, sel) \ -({ unsigned long __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmfc0\t%0, " #source "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - __res; \ +#define __read_64bit_c0_register(source, sel) \ +({ unsigned long __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0, " #source "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res; \ }) -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ +#define __write_32bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ } while (0) -#define __write_64bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmtc0\t%z0, " #register "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ +#define __write_64bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%z0, " #register "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ } while (0) -#define __read_ulong_c0_register(reg, sel) \ - ((sizeof(unsigned long) == 4) ? \ - __read_32bit_c0_register(reg, sel) : \ - __read_64bit_c0_register(reg, sel)) +#define __read_ulong_c0_register(reg, sel) \ + ((sizeof(unsigned long) == 4) ? \ + __read_32bit_c0_register(reg, sel) : \ + __read_64bit_c0_register(reg, sel)) -#define __write_ulong_c0_register(reg, sel, val) \ -do { \ - if (sizeof(unsigned long) == 4) \ - __write_32bit_c0_register(reg, sel, val); \ - else \ - __write_64bit_c0_register(reg, sel, val); \ +#define __write_ulong_c0_register(reg, sel, val) \ +do { \ + if (sizeof(unsigned long) == 4) \ + __write_32bit_c0_register(reg, sel, val); \ + else \ + __write_64bit_c0_register(reg, sel, val); \ } while (0) /* * These versions are only needed for systems with more than 38 bits of * physical address space running the 32-bit kernel. That's none atm :-) */ -#define __read_64bit_c0_split(source, sel) \ -({ \ - unsigned long long val; \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source ", " #sel "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (val)); \ - local_irq_restore(flags); \ - \ - val; \ +#define __read_64bit_c0_split(source, sel) \ +({ \ + unsigned long long val; \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source ", " #sel "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + local_irq_restore(flags); \ + \ + val; \ }) -#define __write_64bit_c0_split(source, sel, val) \ -do { \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - local_irq_restore(flags); \ +#define __write_64bit_c0_split(source, sel, val) \ +do { \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + local_irq_restore(flags); \ } while (0) -#define read_c0_index() __read_32bit_c0_register($0, 0) -#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) +#define read_c0_index() __read_32bit_c0_register($0, 0) +#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) -#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) -#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) +#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) +#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) -#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) -#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) +#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) +#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) -#define read_c0_conf() __read_32bit_c0_register($3, 0) -#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) +#define read_c0_conf() __read_32bit_c0_register($3, 0) +#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) -#define read_c0_context() __read_ulong_c0_register($4, 0) -#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) +#define read_c0_context() __read_ulong_c0_register($4, 0) +#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) -#define read_c0_pagemask() __read_32bit_c0_register($5, 0) -#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) +#define read_c0_pagemask() __read_32bit_c0_register($5, 0) +#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) -#define read_c0_wired() __read_32bit_c0_register($6, 0) -#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) +#define read_c0_wired() __read_32bit_c0_register($6, 0) +#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) -#define read_c0_info() __read_32bit_c0_register($7, 0) +#define read_c0_info() __read_32bit_c0_register($7, 0) -#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ -#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) +#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ +#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) +#define read_c0_count() __read_32bit_c0_register($9, 0) +#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) -#define read_c0_entryhi() __read_ulong_c0_register($10, 0) -#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) +#define read_c0_entryhi() __read_ulong_c0_register($10, 0) +#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) -#define read_c0_compare() __read_32bit_c0_register($11, 0) -#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) +#define read_c0_compare() __read_32bit_c0_register($11, 0) +#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) -#define read_c0_status() __read_32bit_c0_register($12, 0) -#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) +#define read_c0_status() __read_32bit_c0_register($12, 0) +#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) +#define read_c0_cause() __read_32bit_c0_register($13, 0) +#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) -#define read_c0_prid() __read_32bit_c0_register($15, 0) +#define read_c0_prid() __read_32bit_c0_register($15, 0) -#define read_c0_config() __read_32bit_c0_register($16, 0) -#define read_c0_config1() __read_32bit_c0_register($16, 1) -#define read_c0_config2() __read_32bit_c0_register($16, 2) -#define read_c0_config3() __read_32bit_c0_register($16, 3) -#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) -#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) -#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) -#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) +#define read_c0_config() __read_32bit_c0_register($16, 0) +#define read_c0_config1() __read_32bit_c0_register($16, 1) +#define read_c0_config2() __read_32bit_c0_register($16, 2) +#define read_c0_config3() __read_32bit_c0_register($16, 3) +#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) +#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) +#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) +#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) /* * The WatchLo register. There may be upto 8 of them. */ -#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) -#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) -#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) -#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) -#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) -#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) -#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) -#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) -#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) -#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) -#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) -#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) -#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) -#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) -#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) -#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) +#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) +#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) +#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) +#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) +#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) +#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) +#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) +#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) +#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) +#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) +#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) +#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) +#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) +#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) +#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) +#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) /* * The WatchHi register. There may be upto 8 of them. */ -#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) -#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) -#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) -#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) -#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) -#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) -#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) -#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) +#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) +#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) +#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) +#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) +#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) +#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) +#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) +#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) -#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) -#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) -#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) -#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) -#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) -#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) -#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) -#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) +#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) +#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) +#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) +#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) +#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) +#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) +#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) +#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) -#define read_c0_xcontext() __read_ulong_c0_register($20, 0) -#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) +#define read_c0_xcontext() __read_ulong_c0_register($20, 0) +#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) -#define read_c0_intcontrol() __read_32bit_c0_register($20, 1) +#define read_c0_intcontrol() __read_32bit_c0_register($20, 1) #define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val) -#define read_c0_framemask() __read_32bit_c0_register($21, 0) -#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) +#define read_c0_framemask() __read_32bit_c0_register($21, 0) +#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) -#define read_c0_debug() __read_32bit_c0_register($23, 0) -#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) +#define read_c0_debug() __read_32bit_c0_register($23, 0) +#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) -#define read_c0_depc() __read_ulong_c0_register($24, 0) -#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) +#define read_c0_depc() __read_ulong_c0_register($24, 0) +#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) -#define read_c0_ecc() __read_32bit_c0_register($26, 0) -#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) +#define read_c0_ecc() __read_32bit_c0_register($26, 0) +#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) -#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) -#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) +#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) +#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) -#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) +#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) -#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) -#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) +#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) +#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) -#define read_c0_taglo() __read_32bit_c0_register($28, 0) -#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) +#define read_c0_taglo() __read_32bit_c0_register($28, 0) +#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) -#define read_c0_taghi() __read_32bit_c0_register($29, 0) -#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) +#define read_c0_taghi() __read_32bit_c0_register($29, 0) +#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) -#define read_c0_errorepc() __read_ulong_c0_register($30, 0) -#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) +#define read_c0_errorepc() __read_ulong_c0_register($30, 0) +#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) -#define read_c0_epc() __read_ulong_c0_register($14, 0) -#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) +#define read_c0_epc() __read_ulong_c0_register($14, 0) +#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) #if 1 /* @@ -987,20 +987,20 @@ do { \ #define read_32bit_cp0_register(source) \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "mfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) #define read_32bit_cp0_set1_register(source) \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "cfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) @@ -1018,14 +1018,14 @@ do { \ #define write_32bit_cp0_register(register,value) \ __asm__ __volatile__( \ - "mtc0\t%0,"STR(register)"\n\t" \ - "nop" \ + "mtc0\t%0,"STR(register)"\n\t" \ + "nop" \ : : "r" (value)); #define write_32bit_cp0_set1_register(register,value) \ __asm__ __volatile__( \ - "ctc0\t%0,"STR(register)"\n\t" \ - "nop" \ + "ctc0\t%0,"STR(register)"\n\t" \ + "nop" \ : : "r" (value)); #define write_64bit_cp0_register(register,value) \ @@ -1041,16 +1041,16 @@ do { \ #define read_mips32_cp0_config1() \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n\t" \ - "#.set\tmips64\n\t" \ - "#mfc0\t$1, $16, 1\n\t" \ - "#.set\tmips0\n\t" \ - ".word\t0x40018001\n\t" \ - "move\t%0,$1\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" \ - :"=r" (__res)); \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n\t" \ + "#.set\tmips64\n\t" \ + "#mfc0\t$1, $16, 1\n\t" \ + "#.set\tmips0\n\t" \ + ".word\t0x40018001\n\t" \ + "move\t%0,$1\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" \ + :"=r" (__res)); \ __res;}) #endif @@ -1059,95 +1059,95 @@ do { \ */ #define read_32bit_cp1_register(source) \ ({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) /* TLB operations. */ static inline void tlb_probe(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbp\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbp\n\t" + ".set reorder"); } static inline void tlb_read(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbr\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbr\n\t" + ".set reorder"); } static inline void tlb_write_indexed(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwi\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwi\n\t" + ".set reorder"); } static inline void tlb_write_random(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwr\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwr\n\t" + ".set reorder"); } /* * Manipulate bits in a c0 register. */ -#define __BUILD_SET_C0(name,register) \ -static inline unsigned int \ -set_c0_##name(unsigned int set) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -clear_c0_##name(unsigned int clear) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ - \ - return res; \ +#define __BUILD_SET_C0(name,register) \ +static inline unsigned int \ +set_c0_##name(unsigned int set) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res |= set; \ + write_c0_##name(res); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +clear_c0_##name(unsigned int clear) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res &= ~clear; \ + write_c0_##name(res); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +change_c0_##name(unsigned int change, unsigned int new) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res &= ~change; \ + res |= (new & change); \ + write_c0_##name(res); \ + \ + return res; \ } __BUILD_SET_C0(status,CP0_STATUS) __BUILD_SET_C0(cause,CP0_CAUSE) __BUILD_SET_C0(config,CP0_CONFIG) -#define set_cp0_status(x) set_c0_status(x) -#define set_cp0_cause(x) set_c0_cause(x) -#define set_cp0_config(x) set_c0_config(x) +#define set_cp0_status(x) set_c0_status(x) +#define set_cp0_cause(x) set_c0_cause(x) +#define set_cp0_config(x) set_c0_config(x) #endif /* !__ASSEMBLY__ */ diff --git a/libcpu/mips/common/mipscfg.h b/libcpu/mips/common/mipscfg.h index b4f30615f8..f4761be73d 100644 --- a/libcpu/mips/common/mipscfg.h +++ b/libcpu/mips/common/mipscfg.h @@ -24,7 +24,7 @@ typedef struct mips32_core_cfg rt_uint16_t dcache_lines_per_way; rt_uint16_t dcache_ways; - rt_uint16_t max_tlb_entries; /* number of tlb entry */ + rt_uint16_t max_tlb_entries; /* number of tlb entry */ } mips32_core_cfg_t; extern mips32_core_cfg_t g_mips_core; diff --git a/libcpu/mips/loongson_1b/cache.c b/libcpu/mips/loongson_1b/cache.c index 842f392cb7..ccfdda95d3 100644 --- a/libcpu/mips/loongson_1b/cache.c +++ b/libcpu/mips/loongson_1b/cache.c @@ -12,12 +12,12 @@ * 2010-07-09 Bernard first version * 2011-08-08 lgnq modified for LS1B */ - + #include <rtthread.h> #include "../common/mipsregs.h" -#define K0BASE 0x80000000 -#define PRID_LS1B 0x4220 +#define K0BASE 0x80000000 +#define PRID_LS1B 0x4220 extern void Clear_TagLo (void); extern void Invalidate_Icache_Ls1b(unsigned int); @@ -26,21 +26,21 @@ extern void Invalidate_Dcache_Fill_Ls1b(unsigned int); extern void Writeback_Invalidate_Dcache(unsigned int); extern void enable_cpu_cache(void); -typedef struct cacheinfo_t +typedef struct cacheinfo_t { - unsigned int icache_size; - unsigned int dcache_size; - unsigned int icacheline_size; - unsigned int dcacheline_size; + unsigned int icache_size; + unsigned int dcache_size; + unsigned int icacheline_size; + unsigned int dcacheline_size; } cacheinfo_t ; -typedef struct cacheop_t +typedef struct cacheop_t { - void (*Clear_TagLo) (void); - void (*Invalidate_Icache) (unsigned int); - void (*Invalidate_Dcache_Fill) (unsigned int); - void (*Invalidate_Dcache_ClearTag) (unsigned int); - void (*Init_Cache)(void); + void (*Clear_TagLo) (void); + void (*Invalidate_Icache) (unsigned int); + void (*Invalidate_Dcache_Fill) (unsigned int); + void (*Invalidate_Dcache_ClearTag) (unsigned int); + void (*Init_Cache)(void); } cacheop_t ; static cacheop_t cacheop, *pcacheop; @@ -53,24 +53,24 @@ int identify_cpu(void) pcacheop = &cacheop; pcacheinfo = &cacheinfo; - rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); + rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); cpu_id = read_c0_prid(); switch (cpu_id) - { - case PRID_LS1B: - rt_kprintf("CPU:LS1B\n"); - pcacheop->Clear_TagLo = Clear_TagLo; - pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b; - pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b; - pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b; - break; - default: - rt_kprintf("Unknown CPU type, system halted!\n"); - while (1) - { - ; - } - break; + { + case PRID_LS1B: + rt_kprintf("CPU:LS1B\n"); + pcacheop->Clear_TagLo = Clear_TagLo; + pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b; + pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b; + pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b; + break; + default: + rt_kprintf("Unknown CPU type, system halted!\n"); + while (1) + { + ; + } + break; } return 0; @@ -89,7 +89,7 @@ void probe_cache(void) icache_sets = 64 << ((config1 >> 22) & 7); icache_ways = 1 + ((config1 >> 16) & 7); icache_size = icache_sets * icache_ways * icache_line_size; - + if ((dcache_line_size = ((config1 >> 10) & 7))) dcache_line_size = 2 << dcache_line_size; else @@ -97,7 +97,7 @@ void probe_cache(void) dcache_sets = 64 << ((config1 >> 13) & 7); dcache_ways = 1 + ((config1 >> 7) & 7); dcache_size = dcache_sets * dcache_ways * dcache_line_size; - + rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size); rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size); @@ -111,120 +111,120 @@ void probe_cache(void) void invalidate_writeback_dcache_all(void) { - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); - while (start < end) - { - Writeback_Invalidate_Dcache(start); //hit writeback invalidate - start += pcacheinfo->dcacheline_size; - } + while (start < end) + { + Writeback_Invalidate_Dcache(start); //hit writeback invalidate + start += pcacheinfo->dcacheline_size; + } } void invalidate_writeback_dcache(unsigned long addr, int size) { - unsigned long start, end; - - start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); - end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); - - while (start <end) - { - Writeback_Invalidate_Dcache(start); - start += pcacheinfo->dcacheline_size; - } + unsigned long start, end; + + start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); + end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); + + while (start <end) + { + Writeback_Invalidate_Dcache(start); + start += pcacheinfo->dcacheline_size; + } } void invalidate_icache_all(void) { - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->icache_size); + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->icache_size); - while (start < end) - { - pcacheop->Invalidate_Icache(start); - start += pcacheinfo->icacheline_size; - } + while (start < end) + { + pcacheop->Invalidate_Icache(start); + start += pcacheinfo->icacheline_size; + } } void invalidate_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - while (start <end) - { - Invalidate_Dcache_Fill_Ls1b(start); - start += pcacheinfo->icacheline_size; - } +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + while (start <end) + { + Invalidate_Dcache_Fill_Ls1b(start); + start += pcacheinfo->icacheline_size; + } } //with cache disabled void init_dcache(void) { - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); - while (start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } + while (start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } } void rt_hw_cache_init(void) { unsigned int start, end; - - /* 1. identify cpu and probe cache */ - identify_cpu(); - probe_cache(); - start = K0BASE; - end = (start + pcacheinfo->icache_size); + /* 1. identify cpu and probe cache */ + identify_cpu(); + probe_cache(); + + start = K0BASE; + end = (start + pcacheinfo->icache_size); /* - * 2. clear CP0 taglo/taghi register; + * 2. clear CP0 taglo/taghi register; */ pcacheop->Clear_TagLo(); - /* - * 3. invalidate instruction cache; + /* + * 3. invalidate instruction cache; */ - while (start < end) + while (start < end) { - pcacheop->Invalidate_Icache(start); //index invalidate icache - start += pcacheinfo->icacheline_size; + pcacheop->Invalidate_Icache(start); //index invalidate icache + start += pcacheinfo->icacheline_size; } /* - * 4. invalidate data cache; + * 4. invalidate data cache; */ start = K0BASE; end = (start + pcacheinfo->dcache_size); - while(start < end) + while(start < end) { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; } start = K0BASE; - while(start < end) + while(start < end) { - pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache - start += pcacheinfo->dcacheline_size; + pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache + start += pcacheinfo->dcacheline_size; } start = K0BASE; - while(start < end) + while(start < end) { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; } - /* enable cache */ - enable_cpu_cache(); - rt_kprintf("enable cpu cache done\n"); + /* enable cache */ + enable_cpu_cache(); + rt_kprintf("enable cpu cache done\n"); - return ; + return ; } diff --git a/libcpu/mips/loongson_1b/cache.h b/libcpu/mips/loongson_1b/cache.h index b5c2d4501e..8ca015ef4f 100644 --- a/libcpu/mips/loongson_1b/cache.h +++ b/libcpu/mips/loongson_1b/cache.h @@ -12,8 +12,8 @@ * 2010-07-09 Bernard first version * 2011-08-08 lgnq modified for LS1B */ -#ifndef __CACHE_H__ -#define __CACHE_H__ +#ifndef __CACHE_H__ +#define __CACHE_H__ /* * Cache Operations @@ -22,31 +22,31 @@ #define Index_Writeback_Inv_D 0x01 #define Index_Invalidate_SI 0x02 #define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 /* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 /* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b +#define Hit_Writeback_SD 0x1b /* 0x1c is unused */ /* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f #endif diff --git a/libcpu/mips/loongson_1b/cpuport.c b/libcpu/mips/loongson_1b/cpuport.c index c095c04814..23399800f5 100644 --- a/libcpu/mips/loongson_1b/cpuport.c +++ b/libcpu/mips/loongson_1b/cpuport.c @@ -28,13 +28,13 @@ */ void rt_hw_cpu_reset(void) { - /* open the watch-dog */ - WDT_EN = 0x01; /* watch dog enable */ - WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ - WDT_SET = 0x01; /* watch dog start */ + /* open the watch-dog */ + WDT_EN = 0x01; /* watch dog enable */ + WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ + WDT_SET = 0x01; /* watch dog start */ - rt_kprintf("reboot system...\n"); - while (1); + rt_kprintf("reboot system...\n"); + while (1); } /** @@ -43,9 +43,9 @@ void rt_hw_cpu_reset(void) */ void rt_hw_cpu_shutdown(void) { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } extern rt_uint32_t cp0_get_cause(void); @@ -65,59 +65,59 @@ extern rt_uint32_t cp0_get_lo(void); */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; static rt_uint32_t g_sr = 0; if (g_sr == 0) { - g_sr = cp0_get_status(); - g_sr &= 0xfffffffe; - g_sr |= 0x8401; + g_sr = cp0_get_status(); + g_sr &= 0xfffffffe; + g_sr |= 0x8401; } /** Start at stack top */ stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ - *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ - *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ - *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ - *(--stk) = (rt_uint32_t) texit; /* ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* sp */ - *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ - *(--stk) = (rt_uint32_t) parameter; /* a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ + *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ + *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ + *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ + *(--stk) = (rt_uint32_t) texit; /* ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* sp */ + *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ + *(--stk) = (rt_uint32_t) parameter; /* a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/libcpu/mips/loongson_1b/exception.c b/libcpu/mips/loongson_1b/exception.c index 4a3745cbc5..dbcec42ab6 100644 --- a/libcpu/mips/loongson_1b/exception.c +++ b/libcpu/mips/loongson_1b/exception.c @@ -25,7 +25,7 @@ /** * exception handle table */ -#define RT_EXCEPTION_MAX 8 +#define RT_EXCEPTION_MAX 8 exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; /** @@ -47,45 +47,45 @@ exception_func_t rt_set_except_vector(int n, exception_func_t func) void tlb_refill_handler(void) { - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); + rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); } void cache_error_handler(void) { - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); + rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); } static void unhandled_exception_handle(pt_regs_t *regs) { - rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); + rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); } void install_default_execpt_handle(void) { - rt_int32_t i; + rt_int32_t i; - for (i=0; i<RT_EXCEPTION_MAX; i++) - sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; + for (i=0; i<RT_EXCEPTION_MAX; i++) + sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; } void exception_handler(pt_regs_t *regs) { - rt_uint32_t cause; - rt_uint32_t index; + rt_uint32_t cause; + rt_uint32_t index; - cause = (read_c0_cause() & read_c0_config()); - cause = (cause & 0xfc00) >> 8; + cause = (read_c0_cause() & read_c0_config()); + cause = (cause & 0xfc00) >> 8; - for (index = RT_EXCEPTION_MAX; index > 0; index --) - { - if (cause & (1 << index)) - { - sys_exception_handlers[index](regs); - cause &= ~(1 << index); - } - } + for (index = RT_EXCEPTION_MAX; index > 0; index --) + { + if (cause & (1 << index)) + { + sys_exception_handlers[index](regs); + cause &= ~(1 << index); + } + } } /*@}*/ diff --git a/libcpu/mips/loongson_1b/interrupt.c b/libcpu/mips/loongson_1b/interrupt.c index 998d1e4918..4af9319c55 100644 --- a/libcpu/mips/loongson_1b/interrupt.c +++ b/libcpu/mips/loongson_1b/interrupt.c @@ -51,7 +51,7 @@ void rt_hw_interrupt_init(void) rt_int32_t idx; /* pci active low */ - ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq + ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq /* make all interrupts level triggered */ (ls1b_hw0_icregs+0)->int_edge = 0x0000e000; /* mask all interrupts */ diff --git a/libcpu/mips/loongson_1b/ls1b.h b/libcpu/mips/loongson_1b/ls1b.h index 34393a3448..3dab7f9da2 100644 --- a/libcpu/mips/loongson_1b/ls1b.h +++ b/libcpu/mips/loongson_1b/ls1b.h @@ -1,7 +1,7 @@ /* * File : ls1b.h * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team + * COPYRIGHT (C) 2006-2021, RT-Thread Develop Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -17,35 +17,35 @@ #include "../common/mipsregs.h" -#define LS1B_ACPI_IRQ 0 -#define LS1B_HPET_IRQ 1 -#define LS1B_UART0_IRQ 2 -#define LS1B_UART1_IRQ 3 -#define LS1B_UART2_IRQ 4 -#define LS1B_UART3_IRQ 5 -#define LS1B_CAN0_IRQ 6 -#define LS1B_CAN1_IRQ 7 -#define LS1B_SPI0_IRQ 8 -#define LS1B_SPI1_IRQ 9 -#define LS1B_AC97_IRQ 10 -#define LS1B_MS_IRQ 11 -#define LS1B_KB_IRQ 12 -#define LS1B_DMA0_IRQ 13 -#define LS1B_DMA1_IRQ 14 -#define LS1B_NAND_IRQ 15 -#define LS1B_I2C0_IRQ 16 -#define LS1B_I2C1_IRQ 17 -#define LS1B_PWM0_IRQ 18 -#define LS1B_PWM1_IRQ 19 -#define LS1B_PWM2_IRQ 20 -#define LS1B_PWM3_IRQ 21 -#define LS1B_LPC_IRQ 22 -#define LS1B_EHCI_IRQ 32 -#define LS1B_OHCI_IRQ 33 -#define LS1B_GMAC1_IRQ 34 -#define LS1B_GMAC2_IRQ 35 -#define LS1B_SATA_IRQ 36 -#define LS1B_GPU_IRQ 37 +#define LS1B_ACPI_IRQ 0 +#define LS1B_HPET_IRQ 1 +#define LS1B_UART0_IRQ 2 +#define LS1B_UART1_IRQ 3 +#define LS1B_UART2_IRQ 4 +#define LS1B_UART3_IRQ 5 +#define LS1B_CAN0_IRQ 6 +#define LS1B_CAN1_IRQ 7 +#define LS1B_SPI0_IRQ 8 +#define LS1B_SPI1_IRQ 9 +#define LS1B_AC97_IRQ 10 +#define LS1B_MS_IRQ 11 +#define LS1B_KB_IRQ 12 +#define LS1B_DMA0_IRQ 13 +#define LS1B_DMA1_IRQ 14 +#define LS1B_NAND_IRQ 15 +#define LS1B_I2C0_IRQ 16 +#define LS1B_I2C1_IRQ 17 +#define LS1B_PWM0_IRQ 18 +#define LS1B_PWM1_IRQ 19 +#define LS1B_PWM2_IRQ 20 +#define LS1B_PWM3_IRQ 21 +#define LS1B_LPC_IRQ 22 +#define LS1B_EHCI_IRQ 32 +#define LS1B_OHCI_IRQ 33 +#define LS1B_GMAC1_IRQ 34 +#define LS1B_GMAC2_IRQ 35 +#define LS1B_SATA_IRQ 36 +#define LS1B_GPU_IRQ 37 #define LS1B_PCI_INTA_IRQ 38 #define LS1B_PCI_INTB_IRQ 39 #define LS1B_PCI_INTC_IRQ 40 @@ -56,13 +56,13 @@ #define LS1B_GPIO_IRQ_COUNT 96 #define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1) -#define INT_PCI_INTA (1<<6) -#define INT_PCI_INTB (1<<7) -#define INT_PCI_INTC (1<<8) -#define INT_PCI_INTD (1<<9) +#define INT_PCI_INTA (1<<6) +#define INT_PCI_INTB (1<<7) +#define INT_PCI_INTC (1<<8) +#define INT_PCI_INTD (1<<9) #define LS1B_LAST_IRQ 159 -#define MIPS_CPU_TIMER_IRQ 167 +#define MIPS_CPU_TIMER_IRQ 167 #define LS1B_INTREG_BASE 0xbfd01040 #define LS1B_DMA_IRQ_BASE 168 @@ -70,71 +70,71 @@ struct ls1b_intc_regs { - volatile unsigned int int_isr; - volatile unsigned int int_en; - volatile unsigned int int_set; - volatile unsigned int int_clr; /* offset 0x10*/ - volatile unsigned int int_pol; - volatile unsigned int int_edge; /* offset 0 */ -}; + volatile unsigned int int_isr; + volatile unsigned int int_en; + volatile unsigned int int_set; + volatile unsigned int int_clr; /* offset 0x10*/ + volatile unsigned int int_pol; + volatile unsigned int int_edge; /* offset 0 */ +}; struct ls1b_cop_global_regs { - volatile unsigned int control; - volatile unsigned int rd_inten; - volatile unsigned int wr_inten; - volatile unsigned int rd_intisr; /* offset 0x10*/ - volatile unsigned int wr_intisr; - unsigned int unused[11]; -} ; + volatile unsigned int control; + volatile unsigned int rd_inten; + volatile unsigned int wr_inten; + volatile unsigned int rd_intisr; /* offset 0x10*/ + volatile unsigned int wr_intisr; + unsigned int unused[11]; +} ; struct ls1b_cop_channel_regs { - volatile unsigned int rd_control; - volatile unsigned int rd_src; - volatile unsigned int rd_cnt; - volatile unsigned int rd_status; /* offset 0x10*/ - volatile unsigned int wr_control; - volatile unsigned int wr_src; - volatile unsigned int wr_cnt; - volatile unsigned int wr_status; /* offset 0x10*/ -} ; + volatile unsigned int rd_control; + volatile unsigned int rd_src; + volatile unsigned int rd_cnt; + volatile unsigned int rd_status; /* offset 0x10*/ + volatile unsigned int wr_control; + volatile unsigned int wr_src; + volatile unsigned int wr_cnt; + volatile unsigned int wr_status; /* offset 0x10*/ +} ; struct ls1b_cop_regs { - struct ls1b_cop_global_regs global; - struct ls1b_cop_channel_regs chan[8][2]; + struct ls1b_cop_global_regs global; + struct ls1b_cop_channel_regs chan[8][2]; } ; -#define __REG8(addr) *((volatile unsigned char *)(addr)) -#define __REG16(addr) *((volatile unsigned short *)(addr)) -#define __REG32(addr) *((volatile unsigned int *)(addr)) +#define __REG8(addr) *((volatile unsigned char *)(addr)) +#define __REG16(addr) *((volatile unsigned short *)(addr)) +#define __REG32(addr) *((volatile unsigned int *)(addr)) -#define GMAC0_BASE 0xBFE10000 -#define GMAC0_DMA_BASE 0xBFE11000 -#define GMAC1_BASE 0xBFE20000 -#define GMAC1_DMA_BASE 0xBFE21000 -#define I2C0_BASE 0xBFE58000 -#define PWM0_BASE 0xBFE5C000 -#define PWM1_BASE 0xBFE5C010 -#define PWM2_BASE 0xBFE5C020 -#define PWM3_BASE 0xBFE5C030 -#define WDT_BASE 0xBFE5C060 -#define RTC_BASE 0xBFE64000 -#define I2C1_BASE 0xBFE68000 -#define I2C2_BASE 0xBFE70000 -#define AC97_BASE 0xBFE74000 -#define NAND_BASE 0xBFE78000 -#define SPI_BASE 0xBFE80000 -#define CAN1_BASE 0xBF004300 -#define CAN0_BASE 0xBF004400 +#define GMAC0_BASE 0xBFE10000 +#define GMAC0_DMA_BASE 0xBFE11000 +#define GMAC1_BASE 0xBFE20000 +#define GMAC1_DMA_BASE 0xBFE21000 +#define I2C0_BASE 0xBFE58000 +#define PWM0_BASE 0xBFE5C000 +#define PWM1_BASE 0xBFE5C010 +#define PWM2_BASE 0xBFE5C020 +#define PWM3_BASE 0xBFE5C030 +#define WDT_BASE 0xBFE5C060 +#define RTC_BASE 0xBFE64000 +#define I2C1_BASE 0xBFE68000 +#define I2C2_BASE 0xBFE70000 +#define AC97_BASE 0xBFE74000 +#define NAND_BASE 0xBFE78000 +#define SPI_BASE 0xBFE80000 +#define CAN1_BASE 0xBF004300 +#define CAN0_BASE 0xBF004400 /* Watch Dog registers */ -#define WDT_EN __REG32(WDT_BASE + 0x00) -#define WDT_SET __REG32(WDT_BASE + 0x04) -#define WDT_TIMER __REG32(WDT_BASE + 0x08) +#define WDT_EN __REG32(WDT_BASE + 0x00) +#define WDT_SET __REG32(WDT_BASE + 0x04) +#define WDT_TIMER __REG32(WDT_BASE + 0x08) -#define PLL_FREQ __REG32(0xbfe78030) -#define PLL_DIV_PARAM __REG32(0xbfe78034) +#define PLL_FREQ __REG32(0xbfe78030) +#define PLL_DIV_PARAM __REG32(0xbfe78034) #endif diff --git a/libcpu/mips/loongson_1b/mipscfg.c b/libcpu/mips/loongson_1b/mipscfg.c index 10dd3fee9e..73e9efd965 100644 --- a/libcpu/mips/loongson_1b/mipscfg.c +++ b/libcpu/mips/loongson_1b/mipscfg.c @@ -17,18 +17,18 @@ mips32_core_cfg_t g_mips_core = { - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ }; static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) { - rt_uint16_t rets = 1; + rt_uint16_t rets = 1; while (n--) rets *= b; @@ -38,7 +38,7 @@ static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) static rt_uint16_t m_log2(rt_uint16_t b) { - rt_uint16_t rets = 0; + rt_uint16_t rets = 0; while (b != 1) { @@ -54,29 +54,29 @@ static rt_uint16_t m_log2(rt_uint16_t b) */ void mips32_cfg_init(void) { - rt_uint16_t val; - rt_uint32_t cp0_config1; + rt_uint16_t val; + rt_uint32_t cp0_config1; - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } } diff --git a/libcpu/mips/loongson_1c/cache.c b/libcpu/mips/loongson_1c/cache.c index bf97db9b4e..c755c0e4e8 100644 --- a/libcpu/mips/loongson_1c/cache.c +++ b/libcpu/mips/loongson_1c/cache.c @@ -13,12 +13,12 @@ * 2011-08-08 lgnq modified for LS1B * 2015-07-08 chinesebear modified for loongson 1c */ - + #include <rtthread.h> #include "../common/mipsregs.h" -#define K0BASE 0x80000000 -#define PRID_LS1C 0x4220 +#define K0BASE 0x80000000 +#define PRID_LS1C 0x4220 extern void Clear_TagLo (void); extern void Invalidate_Icache_Ls1c(unsigned int); @@ -27,21 +27,21 @@ extern void Invalidate_Dcache_Fill_Ls1c(unsigned int); extern void Writeback_Invalidate_Dcache(unsigned int); extern void enable_cpu_cache(void); -typedef struct cacheinfo_t +typedef struct cacheinfo_t { - unsigned int icache_size; - unsigned int dcache_size; - unsigned int icacheline_size; - unsigned int dcacheline_size; + unsigned int icache_size; + unsigned int dcache_size; + unsigned int icacheline_size; + unsigned int dcacheline_size; } cacheinfo_t ; -typedef struct cacheop_t +typedef struct cacheop_t { - void (*Clear_TagLo) (void); - void (*Invalidate_Icache) (unsigned int); - void (*Invalidate_Dcache_Fill) (unsigned int); - void (*Invalidate_Dcache_ClearTag) (unsigned int); - void (*Init_Cache)(void); + void (*Clear_TagLo) (void); + void (*Invalidate_Icache) (unsigned int); + void (*Invalidate_Dcache_Fill) (unsigned int); + void (*Invalidate_Dcache_ClearTag) (unsigned int); + void (*Init_Cache)(void); } cacheop_t ; static cacheop_t cacheop, *pcacheop; @@ -54,24 +54,24 @@ int identify_cpu(void) pcacheop = &cacheop; pcacheinfo = &cacheinfo; - rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); + rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); cpu_id = read_c0_prid(); switch (cpu_id) - { - case PRID_LS1C: - rt_kprintf("CPU:Loongson 1C\n"); - pcacheop->Clear_TagLo = Clear_TagLo; - pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c; - pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c; - pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c; - break; - default: - rt_kprintf("Unknown CPU type, system halted!\n"); - while (1) - { - ; - } - break; + { + case PRID_LS1C: + rt_kprintf("CPU:Loongson 1C\n"); + pcacheop->Clear_TagLo = Clear_TagLo; + pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c; + pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c; + pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c; + break; + default: + rt_kprintf("Unknown CPU type, system halted!\n"); + while (1) + { + ; + } + break; } return 0; @@ -90,7 +90,7 @@ void probe_cache(void) icache_sets = 64 << ((config1 >> 22) & 7); icache_ways = 1 + ((config1 >> 16) & 7); icache_size = icache_sets * icache_ways * icache_line_size; - + if ((dcache_line_size = ((config1 >> 10) & 7))) dcache_line_size = 2 << dcache_line_size; else @@ -98,7 +98,7 @@ void probe_cache(void) dcache_sets = 64 << ((config1 >> 13) & 7); dcache_ways = 1 + ((config1 >> 7) & 7); dcache_size = dcache_sets * dcache_ways * dcache_line_size; - + rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size); rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size); @@ -112,122 +112,122 @@ void probe_cache(void) void invalidate_writeback_dcache_all(void) { - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); - while (start < end) - { - Writeback_Invalidate_Dcache(start); //hit writeback invalidate - start += pcacheinfo->dcacheline_size; - } + while (start < end) + { + Writeback_Invalidate_Dcache(start); //hit writeback invalidate + start += pcacheinfo->dcacheline_size; + } } void invalidate_writeback_dcache(unsigned long addr, int size) { - unsigned long start, end; - - start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); - end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); - - while (start <end) - { - Writeback_Invalidate_Dcache(start); - start += pcacheinfo->dcacheline_size; - } + unsigned long start, end; + + start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); + end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); + + while (start <end) + { + Writeback_Invalidate_Dcache(start); + start += pcacheinfo->dcacheline_size; + } } void invalidate_icache_all(void) { - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->icache_size); + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->icache_size); - while (start < end) - { - pcacheop->Invalidate_Icache(start); - start += pcacheinfo->icacheline_size; - } + while (start < end) + { + pcacheop->Invalidate_Icache(start); + start += pcacheinfo->icacheline_size; + } } void invalidate_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - while (start <end) - { - Invalidate_Dcache_Fill_Ls1c(start); - start += pcacheinfo->icacheline_size; - } +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + while (start <end) + { + Invalidate_Dcache_Fill_Ls1c(start); + start += pcacheinfo->icacheline_size; + } } //with cache disabled void init_dcache(void) { - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); - while (start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } + while (start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } } void rt_hw_cache_init(void) { unsigned int start, end; - - /* 1. identify cpu and probe cache */ - identify_cpu(); - probe_cache(); - start = K0BASE; - end = (start + pcacheinfo->icache_size); + /* 1. identify cpu and probe cache */ + identify_cpu(); + probe_cache(); + + start = K0BASE; + end = (start + pcacheinfo->icache_size); /* - * 2. clear CP0 taglo/taghi register; + * 2. clear CP0 taglo/taghi register; */ pcacheop->Clear_TagLo(); - /* - * 3. invalidate instruction cache; + /* + * 3. invalidate instruction cache; */ - while (start < end) + while (start < end) { - pcacheop->Invalidate_Icache(start); //index invalidate icache - start += pcacheinfo->icacheline_size; + pcacheop->Invalidate_Icache(start); //index invalidate icache + start += pcacheinfo->icacheline_size; } /* - * 4. invalidate data cache; + * 4. invalidate data cache; */ start = K0BASE; end = (start + pcacheinfo->dcache_size); - while(start < end) + while(start < end) { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; } start = K0BASE; - while(start < end) + while(start < end) { - pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache - start += pcacheinfo->dcacheline_size; + pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache + start += pcacheinfo->dcacheline_size; } start = K0BASE; - while(start < end) + while(start < end) { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; } - /* enable cache */ - enable_cpu_cache(); - rt_kprintf("enable cpu cache done\n"); + /* enable cache */ + enable_cpu_cache(); + rt_kprintf("enable cpu cache done\n"); - return ; + return ; } diff --git a/libcpu/mips/loongson_1c/cache.h b/libcpu/mips/loongson_1c/cache.h index b5c2d4501e..8ca015ef4f 100644 --- a/libcpu/mips/loongson_1c/cache.h +++ b/libcpu/mips/loongson_1c/cache.h @@ -12,8 +12,8 @@ * 2010-07-09 Bernard first version * 2011-08-08 lgnq modified for LS1B */ -#ifndef __CACHE_H__ -#define __CACHE_H__ +#ifndef __CACHE_H__ +#define __CACHE_H__ /* * Cache Operations @@ -22,31 +22,31 @@ #define Index_Writeback_Inv_D 0x01 #define Index_Invalidate_SI 0x02 #define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 /* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 /* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b +#define Hit_Writeback_SD 0x1b /* 0x1c is unused */ /* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f #endif diff --git a/libcpu/mips/loongson_1c/cpuport.c b/libcpu/mips/loongson_1c/cpuport.c index 03fdc2a514..147f4882bf 100644 --- a/libcpu/mips/loongson_1c/cpuport.c +++ b/libcpu/mips/loongson_1c/cpuport.c @@ -31,13 +31,13 @@ register rt_uint32_t $GP __asm__ ("$28"); */ void rt_hw_cpu_reset(void) { - /* open the watch-dog */ - WDT_EN = 0x01; /* watch dog enable */ - WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ - WDT_SET = 0x01; /* watch dog start */ + /* open the watch-dog */ + WDT_EN = 0x01; /* watch dog enable */ + WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ + WDT_SET = 0x01; /* watch dog start */ - rt_kprintf("reboot system...\n"); - while (1); + rt_kprintf("reboot system...\n"); + while (1); } /** @@ -46,9 +46,9 @@ void rt_hw_cpu_reset(void) */ void rt_hw_cpu_shutdown(void) { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } extern rt_uint32_t cp0_get_cause(void); @@ -68,73 +68,73 @@ extern rt_uint32_t cp0_get_lo(void); */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; static rt_uint32_t g_sr = 0; - static rt_uint32_t g_gp = 0; + static rt_uint32_t g_gp = 0; if (g_sr == 0) { - g_sr = cp0_get_status(); - g_sr &= 0xfffffffe; - g_sr |= 0x8401; + g_sr = cp0_get_status(); + g_sr &= 0xfffffffe; + g_sr |= 0x8401; - g_gp = $GP; + g_gp = $GP; } /** Start at stack top */ stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ - *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ - *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ - *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ - *(--stk) = (rt_uint32_t) texit; /* ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* sp */ - *(--stk) = (rt_uint32_t) g_gp; /* gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ - *(--stk) = (rt_uint32_t) parameter; /* a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ + *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ + *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ + *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ + *(--stk) = (rt_uint32_t) texit; /* ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* sp */ + *(--stk) = (rt_uint32_t) g_gp; /* gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ + *(--stk) = (rt_uint32_t) parameter; /* a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } #define cache_op(op,addr) \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noreorder \n" \ - " .set mips3\n\t \n" \ - " cache %0, %1 \n" \ - " .set pop \n" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))) + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) #if defined(CONFIG_CPU_LOONGSON2) #define Hit_Invalidate_I 0x00 @@ -148,17 +148,17 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad void flush_cache(unsigned long start_addr, unsigned long size) { - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); - while (1) { - cache_op(Hit_Writeback_Inv_D, addr); - cache_op(Hit_Invalidate_I, addr); - if (addr == aend) - break; - addr += lsize; - } + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += lsize; + } } diff --git a/libcpu/mips/loongson_1c/exception.c b/libcpu/mips/loongson_1c/exception.c index 4a3745cbc5..dbcec42ab6 100644 --- a/libcpu/mips/loongson_1c/exception.c +++ b/libcpu/mips/loongson_1c/exception.c @@ -25,7 +25,7 @@ /** * exception handle table */ -#define RT_EXCEPTION_MAX 8 +#define RT_EXCEPTION_MAX 8 exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; /** @@ -47,45 +47,45 @@ exception_func_t rt_set_except_vector(int n, exception_func_t func) void tlb_refill_handler(void) { - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); + rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); } void cache_error_handler(void) { - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); + rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); } static void unhandled_exception_handle(pt_regs_t *regs) { - rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); + rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); } void install_default_execpt_handle(void) { - rt_int32_t i; + rt_int32_t i; - for (i=0; i<RT_EXCEPTION_MAX; i++) - sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; + for (i=0; i<RT_EXCEPTION_MAX; i++) + sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; } void exception_handler(pt_regs_t *regs) { - rt_uint32_t cause; - rt_uint32_t index; + rt_uint32_t cause; + rt_uint32_t index; - cause = (read_c0_cause() & read_c0_config()); - cause = (cause & 0xfc00) >> 8; + cause = (read_c0_cause() & read_c0_config()); + cause = (cause & 0xfc00) >> 8; - for (index = RT_EXCEPTION_MAX; index > 0; index --) - { - if (cause & (1 << index)) - { - sys_exception_handlers[index](regs); - cause &= ~(1 << index); - } - } + for (index = RT_EXCEPTION_MAX; index > 0; index --) + { + if (cause & (1 << index)) + { + sys_exception_handlers[index](regs); + cause &= ~(1 << index); + } + } } /*@}*/ diff --git a/libcpu/mips/loongson_1c/mipscfg.c b/libcpu/mips/loongson_1c/mipscfg.c index 10dd3fee9e..73e9efd965 100644 --- a/libcpu/mips/loongson_1c/mipscfg.c +++ b/libcpu/mips/loongson_1c/mipscfg.c @@ -17,18 +17,18 @@ mips32_core_cfg_t g_mips_core = { - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ }; static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) { - rt_uint16_t rets = 1; + rt_uint16_t rets = 1; while (n--) rets *= b; @@ -38,7 +38,7 @@ static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) static rt_uint16_t m_log2(rt_uint16_t b) { - rt_uint16_t rets = 0; + rt_uint16_t rets = 0; while (b != 1) { @@ -54,29 +54,29 @@ static rt_uint16_t m_log2(rt_uint16_t b) */ void mips32_cfg_init(void) { - rt_uint16_t val; - rt_uint32_t cp0_config1; + rt_uint16_t val; + rt_uint32_t cp0_config1; - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } } diff --git a/libcpu/mips/pic32/cpuport.c b/libcpu/mips/pic32/cpuport.c index 3f08d57167..089f652bce 100644 --- a/libcpu/mips/pic32/cpuport.c +++ b/libcpu/mips/pic32/cpuport.c @@ -45,51 +45,51 @@ rt_uint32_t __attribute__((nomips16)) _get_gp(void) */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; /** Start at stack top */ stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */ - *(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) 0; /* lo */ - *(--stk) = (rt_uint32_t) 0; /* hi */ - *(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */ - *(--stk) = (rt_uint32_t) texit; /* 31 ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */ - *(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */ - *(--stk) = (rt_uint32_t) parameter; /* 4 a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */ + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */ + *(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) 0; /* lo */ + *(--stk) = (rt_uint32_t) 0; /* hi */ + *(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */ + *(--stk) = (rt_uint32_t) texit; /* 31 ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */ + *(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */ + *(--stk) = (rt_uint32_t) parameter; /* 4 a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } |